A dual-path complementary synchronous rectification drive circuit
By using a main control chip with bootstrap and amplification driving capabilities in the synchronous rectifier driver circuit, combined with the second voltage-regulating diode and transistor, the conversion of dual-channel complementary driving is achieved, solving the problems of high cost and difficult design in the prior art, and achieving the effects of low cost and simple structure.
Patent Information
- Application Number
- CN202411530274.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-04-08
AI Technical Summary
The existing synchronous rectifier driver circuits are costly and difficult to design, resulting in increased controller complexity and peripheral driver configuration requirements, thereby increasing overall costs.
A dual-channel complementary synchronous rectification driving circuit is adopted, and a main control chip with bootstrap and amplification driving capabilities is connected to the power supply voltage through the second voltage-regulating diode and transistor, which realizes the inversion and delay of the driving signal, and is converted into a dual-channel complementary driving.
It reduces the design difficulty and cost, realizes the conversion of dual-channel complementary drives, and has the characteristics of simple structure and low cost, and is suitable for reporting synchronous rectification technology.
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Figure CN119787781A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of circuit technology, and in particular to a dual-path complementary synchronous rectification drive circuit. Background Art
[0002] As the power level of power supply technology continues to increase and the power density becomes larger and larger, synchronous rectification technology has outstanding advantages in the design of high-power and high-current power electronic converters. Compared with the traditional diode rectification method, synchronous rectification technology can reduce the conduction loss of power semiconductor devices and improve conversion efficiency. However, the introduction of synchronous rectification technology has increased the difficulty of design. At present, in order to realize the above-mentioned synchronous rectification drive method, a more complex main controller is selected from the beginning of the design, and a controller with at least two PWM outputs or even internal integrated bootstrap drive is often selected. Although the design difficulty is greatly reduced, the increase in the complexity of the controller directly leads to a large increase in cost. In addition, since the main controller itself does not have a large driving capability, a driver still needs to be configured on the periphery.
[0003] Therefore, how to provide a synchronous rectification driving circuit that reduces design difficulty and design cost is a technical issue that needs to be solved urgently in the industry. Summary of the invention
[0004] In view of this, an embodiment of the present invention provides a dual-path complementary synchronous rectification driving circuit to solve the problem of high cost of the synchronous rectification driving circuit in the prior art.
[0005] According to a first aspect, an embodiment of the present invention provides a dual-path complementary synchronous rectification driving circuit, comprising: Main control chip; The main control chip has two input ports, namely the fifth pin and the sixth pin, and two output ports, namely the third pin and the eighth pin, wherein the fifth pin corresponds to the third pin, and the sixth pin corresponds to the eighth pin; The fifth pin is connected to a driving signal through a second voltage stabilizing diode, the driving signal is connected to a cathode of the second voltage stabilizing diode, and an anode of the second voltage stabilizing diode is connected to the fifth pin; The sixth pin is connected to the power supply voltage through the first adjustable resistor, the first voltage regulator diode and the transistor in sequence, the power supply voltage is connected to the collector of the transistor, the base of the transistor is connected to between the drive signal and the cathode of the second voltage regulator diode through the first resistor, the emitter of the transistor is connected to the anode of the first voltage regulator diode, the cathode of the first voltage regulator diode is connected to the sixth pin through the first adjustable resistor, the cathode of the first voltage regulator diode is also grounded through the first capacitor and the second resistor respectively, the first capacitor and the second resistor are connected in parallel between the cathode of the first voltage regulator diode and the grounding end, one end of the first adjustable resistor is connected to the cathode of the first voltage regulator diode, the other end of the first adjustable resistor is connected to the sixth pin and the N-channel MOS transistor, the drain of the N-channel MOS transistor is connected to the first adjustable resistor, the source of the N-channel MOS transistor is grounded, the gate of the N-channel MOS transistor is connected to between the drive signal and the cathode of the second voltage regulator diode through the fourth resistor, and the source and gate of the N-channel MOS transistor are connected between the third resistor.
[0006] In combination with the first aspect, in the first implementation of the first aspect, the sixth pin is grounded through a second capacitor, one end of the second capacitor is connected to the sixth pin, and the other end of the second capacitor is grounded and connected to the supply voltage through a fifth capacitor.
[0007] In combination with the first embodiment of the first aspect, in the second embodiment of the first aspect, a second adjustable resistor is arranged in parallel between the positive and negative electrodes of the second voltage regulator diode, the fifth pin is grounded through a third capacitor, one end of the third capacitor is connected to the fifth pin, and the other end of the third capacitor is respectively grounded and connected to the supply voltage through the fifth capacitor.
[0008] In combination with the first aspect, in a third implementation of the first aspect, the resistance of the second resistor is greater than the resistance of the first adjustable resistor.
[0009] In combination with the first aspect, in a fourth implementation of the first aspect, the first pin of the main control chip is connected to the power supply voltage.
[0010] In combination with the first embodiment of the first aspect, in the fifth embodiment of the first aspect, the ninth pin of the main control chip is respectively grounded and connected to the power supply voltage through a fifth capacitor.
[0011] In combination with the first embodiment of the first aspect, in a sixth embodiment of the first aspect, the seventh pin of the main control chip is respectively grounded and connected to the supply voltage through a fifth capacitor.
[0012] In combination with the first aspect, in a seventh implementation of the first aspect, the second pin and the fourth pin of the main control chip are connected through a fourth capacitor.
[0013] In combination with the first aspect, in an eighth implementation of the first aspect, the main control chip adopts a driver chip with bootstrap and amplification driving capabilities.
[0014] In combination with the first aspect, in a ninth implementation of the first aspect, the driving signal is a PWM signal emitted by a signal generator.
[0015] The dual-path complementary synchronous rectification driving circuit of the present invention selects a driver chip with bootstrap and amplification driving capabilities, and the main control chip has two input ports and two output ports corresponding to the two input ports, wherein the fifth pin as one of the input ports is connected to the driving signal through the second voltage stabilizing diode, and the sixth pin as the other input port is connected to the power supply voltage through the first adjustable resistor, the first voltage stabilizing diode and the transistor in sequence, the power supply voltage is connected to the collector of the transistor, the base of the transistor is connected to between the driving signal and the negative electrode of the second voltage stabilizing diode through the first resistor, and the emitter of the transistor is connected to the positive electrode of the first voltage stabilizing diode. The cathode of the first voltage zener diode is connected to the sixth pin through the first adjustable resistor, the cathode of the first voltage zener diode is also grounded through the first capacitor and the second resistor respectively, the first capacitor and the second resistor are connected in parallel between the cathode of the first voltage zener diode and the grounding end, one end of the first adjustable resistor is connected to the cathode of the first voltage zener diode, the other end of the first adjustable resistor is connected to the sixth pin and the N-channel MOS tube, the drain of the N-channel MOS tube is connected to the first adjustable resistor, the source of the N-channel MOS tube is grounded, the gate of the N-channel MOS tube is connected to between the drive signal and the cathode of the second voltage zener diode through the fourth resistor, and a third resistor is connected between the source and the gate of the N-channel MOS tube. Through such a circuit design, when the driving signal inputs high-level and low-level signals respectively, the voltage on the capacitor C1 is discharged through the second resistor and the first adjustable resistor by correspondingly turning on or off the working state of the N-channel MOS tube and the transistor Q1, and the power supply voltage is sequentially charged to the first capacitor through the transistor and the first voltage regulator diode to a corresponding voltage value. Correspondingly, the sixth pin of the main control chip inputs a low-level signal, and the eighth pin outputs a low-level signal, or the voltage on the first capacitor is discharged through the second resistor and the first adjustable resistor, and the corresponding sixth pin input voltage of the main control chip is a high-level power supply voltage, and the eighth pin outputs a high-level signal. Through the above-mentioned external processing method, the drive is inverted and delayed to realize the conversion of one-way drive into a dual-way complementary drive, and it has the characteristics of low cost and simple structure, and is more suitable for application in the synchronous rectification technology. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0017] in: Figure 1 The circuit diagram of the dual-path complementary synchronous rectification driving circuit provided by the present invention is shown. DETAILED DESCRIPTION
[0018] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
[0019] As the power level of power supply technology continues to increase and the power density becomes larger and larger, synchronous rectification technology has outstanding advantages in the design of high-power, high-current power electronic converters. Compared with the traditional diode rectification method, synchronous rectification technology can reduce the conduction loss of power semiconductor devices and improve conversion efficiency. However, the introduction of synchronous rectification technology has increased the difficulty of design. This is because synchronous rectification requires an additional drive circuit, and there is often a floating drive situation. In addition, there is a strict timing control between the drive of the synchronous rectification and the drive of the main switch tube. The most common is that the drive of the main switch tube complements the drive of the synchronous rectification to ensure stable operation, and there is a certain dead zone.
[0020] At present, in order to realize the above-mentioned synchronous rectification driving mode, a more complex main controller is selected from the beginning of the design. Most of the controllers have at least two PWM outputs or even internal integrated bootstrap drive. Although the design difficulty is greatly reduced, the increase in the complexity of the controller directly leads to a large increase in cost. In addition, since the main controller itself does not have a large driving capability, the periphery still needs to be configured with a driver, which invisibly increases the overall cost.
[0021] Therefore, how to provide a synchronous rectification driving circuit that reduces design difficulty and design cost is a technical issue that needs to be solved urgently in the industry.
[0022] In order to solve the above problems, a dual-path complementary synchronous rectification driving circuit is provided in this specification. Figure 1 As shown, the circuit may include: The main control chip U1 is a driver chip with bootstrap and amplification driving capabilities.
[0023] like Figure 1 As shown, the main control chip has two input ports, the fifth pin H1 and the sixth pin L1, and correspondingly has two output ports, the third pin HO and the eighth pin LO. The fifth pin H1 corresponds to the third pin HO, and the sixth pin L1 corresponds to the eighth pin LO. The third pin HO and the eighth pin LO are respectively used to drive the main switch and the synchronous rectifier tube, wherein the third pin HO is a floating ground drive, and the reference ground is HS. During use, the third pin HO and the eighth pin LO can be selected according to the topology requirements to drive the corresponding switch tube. V CC represents the supply voltage, D1 represents the first voltage-stabilizing diode, D2 represents the second voltage-stabilizing diode, Q1 represents the transistor, Q2 represents the N-channel MOS tube, and the driving signal is the PWM signal emitted by the signal generator, that is, Figure 1 PWM identified in .
[0024] The sixth pin L1 is connected to the power supply voltage V via the first adjustable resistor R5, the first voltage stabilizing diode D1 and the transistor Q1 in sequence. CC Connection, supply voltage V CC The collector of the transistor Q1 is connected, the base of the transistor Q1 is connected to the drive signal and the cathode of the second voltage zener diode D2 through the first resistor R1, the emitter of the transistor Q1 is connected to the anode of the first voltage zener diode D1, the cathode of the first voltage zener diode D1 is connected to the sixth pin L1 through the first adjustable resistor R5, and the cathode of the first voltage zener diode D1 is also grounded through the first capacitor C1 and the second resistor R2, wherein the first capacitor C1 and the second resistor R2 are connected in parallel to the cathode of the first voltage zener diode D1 and The first adjustable resistor R5 is connected to the cathode of the first voltage zener diode D1, the other end of the first adjustable resistor R5 is connected to the sixth pin L1 and the N-channel MOS tube Q2, the drain of the N-channel MOS tube Q2 is connected to the first adjustable resistor R5, the source of the N-channel MOS tube Q2 is grounded, the gate of the N-channel MOS tube Q2 is connected to the driving signal and the cathode of the second voltage zener diode D2 through the fourth resistor R6, and the third resistor R4 is connected between the source and the gate of the N-channel MOS tube Q2.
[0025] The sixth pin L1 is grounded through the second capacitor C2, one end of the second capacitor C2 is connected to the sixth pin L1, and the other end of the second capacitor C2 is grounded and connected to the supply voltage V through the fifth capacitor C5. CC connect.
[0026] A second adjustable resistor R3 is connected in parallel between the positive and negative electrodes of the second voltage stabilizing diode D2. The fifth pin H1 is grounded through a third capacitor C3. One end of the third capacitor C3 is connected to the fifth pin H1. The other end of the third capacitor C3 is grounded and connected to the supply voltage V through a fifth capacitor C5. CC connect.
[0027] In this embodiment, the resistance of the second resistor R2 is greater than the resistance of the first adjustable resistor R5 and the resistance of the second resistor R2 is selected to be larger. Specifically, the resistance of the second resistor R2 needs to be greater than the preset resistance.
[0028] In this embodiment, the main control chip U1 has a total of nine pins, and the connection method of the other pins is as follows: The first pin VDD of the main control chip U1 is connected to the power supply voltage V CC The ninth pin PAD of the main control chip U1 is connected to the ground and connected to the supply voltage V through the fifth capacitor C5. CC The seventh pin VSS of the main control chip U1 is connected to the ground and connected to the supply voltage V through the fifth capacitor C5. CC Connection: The second pin HB and the fourth pin HS of the main control chip U1 are connected through a fourth capacitor C4.
[0029] When the circuit works: when Figure 1 When the PWM signal inputted into the main control chip U1 is a high-level signal, the fifth pin of the main control chip U1 inputs a high-level signal, and the third pin outputs a high-level signal. At this time, because the PWM signal is a high-level signal, the N-channel MOS tube Q2 is turned on, and the drain of the N-channel MOS tube Q2 is pulled down to the ground. Therefore, the sixth pin of the main control chip U1 inputs a low-level signal, and the eighth pin outputs a low-level signal. At the same time, the transistor Q1 is also in the on state, and the power supply voltage V CC The first capacitor C1 is charged to a corresponding voltage value through the transistor Q1 and the first voltage stabilizing diode D1 in sequence.
[0030] On the contrary, when Figure 1 When the PWM signal inputted in is a low-level signal, the fifth pin of the main control chip U1 inputs a low-level signal, and the third pin outputs a low-level signal. At this time, because the PWM signal is a low-level signal, the N-channel MOS tube Q2 is in the off state, and at the same time, the transistor Q1 is also in the off state, and the voltage on the capacitor C1 is discharged through the second resistor R2 and the first adjustable resistor R5. At the same time, because the resistance value of the second resistor R2 is greater than the resistance value of the first adjustable resistor R5 and the resistance value of the second resistor R2 is selected to be larger, the voltage on the capacitor C1 will have a certain maintenance time, and the amplitude is V CC Therefore, the input voltage of the sixth pin of the main control chip U1 is the high-level power supply voltage VCC , the eighth pin outputs a high level signal.
[0031] Through the above method, one-way drive can be converted into two-way complementary drive. In addition, by adjusting the values of the first adjustable resistor R5, the second adjustable resistor R3, the second capacitor C2 and the third capacitor C3, the rising speed of the signal rising edge of the fifth pin and the sixth pin of the input port of the main control chip U1 can be adjusted respectively, so as to achieve the delay processing of the corresponding control signal, so as to achieve the purpose of adjusting the dead zone, wherein the first adjustable resistor R5 and the second capacitor C2 are a control group, and the second adjustable resistor R3 and the third capacitor C3 are another control group. The second voltage stabilizing diode D2 can quickly discharge the third capacitor C3 when the PWM signal changes from a high level to a low level, so that the falling edge of the driving signal drops quickly to prevent tailing, and thus can also play a role in preventing false connection. When the second capacitor C2 is discharged, the conduction of the N-channel MOS tube Q2 is used to achieve rapid conduction.
[0032] The dual-path complementary synchronous rectification driving circuit of the present invention selects a driver chip with bootstrap and amplification driving capabilities, and the main control chip has two input ports and two output ports corresponding to the two input ports, wherein the fifth pin as one of the input ports is connected to the driving signal through the second voltage stabilizing diode, and the sixth pin as the other input port is connected to the power supply voltage through the first adjustable resistor, the first voltage stabilizing diode and the transistor in sequence, the power supply voltage is connected to the collector of the transistor, the base of the transistor is connected to between the driving signal and the negative electrode of the second voltage stabilizing diode through the first resistor, and the emitter of the transistor is connected to the positive electrode of the first voltage stabilizing diode. The cathode of the first voltage zener diode is connected to the sixth pin through the first adjustable resistor, the cathode of the first voltage zener diode is also grounded through the first capacitor and the second resistor respectively, the first capacitor and the second resistor are connected in parallel between the cathode of the first voltage zener diode and the grounding end, one end of the first adjustable resistor is connected to the cathode of the first voltage zener diode, the other end of the first adjustable resistor is connected to the sixth pin and the N-channel MOS tube, the drain of the N-channel MOS tube is connected to the first adjustable resistor, the source of the N-channel MOS tube is grounded, the gate of the N-channel MOS tube is connected to between the drive signal and the cathode of the second voltage zener diode through the fourth resistor, and a third resistor is connected between the source and the gate of the N-channel MOS tube. Through such a circuit design, when the driving signal inputs high-level and low-level signals respectively, the voltage on the capacitor C1 is discharged through the second resistor and the first adjustable resistor by correspondingly turning on or off the working state of the N-channel MOS tube and the transistor Q1, and the power supply voltage is sequentially charged to the first capacitor through the transistor and the first voltage regulator diode to a corresponding voltage value. Correspondingly, the sixth pin of the main control chip inputs a low-level signal, and the eighth pin outputs a low-level signal, or the voltage on the first capacitor is discharged through the second resistor and the first adjustable resistor, and the corresponding sixth pin input voltage of the main control chip is a high-level power supply voltage, and the eighth pin outputs a high-level signal. Through the above-mentioned external processing method, the drive is inverted and delayed to realize the conversion of one-way drive into a dual-way complementary drive, and it has the characteristics of low cost and simple structure, and is more suitable for application in the synchronous rectification technology.
[0033] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.
[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A dual-path complementary synchronous rectification drive circuit, characterized in that: include: Main control chip; The main control chip has two input ports, namely the fifth pin and the sixth pin, and two output ports, namely the third pin and the eighth pin, wherein the fifth pin corresponds to the third pin, and the sixth pin corresponds to the eighth pin; The fifth pin is connected to a driving signal through a second voltage stabilizing diode, the driving signal is connected to a cathode of the second voltage stabilizing diode, and an anode of the second voltage stabilizing diode is connected to the fifth pin; The sixth pin is connected to the power supply voltage through the first adjustable resistor, the first voltage regulator diode and the transistor in sequence, the power supply voltage is connected to the collector of the transistor, the base of the transistor is connected to between the drive signal and the cathode of the second voltage regulator diode through the first resistor, the emitter of the transistor is connected to the anode of the first voltage regulator diode, the cathode of the first voltage regulator diode is connected to the sixth pin through the first adjustable resistor, the cathode of the first voltage regulator diode is also grounded through the first capacitor and the second resistor respectively, the first capacitor and the second resistor are connected in parallel between the cathode of the first voltage regulator diode and the grounding end, one end of the first adjustable resistor is connected to the cathode of the first voltage regulator diode, the other end of the first adjustable resistor is connected to the sixth pin and the N-channel MOS transistor, the drain of the N-channel MOS transistor is connected to the first adjustable resistor, the source of the N-channel MOS transistor is grounded, the gate of the N-channel MOS transistor is connected to between the drive signal and the cathode of the second voltage regulator diode through the fourth resistor, and the source and gate of the N-channel MOS transistor are connected between the third resistor.
2. The dual-path complementary synchronous rectification driving circuit according to claim 1, characterized in that: The sixth pin is grounded through a second capacitor, one end of the second capacitor is connected to the sixth pin, and the other end of the second capacitor is grounded and connected to a supply voltage through a fifth capacitor.
3. The dual-path complementary synchronous rectification driving circuit according to claim 2, characterized in that: A second adjustable resistor is arranged in parallel between the positive and negative electrodes of the second voltage regulator diode, the fifth pin is grounded through a third capacitor, one end of the third capacitor is connected to the fifth pin, and the other end of the third capacitor is respectively grounded and connected to the supply voltage through the fifth capacitor.
4. The dual-path complementary synchronous rectification driving circuit according to claim 1, characterized in that: The resistance of the second resistor is greater than the resistance of the first adjustable resistor.
5. The dual-path complementary synchronous rectification driving circuit according to claim 1, characterized in that: The first pin of the main control chip is connected to the power supply voltage.
6. The dual-path complementary synchronous rectification driving circuit according to claim 2, characterized in that: The ninth pin of the main control chip is grounded and connected to the supply voltage through the fifth capacitor.
7. The dual-path complementary synchronous rectification driving circuit according to claim 2, characterized in that: The seventh pin of the main control chip is respectively grounded and connected to the supply voltage through the fifth capacitor.
8. The dual-path complementary synchronous rectification driving circuit according to claim 1, characterized in that: The second pin and the fourth pin of the main control chip are connected via a fourth capacitor.
9. The dual-path complementary synchronous rectification driving circuit according to claim 1, characterized in that: The main control chip adopts a driver chip with bootstrap and amplification driving capabilities.
10. The dual-path complementary synchronous rectification driving circuit according to claim 1, characterized in that: The driving signal is a PWM signal sent by a signal generator.