Electrostatic protection circuit and electronic equipment

Abstract

The present application provides an electrostatic protection circuit and an electronic device, wherein the electrostatic protection circuit includes: a detection module, the detection module is used to output an enable signal when an electrostatic pulse is input to the positive input terminal of a power supply; a clamping module, the clamping module is used to discharge the electrostatic pulse at the positive input terminal of the power supply to the negative input terminal of the power supply in response to the enable signal; wherein the clamping module includes a plurality of clamping transistors connected in series between the positive input terminal of the power supply and the negative input terminal of the power supply, and the maximum source-drain voltage of the clamping transistor is less than or equal to a preset value; the detection module includes at least one detection unit, each detection unit is connected in parallel between the positive input terminal of the power supply and the negative input terminal of the power supply, and each clamping transistor is turned on in response to the enable signal output by the same or different detection units. The present application adopts a plurality of low-voltage clamping transistors connected in series to replace the traditional high-voltage transistor, which is conducive to quickly discharging the electrostatic pulse current and reducing the circuit area of ​​the electrostatic protection circuit.

Description

Technical Field

[0001] The present application relates to the technical field of electrostatic protection, and in particular to an electrostatic protection circuit and an electronic device. Background Art

[0002] At present, in order to prevent electrostatic pulses from causing circuit damage, an electrostatic protection circuit is usually set at the output port of a high-voltage power supply or the input port of an integrated circuit corresponding to the high-voltage power supply, so that the electrostatic pulses input by the high-voltage power supply can be discharged through the electrostatic protection circuit, thereby achieving the purpose of electrostatic protection of the circuit.

[0003] In the related technology, the electrostatic protection circuit usually uses a high-voltage transistor to discharge the electrostatic pulse in the high-voltage power supply. Although the voltage resistance of the high-voltage transistor can meet the requirements of the high-voltage power supply, the high-voltage transistor has a large on-resistance, which leads to the problem that the high-voltage transistor cannot quickly discharge the electrostatic pulse current. Summary of the invention

[0004] The present application provides an electrostatic protection circuit and an electronic device to solve the above technical problems.

[0005] In a first aspect, the present application provides an electrostatic protection circuit, comprising:

[0006] A detection module, the detection module is used to output an enable signal when an electrostatic pulse is input to the positive input terminal of the power supply;

[0007] A clamping module, the clamping module is used to discharge the electrostatic pulse at the positive input terminal of the power supply to the negative input terminal of the power supply in response to an enable signal;

[0008] Wherein, the clamping module includes a plurality of clamping transistors connected in series between the positive input terminal of the power supply and the negative input terminal of the power supply, and the maximum source-drain voltage of the clamping transistor is less than or equal to a preset value;

[0009] The detection module includes at least one detection unit, each detection unit is connected in parallel between a positive power input terminal and a negative power input terminal, and each clamp transistor is turned on in response to an enable signal output by the same or different detection units.

[0010] In some embodiments, the electrostatic protection circuit further includes a trigger module;

[0011] The trigger module is used to output a control signal according to the enable signal output by the detection unit, and the control signal is used to control the clamp transistor to be turned on, so that each clamp transistor is turned on in response to the enable signal output by the detection unit.

[0012] In some embodiments, the detection unit includes a first resistor and a first capacitor;

[0013] The first end of the first resistor is connected to the positive input terminal of the power supply, the second end of the first resistor is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the negative input terminal of the power supply.

[0014] In some embodiments, the trigger module includes a first PMOS transistor and a first NMOS transistor;

[0015] The first end of the first PMOS tube is connected to the positive input end of the power supply, the second end of the first PMOS tube is connected to the second end of the first NMOS tube, and the first end of the first NMOS tube is connected to the negative input end of the power supply;

[0016] The control ends of the first PMOS tube and the first NMOS tube are connected to a first node between the first resistor and the first capacitor, and the control end of each clamping transistor is connected to a second node between the first PMOS tube and the first NMOS tube.

[0017] In some embodiments, the trigger module includes a plurality of trigger units connected in series between the positive input terminal of the power supply and the negative input terminal of the power supply, and the trigger units correspond one to one with the clamp transistors;

[0018] The trigger unit is used for outputting a control signal to the corresponding clamp transistor according to the enable signal output by the detection unit.

[0019] In some embodiments, each trigger unit includes a first PMOS transistor and a second resistor, and the first PMOS transistor and the second resistor are connected in series;

[0020] The control end of each first PMOS tube is connected to a first node between the first resistor and the first capacitor, and the control end of each clamping transistor is connected to a second node between the first PMOS tube and the second resistor.

[0021] In some embodiments, the detection unit includes a first resistor and a first capacitor;

[0022] The first end of the first capacitor is connected to the positive input end of the power supply, the second end of the first capacitor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the negative input end of the power supply.

[0023] In some embodiments, the trigger module includes a plurality of trigger units connected in series between the positive input terminal of the power supply and the negative input terminal of the power supply, and the trigger units correspond one to one with the clamp transistors;

[0024] Each trigger unit includes a first NMOS tube and a second resistor, and the first NMOS tube is connected in series with the second resistor;

[0025] The control end of each first NMOS tube is connected to a first node between the first resistor and the first capacitor, and the control end of each clamping transistor is connected to a second node between the first NMOS tube and the second resistor.

[0026] In some embodiments, the trigger module includes a plurality of trigger units, the detection module includes a plurality of detection units, and the detection units, the trigger units, and the clamp transistors correspond one to one;

[0027] A plurality of trigger units are connected in series between the positive power input terminal and the negative power input terminal. Each trigger unit is used for outputting a control signal according to an enable signal output by a corresponding detection unit to control the corresponding clamp transistor to be turned on.

[0028] In some embodiments, the plurality of trigger units include a first trigger unit and a second trigger unit, the plurality of detection units include a first detection unit and a second detection unit, and the plurality of clamp transistors include a first clamp transistor and a second clamp transistor;

[0029] The first detection unit is used to output a first enable signal when an electrostatic pulse is input to the positive input terminal of the power supply, and the first trigger unit is used to output a first control signal according to the first enable signal output by the first detection unit, and the first control signal is used to control the first clamp transistor to be turned on;

[0030] The second detection unit is used to output a second enable signal when an electrostatic pulse is input to the positive input terminal of the power supply. The second trigger unit is used to output a second control signal according to the second enable signal output by the second detection unit. The second control signal is used to control the conduction of the second clamp transistor.

[0031] In some embodiments, the first detection unit includes a first resistor and a first capacitor, and the second detection unit includes a second resistor and a second capacitor;

[0032] A first end of the first resistor is connected to the positive input terminal of the power supply, a second end of the first resistor is connected to the first end of the first capacitor, and a second end of the first capacitor is connected to the negative input terminal of the power supply;

[0033] The first end of the second capacitor is connected to the positive input end of the power supply, the second end of the second capacitor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the negative input end of the power supply.

[0034] In some embodiments, the first trigger unit includes a first PMOS transistor and a third resistor, and the second trigger unit includes a first NMOS transistor and a fourth resistor;

[0035] The first PMOS transistor, the third resistor, the first NMOS transistor and the fourth resistor are sequentially connected in series between the positive input terminal of the power supply and the negative input terminal of the power supply;

[0036] The control end of the first PMOS tube is connected to a first node between the first resistor and the first capacitor, and the control end of the first clamping transistor is connected to a third node between the first PMOS tube and the third resistor;

[0037] The control end of the first NMOS transistor is connected to a second node between the second resistor and the second capacitor, and the control end of the second clamp transistor is connected to a fourth node between the first NMOS transistor and the fourth resistor.

[0038] In some embodiments, a first terminal of the first clamp transistor is connected to a positive input terminal of a power supply, and a second terminal of the first clamp transistor is connected to an intermediate node between the third resistor and the first NMOS transistor;

[0039] The first end of the second clamping transistor is connected to the middle node between the third resistor and the first NMOS transistor, and the second end of the second clamping transistor is connected to the negative input end of the power supply.

[0040] In some embodiments, the electrostatic protection circuit further includes a first bias resistor and a second bias resistor;

[0041] A first end of the first bias resistor is connected to the positive input end of the power supply, and a second end of the first bias resistor is connected to an intermediate node between the third resistor and the first NMOS transistor;

[0042] The first end of the second bias resistor is connected to the middle node between the third resistor and the first NMOS tube, and the second end of the second bias resistor is connected to the negative input end of the power supply.

[0043] In a second aspect, the present application provides an electronic device, comprising the electrostatic protection circuit as described in the first aspect.

[0044] In the present application, when an electrostatic pulse is input to the positive input terminal of the power supply, the detection module can output an enable signal, so that the clamping module can discharge the electrostatic pulse at the positive input terminal of the power supply to the negative input terminal of the power supply in response to the enable signal, so as to achieve the purpose of electrostatic pulse protection. In the present application, the clamping module includes a plurality of clamping transistors connected in series between the positive input terminal of the power supply and the negative input terminal of the power supply, and the maximum source-drain voltage of the clamping transistor is less than or equal to a preset value, that is, the present application uses a plurality of low-voltage clamping transistors connected in series to replace the traditional high-voltage transistor. Due to the characteristics of the low-voltage clamping transistor having a small on-resistance and a small circuit area, it can ensure that the clamping module can quickly discharge the electrostatic pulse current and reduce the circuit area of ​​the electrostatic protection circuit.

[0045] At the same time, since the detection module includes at least one detection unit, each detection unit is connected in parallel between the positive power input terminal and the negative power input terminal, the enable signal output by each detection unit is directly related to the electrostatic pulse. Then, for multiple clamp transistors connected in series, each clamp transistor can be turned on in response to the enable signal output by the same or different detection units, thereby ensuring that each clamp transistor in the multiple clamp transistors connected in series is better turned on. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 A schematic diagram of an electrostatic protection circuit in the related art is shown;

[0048] Figure 2 A schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0049] Figure 3 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0050] Figure 4 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0051] Figure 5 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0052] Figure 6 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0053] Figure 7 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0054] Figure 8 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0055] Fig. 9 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0056] Fig.10 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0057] Fig.11 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0058] Fig.12 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0059] Fig.13 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0060] Fig.14 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0061] Fig.15 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0062] Fig.16 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown;

[0063] Fig.17 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown.

[0064] Among them, 10 is a detection module, 11 is a detection unit, 111 is a first detection unit, 112 is a second detection unit, 20 is a clamping module, 30 is a triggering module, 31 is a triggering unit, a first triggering unit 311, and a second triggering unit 312;

[0065] Power positive input terminal Power, power negative input terminal Gound, enable signal EN, first enable signal EN1, second enable signal EN2, clamp transistor M0, first clamp transistor M1, second clamp transistor M2, control signal VC, first control signal VC1, second control signal VC2, first resistor R1, first capacitor C1, first node M1, first PMOS tube MP1, first NMOS tube MN1, second node M2, second resistor R2, third resistor R3, fourth resistor R4, third node M3, fourth node M4, second capacitor C2, intermediate node MO, first bias resistor R01, second bias resistor R02. DETAILED DESCRIPTION

[0066] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0067] In the description of the present invention, the word "exemplary" is used to mean "used as an example, illustration, or description". Any embodiment described in this application as "exemplary" is not necessarily to be construed as being preferred or advantageous over other embodiments. The following description is given to enable any person skilled in the art to implement and use the present invention. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present invention can be implemented without using these specific details. In other instances, well-known structures and processes are not elaborated in detail to avoid obscuring the description of the present invention with unnecessary details. Therefore, the present invention is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in this application.

[0068] At present, in order to prevent the circuit from being damaged by electrostatic pulses, an electrostatic protection circuit is usually set at the output port of the high-voltage power supply or the input port of the integrated circuit corresponding to the high-voltage power supply. Figure 1 , Figure 1 A schematic diagram of an electrostatic protection circuit in the related art is shown, wherein the electrostatic protection circuit includes a detection circuit composed of a resistor R0 and a capacitor C0, a trigger circuit composed of a PMOS tube MP0 and an NMOS tube MN0, and a high-voltage discharge transistor M.

[0069] When an electrostatic pulse appears in the input voltage of the power input terminal V+, the electrostatic pulse charges the capacitor C0 through the resistor R0. When the capacitor C0 is overcharged, the PMOS tube MP0 is turned on and the NMOS tube MN0 is turned off, so the high-voltage discharge transistor M can be controlled to be turned on, so that the electrostatic pulse is discharged through the high-voltage discharge transistor M, and finally the electrostatic protection purpose of the subsequent circuit is achieved. However, although the voltage resistance of the high-voltage transistor can meet the requirements of the high-voltage power supply, the high-voltage transistor has a large on-resistance, which leads to the problem that the high-voltage transistor cannot quickly discharge the electrostatic pulse current.

[0070] To this end, the embodiments of the present application provide an electrostatic protection circuit and an electronic device, which are described in detail below.

[0071] First, see Figure 2 , Figure 2 A schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown, wherein the electrostatic protection circuit includes a detection module 10 and a clamping module 20 .

[0072] Specifically, the detection module 10 is used to output an enable signal EN when an electrostatic pulse is input to the positive input terminal Power of the power supply, so that the clamping module 20 discharges the electrostatic pulse of the positive input terminal Power of the power supply to the negative input terminal Gound of the power supply through the enable signal EN. In some embodiments of the present application, the detection module 10 may include a capacitor, and the enable signal EN may be an electrical signal of the capacitor charging process when an electrostatic pulse is input to the positive input terminal. In some embodiments of the present application, the detection module 10 may include a voltage comparison circuit (e.g., a hysteresis comparator), and the voltage comparison circuit compares the voltage of the positive input terminal Power of the power supply with a reference voltage. When the voltage of the positive input terminal Power of the power supply is greater than the reference voltage, it indicates that an electrostatic pulse exists, so the voltage comparison circuit can output a level signal (e.g., a high level signal) as the enable signal EN.

[0073] It is understandable that the implementation of the detection module 10 is not limited thereto. In some possible embodiments, the detection module 10 may also determine whether an electrostatic pulse exists by detecting the magnitude of the current.

[0074] The clamp module 20 can discharge the electrostatic pulse of the positive input terminal Power of the power supply to the negative input terminal Gound of the power supply in response to the enable signal EN, so that the electrostatic pulse can be discharged and the subsequent circuit can be protected. In some embodiments of the present application, the enable signal EN can directly control the clamp module 20, so that the clamp module 20 discharges the electrostatic pulse of the positive input terminal Power of the power supply to the negative input terminal Gound of the power supply. In some embodiments of the present application, the enable signal EN can indirectly control the clamp module 20, for example, the enable signal EN of the detection module 10 can be input to the inverter, and the inverter outputs a control signal to control the clamp module 20.

[0075] In an embodiment of the present application, the clamping module 20 includes a plurality of clamping transistors M0 connected in series between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply, and the maximum source-drain voltage of the clamping transistor M0 is less than or equal to a preset value. It should be noted that the preset value referred to in the present application is less than the maximum source-drain voltage of any high-voltage transistor, that is, the plurality of clamping transistors M0 connected in series between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply are low-voltage transistors. Compared with the conventional scheme of using high-voltage transistors to discharge electrostatic pulses, the present application uses a plurality of low-voltage clamping transistors M0 connected in series to replace the conventional high-voltage transistors. Due to the characteristics of the low-voltage clamping transistor M0 having a small on-resistance and a small circuit area, it is possible to ensure that the clamping module 20 discharges the electrostatic pulse current quickly and reduces the circuit area of ​​the electrostatic protection circuit.

[0076] At the same time, the detection module 10 includes at least one detection unit 11, each detection unit 11 is connected in parallel between the positive power input terminal and the negative power input terminal Gound, and each detection unit 11 directly outputs an enable signal EN based on the electrostatic pulse. Therefore, the enable signal EN output by each detection unit 11 is directly related to the electrostatic pulse. Then, for multiple clamp transistors M0 connected in series, each clamp transistor M0 can be turned on in response to the enable signal EN output by the same or different detection units 11, thereby ensuring that each clamp transistor M0 in the multiple clamp transistors M0 connected in series is better turned on, avoiding the phenomenon that multiple clamp transistors M0 connected in series cannot be turned on.

[0077] In some embodiments of the present application, for example, the enable signal EN can indirectly control the clamp module 20, see Figure 3 , Figure 3 Another schematic diagram of the electrostatic protection circuit in an embodiment of the present application is shown, wherein the electrostatic protection circuit also includes a trigger module 30, the trigger module 30 is used to output a control signal VC according to the enable signal EN output by the detection unit 11, and the control signal VC is used to control each clamping transistor M0 to be turned on, so that each clamping transistor M0 is turned on in response to the enable signal EN output by the first detection unit 111.

[0078] It should be noted that, in some embodiments, for example, the enable signal EN may refer to an electrical signal of a capacitor charged when an electrostatic pulse is input to the positive input terminal. Since the electrical signal of the capacitor charging is not stable, this may cause the clamping transistor M0 to fail to turn on in time when an electrostatic pulse occurs. In the above embodiment, by further providing a trigger module 30, the trigger module 30 can output a stable control signal VC through the unstable enable signal EN, thereby ensuring that the clamping transistor M0 is stably turned on and discharges the electrostatic pulse current.

[0079] As an exemplary embodiment of the trigger unit 31, see Figure 4 , Figure 4 Another schematic diagram of the electrostatic protection circuit in the embodiment of the present application is shown, wherein the detection unit 11 includes a first resistor R1 and a first capacitor C1; the first end of the first resistor R1 is connected to the positive input terminal Power of the power supply, the second end of the first resistor R1 is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected to the negative input terminal Gound of the power supply. Specifically, when an electrostatic pulse is input to the positive input terminal Power of the power supply, the electrostatic pulse will charge the first capacitor C1 through the first resistor R1, and the voltage of the first node M1 between the first resistor R1 and the first capacitor C1 will increase. Therefore, the trigger module 30 can output a stable control signal VC according to the increased voltage signal of the first node M1, thereby controlling the clamping transistor M0 to turn on and discharge the electrostatic pulse current.

[0080] In some embodiments of the present application, for example, for an embodiment in which each clamp transistor M0 is turned on in response to an enable signal EN output by the same detection unit 11, see Figure 5 , Figure 5 Another schematic diagram of the electrostatic protection circuit in the embodiment of the present application is shown, wherein the trigger module 30 includes a first PMOS tube MP1 and a first NMOS tube MN1; the first end of the first PMOS tube MP1 is connected to the positive input terminal Power of the power supply, the second end of the first PMOS tube MP1 is connected to the second end of the first NMOS tube MN1, and the first end of the first NMOS tube MN1 is connected to the negative input terminal Gound of the power supply; the control ends of the first PMOS tube MP1 and the first NMOS tube MN1 are connected to the first node M1 between the first resistor R1 and the first capacitor C1, and the control end of each clamping transistor M0 is connected to the second node M2 ​​between the first PMOS tube MP1 and the first NMOS tube MN1.

[0081] It should be noted that, when the electrostatic pulse causes the voltage of the first node M1 to increase, the gate voltages of the first PMOS tube MP1 and the first NMOS tube MN1 are lower than the source voltage, so the first PMOS tube MP1 is turned on and the first NMOS tube MN1 is turned off, so that the second node M2 ​​between the first PMOS tube MP1 and the first NMOS tube MN1 is in a high level state, and the voltage of the second node M2 ​​can turn on the multiple series clamping transistors M0 and discharge the electrostatic pulse, and it can be seen that the multiple series clamping transistors M0 are turned on in response to the enable signal EN output by the same detection unit 11.

[0082] Understandably, in Figure 5 In the figure, the clamping transistor M0 is taken as a low-voltage NMOS tube for exemplary description. In some possible embodiments, the clamping transistor M0 may also be a low-voltage PMOS tube.

[0083] It should be noted that the first pole / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain.

[0084] In some embodiments of the present application, for example, for an embodiment in which each clamp transistor M0 is turned on in response to an enable signal EN output by the same detection unit 11, see Figure 6 , Figure 6 Another schematic diagram of the electrostatic protection circuit in an embodiment of the present application is shown, wherein the trigger module 30 includes a plurality of trigger units 31 connected in series between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply, and the trigger unit 31 corresponds one-to-one to the clamping transistor M0; the trigger unit 31 is used to output a control signal VC to the corresponding clamping transistor M0 according to the enable signal EN output by the detection unit 11.

[0085] It should be noted that, since multiple clamp transistors M0 are connected in series, the source voltage of each clamp transistor M0 is not the same. If the same control signal VC is used to control the gate voltage of each clamp transistor M0, there may be a phenomenon that multiple clamp transistors M0 connected in series are turned on unevenly. In the above embodiment, since the trigger module 30 includes multiple trigger units 31 connected in series between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply, each trigger unit 31 can output a control signal VC to the corresponding clamp transistor M0 according to the enable signal EN output by the detection unit 11, and according to the series voltage division principle, it can be known that the voltage of the control signal VC output by each trigger unit 31 is not equal. Combined with the different source voltages of each clamp transistor M0, this can make the source and gate voltage difference of each clamp transistor M0 basically equivalent, so that multiple clamp transistors M0 connected in series are evenly turned on, and finally achieve a better electrostatic pulse discharge effect.

[0086] As an exemplary embodiment of the trigger unit 31, see Figure 7 , Figure 7 Another schematic diagram of the electrostatic protection circuit in an embodiment of the present application is shown, wherein each trigger unit 31 includes a first PMOS tube MP1 and a second resistor R2, and the first PMOS tube MP1 is connected in series with the second resistor R2; the control end of each first PMOS tube MP1 is connected to the first node M1 between the first resistor R1 and the first capacitor C1, and the control end of each clamping transistor M0 is connected to the second node M2 ​​between the first PMOS tube MP1 and the second resistor R2.

[0087] Specifically, when the electrostatic pulse causes the voltage of the first node M1 to increase, the first PMOS tube MP1 of each trigger unit 31 is turned on, so the second node M2 ​​between the first PMOS tube MP1 and the second resistor R2 in the trigger unit 31 presents a high level. According to the principle of resistance voltage division, it can be seen that the voltage of the second node M2 ​​in each trigger unit 31 is not equal. Combined with the fact that the source voltage of each clamping transistor M0 is not the same, it can be seen that the source and gate voltage difference of each clamping transistor M0 is basically the same, so that multiple clamping transistors M0 connected in series can be turned on evenly in the end.

[0088] As another exemplary embodiment of the trigger unit 31, see Figure 8 , Figure 8 Another schematic diagram of the electrostatic protection circuit in an embodiment of the present application is shown, wherein the detection unit 11 includes a first resistor R1 and a first capacitor C1; the first end of the first capacitor C1 is connected to the positive input terminal Power of the power supply, the second end of the first capacitor C1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the negative input terminal Gound of the power supply.

[0089] That is to say, the first capacitor C1 and the first resistor R1 can also be connected in series between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply. When an electrostatic pulse is input into the positive input terminal Power of the power supply, the electrostatic pulse charges the first capacitor C1. During the charging process of the first capacitor C1, the first node M1 between the first resistor R1 and the first capacitor C1 gradually decreases. Therefore, the trigger module 30 can output a stable control signal VC according to the voltage signal of the reduced first node M1, thereby controlling the clamping transistor M0 to turn on and discharge the electrostatic pulse current.

[0090] In some embodiments of the present application, for example, the first capacitor C1 and the first resistor R1 can also be connected in series between the positive input terminal Power and the negative input terminal Gound of the power supply, see Fig. 9 , Fig. 9 Another schematic diagram of the electrostatic protection circuit in an embodiment of the present application is shown, wherein the trigger module 30 includes a plurality of trigger units 31 connected in series between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply, and the trigger unit 31 corresponds to the clamping transistor M0 one by one; each trigger unit 31 includes a first NMOS tube MN1 and a second resistor R2, and the first NMOS tube MN1 is connected in series with the second resistor R2; the control end of each first NMOS tube MN1 is connected to the first node M1 between the first resistor R1 and the first capacitor C1, and the control end of each clamping transistor M0 is connected to the second node M2 ​​between the first NMOS tube MN1 and the second resistor R2.

[0091] It should be noted that, when the electrostatic pulse causes the voltage of the first node M1 to gradually decrease, the first NMOS tube MN1 of each trigger unit 31 is turned on, so the second node M2 ​​between the first NMOS tube MN1 and the second resistor R2 in the trigger unit 31 presents a high level. According to the principle of resistance voltage division, it can be known that the voltage of the second node M2 ​​in each trigger unit 31 is not equal. Combined with the different source voltages of each clamping transistor M0, this can make the source and gate voltage difference of each clamping transistor M0 basically equivalent, so that multiple clamping transistors M0 connected in series can be turned on evenly in the end.

[0092] In some embodiments of the present application, for example, for an embodiment in which each clamp transistor M0 is turned on in response to an enable signal EN output by a different detection unit 11, see Fig.10 , Fig.10 Another schematic diagram of the electrostatic protection circuit in the embodiment of the present application is shown, wherein the trigger module 30 includes multiple trigger units 31, the detection module 10 includes multiple detection units 11, and the detection units 11, the trigger units 31 and the clamping transistors M0 correspond to each other one by one; the multiple trigger units 31 are connected in series between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply, and each trigger unit 31 is used to output a control signal VC according to the enable signal EN output by the corresponding detection unit 11 to control the corresponding clamping transistor M0 to be turned on.

[0093] For example, taking the number of the trigger units 31, the detection units 11, and the clamp transistors M0 as two, see Fig.11 , Fig.11 Another schematic diagram of the electrostatic protection circuit in the embodiment of the present application is shown, wherein the plurality of trigger units 31 include a first trigger unit 311 and a second trigger unit 312, the plurality of detection units 11 include a first detection unit 111 and a second detection unit 112, and the plurality of clamp transistors M0 include a first clamp transistor M1 and a second clamp transistor M2; the first detection unit 111 is used to output a first enable signal EN1 when an electrostatic pulse is input to the positive input terminal Power of the power supply, the first trigger unit 311 is used to output a first control signal VC1 according to the first enable signal EN1 output by the first detection unit 111, and the first control signal VC1 is used to control the first clamp transistor M1 to be turned on; the second detection unit 112 is used to output a second enable signal EN2 when an electrostatic pulse is input to the positive input terminal Power of the power supply, the second trigger unit 312 is used to output a second control signal VC2 according to the second enable signal EN2 output by the second detection unit 112, and the second control signal VC2 is used to control the second clamp transistor M2 to be turned on.

[0094] It should be noted that, since multiple trigger units 31 are connected in series between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply, multiple clamping transistors M0 connected in series can be evenly turned on; at the same time, since each trigger unit 31 outputs a control signal VC according to the enable signal EN output by the corresponding detection unit 11, and each detection unit 11 is connected in parallel between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply, each detection unit 11 can ensure that the corresponding trigger unit 31 efficiently outputs the control signal VC, so that each clamping transistor M0 is efficiently and evenly turned on, and finally a better electrostatic pulse current discharge effect is achieved.

[0095] In some embodiments of the present application, for example, the plurality of detection units 11 include a first detection unit 111 and a second detection unit 112. Fig.12 , Fig.12 Another schematic diagram of the electrostatic protection circuit in an embodiment of the present application is shown, wherein the first detection unit 111 includes a first resistor R1 and a first capacitor C1, and the second detection unit 112 includes a second resistor R2 and a second capacitor C2; the first end of the first resistor R1 is connected to the positive input terminal Power of the power supply, the second end of the first resistor R1 is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected to the negative input terminal Gound of the power supply; the first end of the second capacitor C2 is connected to the positive input terminal Power of the power supply, the second end of the second capacitor C2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the negative input terminal Gound of the power supply.

[0096] Specifically, when an electrostatic pulse is input to the positive input terminal Power of the power supply, the electrostatic pulse will charge the first capacitor C1 and the second capacitor C2, the voltage of the first node M1 between the first resistor R1 and the first capacitor C1 increases, and the voltage of the first node M1 between the second resistor R2 and the second capacitor C2 gradually decreases. Therefore, the first trigger unit 311 can output a stable first control signal VC1 according to the increased voltage signal of the first node M1, and the second trigger unit 312 can output a stable second control signal VC2 according to the reduced voltage signal of the second node M2, thereby controlling the first clamp transistor M1 and the second clamp transistor M2 to turn on to discharge the electrostatic pulse current.

[0097] In some embodiments of the present application, for example, for an embodiment in which the plurality of trigger units 31 include a first trigger unit 311 and a second trigger unit 312, see Fig.13 , Fig.13Another schematic diagram of the electrostatic protection circuit in the embodiment of the present application is shown, wherein the first trigger unit 311 includes a first PMOS tube MP1 and a third resistor R3, and the second trigger unit 312 includes a first NMOS tube MN1 and a fourth resistor R4; the first PMOS tube MP1, the third resistor R3, the first NMOS tube MN1 and the fourth resistor R4 are sequentially connected in series between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply; the control end of the first PMOS tube MP1 is connected to the first node M1 between the first resistor R1 and the first capacitor C1, and the control end of the first clamping transistor M1 is connected to the third node M3 between the first PMOS tube MP1 and the third resistor R3; the control end of the first NMOS tube MN1 is connected to the second node M2 ​​between the second resistor R2 and the second capacitor C2, and the control end of the second clamping transistor M2 is connected to the fourth node M4 between the first NMOS tube MN1 and the fourth resistor R4.

[0098] Specifically, when the electrostatic pulse causes the voltage of the first node M1 to increase and the voltage of the second node M2 ​​to decrease, the first PMOS tube MP1 and the first NMOS tube MN1 are turned on, so the third node M3 between the first PMOS tube MP1 and the third resistor R3 presents a high level, and the fourth node M4 between the first NMOS tube MN1 and the fourth resistor R4 presents a high level. According to the resistance voltage division principle, it can be seen that the voltages of the third node M3 and the fourth node M4 are not equal. Combined with the fact that the source voltages of the first clamping transistor M1 and the second clamping transistor M2 are not the same, it can be seen that the source and gate voltage difference of the first clamping transistor M1 and the second clamping transistor M2 is basically the same, so the first clamping transistor M1 and the second clamping transistor M2 can be evenly turned on in the end.

[0099] In some embodiments of the present application, see Fig.14 , Fig.14 Another schematic diagram of the electrostatic protection circuit in an embodiment of the present application is shown, wherein the first end of the first clamping transistor M1 is connected to the positive input terminal Power of the power supply, and the second end of the first clamping transistor M1 is connected to the middle node MO between the third resistor R3 and the first NMOS tube MN1; the first end of the second clamping transistor M2 is connected to the middle node MO between the third resistor R3 and the first NMOS tube MN1, and the second end of the second clamping transistor M2 is connected to the negative input terminal Gound of the power supply.

[0100] It can be seen that the intermediate node MO is a node between the first trigger unit 311 and the second trigger unit 312. Since the first end of the first clamping transistor M1 and the second end of the second clamping transistor M2 are both connected to the intermediate node MO, the intermediate node MO can clamp the source voltage of the first clamping transistor M1, so that the first trigger unit 311 controls the source and gate voltages of the first clamping transistor M1, and the second trigger unit 312 controls the source and gate voltages of the second clamping transistor M2, and finally the first clamping transistor M1 and the second clamping transistor M2 are evenly turned on.

[0101] In some embodiments of the present application, see Fig.15 , Fig.15 Another schematic diagram of the electrostatic protection circuit in an embodiment of the present application is shown, wherein the electrostatic protection circuit also includes a first bias resistor R01 and a second bias resistor R02; the first end of the first bias resistor R01 is connected to the positive input terminal Power of the power supply, and the second end of the first bias resistor R01 is connected to the middle node MO between the third resistor R3 and the first NMOS tube MN1; the first end of the second bias resistor R02 is connected to the middle node MO between the third resistor R3 and the first NMOS tube MN1, and the second end of the second bias resistor R02 is connected to the negative input terminal Gound of the power supply.

[0102] That is to say, the first bias resistor R01 and the second bias resistor R02 are connected in series between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply, and the first bias resistor R01 and the second bias resistor R02 can bias the voltage of the intermediate node MO through voltage division. For the first clamping transistor M1 and the second clamping transistor M2, the source voltage and the drain voltage of the first clamping transistor M1 are equal to the voltage across the first bias resistor R01, and the source voltage and the drain voltage of the second clamping transistor M2 are equal to the voltage across the second bias resistor R02. The voltage between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply is divided by the first bias resistor R01 and the second bias resistor R02. Therefore, even if the first clamping transistor M1 and the second clamping transistor M2 are low-voltage MOS tubes, they will not be damaged due to the excessively high voltage between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply.

[0103] It can be understood that, for the embodiment in which multiple clamping transistors M0 are turned on in response to the enable signal EN output by the same trigger unit 31, a bias voltage can also be set to bias the source voltage and drain voltage of each clamping transistor M0. Fig.16 as well as Fig.17 , Fig.16 Another schematic diagram of an electrostatic protection circuit in an embodiment of the present application is shown. Fig.17Another schematic diagram of the electrostatic protection circuit in an embodiment of the present application is shown, in which a first bias resistor R01 and a second bias resistor R02 can be connected in series between the positive input terminal Power of the power supply and the negative input terminal Gound of the power supply, and the voltage of the intermediate node MO is biased by the first bias resistor R01 and the second bias resistor R02.

[0104] Furthermore, in order to better implement the electrostatic protection circuit in the embodiment of the present application, on the basis of the electrostatic protection circuit, the present application also provides an electronic device, the electronic device including the electrostatic protection circuit as in any of the above embodiments. Since the electronic device in the embodiment of the present application is provided with the electrostatic protection circuit of the above embodiment, it has all the beneficial effects of the above electrostatic protection circuit, which will not be described in detail here.

[0105] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above, and will not be repeated here.

[0106] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0107] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more embodiments of the invention, in the above description of the embodiments of this application, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0108] The above is a detailed introduction to an electrostatic protection circuit and an electronic device provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. An electrostatic protection circuit, characterized in that: include: A detection module, the detection module is used to output an enable signal when an electrostatic pulse is input to the positive input terminal of the power supply; A clamping module, the clamping module is used to discharge the electrostatic pulse at the positive input terminal of the power supply to the negative input terminal of the power supply in response to the enable signal; Wherein, the clamping module comprises a plurality of clamping transistors connected in series between the positive input terminal of the power supply and the negative input terminal of the power supply, and the maximum source-drain voltage of the clamping transistor is less than or equal to a preset value; The detection module includes at least one detection unit, each of the detection units is connected in parallel between the positive power input terminal and the negative power input terminal, and each of the clamp transistors is turned on in response to an enable signal output by the same or different detection units.

2. The electrostatic protection circuit according to claim 1, characterized in that: The electrostatic protection circuit also includes a trigger module; The trigger module is used to output a control signal according to the enable signal output by the detection unit, and the control signal is used to control the clamp transistors to be turned on, so that each of the clamp transistors is turned on in response to the enable signal output by the detection unit.

3. The electrostatic protection circuit according to claim 2, characterized in that: The detection unit includes a first resistor and a first capacitor; The first end of the first resistor is connected to the positive input terminal of the power supply, the second end of the first resistor is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the negative input terminal of the power supply.

4. The electrostatic protection circuit according to claim 3, characterized in that: The trigger module includes a first PMOS tube and a first NMOS tube; The first end of the first PMOS tube is connected to the positive input end of the power supply, the second end of the first PMOS tube is connected to the second end of the first NMOS tube, and the first end of the first NMOS tube is connected to the negative input end of the power supply; The control ends of the first PMOS tube and the first NMOS tube are connected to a first node between the first resistor and the first capacitor, and the control end of each clamping transistor is connected to a second node between the first PMOS tube and the first NMOS tube.

5. The electrostatic protection circuit according to claim 3, characterized in that: The trigger module comprises a plurality of trigger units connected in series between the positive input terminal of the power supply and the negative input terminal of the power supply, and the trigger units correspond to the clamp transistors one by one; The trigger unit is used for outputting a control signal to the corresponding clamp transistor according to the enable signal output by the detection unit.

6. The electrostatic protection circuit according to claim 5, characterized in that: Each of the trigger units includes a first PMOS tube and a second resistor, wherein the first PMOS tube is connected in series with the second resistor; The control end of each of the first PMOS transistors is connected to a first node between the first resistor and the first capacitor, and the control end of each of the clamping transistors is connected to a second node between the first PMOS transistor and the second resistor.

7. The electrostatic protection circuit according to claim 2, characterized in that: The detection unit includes a first resistor and a first capacitor; The first end of the first capacitor is connected to the positive input end of the power supply, the second end of the first capacitor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the negative input end of the power supply.

8. The electrostatic protection circuit according to claim 7, characterized in that: The trigger module comprises a plurality of trigger units connected in series between the positive input terminal of the power supply and the negative input terminal of the power supply, and the trigger units correspond to the clamp transistors one by one; Each of the trigger units includes a first NMOS tube and a second resistor, and the first NMOS tube is connected in series with the second resistor; The control end of each of the first NMOS transistors is connected to a first node between the first resistor and the first capacitor, and the control end of each of the clamping transistors is connected to a second node between the first NMOS transistor and the second resistor.

9. The electrostatic protection circuit according to claim 2, characterized in that: The trigger module includes a plurality of trigger units, the detection module includes a plurality of detection units, and the detection units, the trigger units and the clamp transistors correspond to each other one by one; A plurality of the trigger units are connected in series between the positive power input terminal and the negative power input terminal, and each of the trigger units is used to output a control signal according to an enable signal output by the corresponding detection unit to control the corresponding clamp transistor to be turned on.

10. The electrostatic protection circuit according to claim 9, characterized in that: The plurality of trigger units include a first trigger unit and a second trigger unit, the plurality of detection units include a first detection unit and a second detection unit, and the plurality of clamp transistors include a first clamp transistor and a second clamp transistor; The first detection unit is used to output a first enable signal when an electrostatic pulse is input to the positive input terminal of the power supply, and the first trigger unit is used to output a first control signal according to the first enable signal output by the first detection unit, and the first control signal is used to control the first clamp transistor to be turned on; The second detection unit is used to output a second enable signal when an electrostatic pulse is input to the positive input terminal of the power supply, and the second trigger unit is used to output a second control signal according to the second enable signal output by the second detection unit, and the second control signal is used to control the conduction of the second clamping transistor.

11. The electrostatic protection circuit according to claim 10, characterized in that: The first detection unit includes a first resistor and a first capacitor, and the second detection unit includes a second resistor and a second capacitor; The first end of the first resistor is connected to the positive input terminal of the power supply, the second end of the first resistor is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the negative input terminal of the power supply; The first end of the second capacitor is connected to the positive input end of the power supply, the second end of the second capacitor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the negative input end of the power supply.

12. The electrostatic protection circuit according to claim 11, characterized in that: The first trigger unit includes a first PMOS tube and a third resistor, and the second trigger unit includes a first NMOS tube and a fourth resistor; The first PMOS transistor, the third resistor, the first NMOS transistor and the fourth resistor are sequentially connected in series between the positive input terminal of the power supply and the negative input terminal of the power supply; The control end of the first PMOS transistor is connected to a first node between the first resistor and the first capacitor, and the control end of the first clamp transistor is connected to a third node between the first PMOS transistor and the third resistor; The control end of the first NMOS transistor is connected to a second node between the second resistor and the second capacitor, and the control end of the second clamp transistor is connected to a fourth node between the first NMOS transistor and the fourth resistor.

13. The electrostatic protection circuit according to claim 12, characterized in that: The first end of the first clamp transistor is connected to the positive input end of the power supply, and the second end of the first clamp transistor is connected to the middle node between the third resistor and the first NMOS transistor; The first end of the second clamp transistor is connected to the middle node between the third resistor and the first NMOS transistor, and the second end of the second clamp transistor is connected to the negative input end of the power supply.

14. The electrostatic protection circuit according to claim 12, characterized in that: The electrostatic protection circuit also includes a first bias resistor and a second bias resistor; The first end of the first bias resistor is connected to the positive input end of the power supply, and the second end of the first bias resistor is connected to the middle node between the third resistor and the first NMOS transistor; The first end of the second bias resistor is connected to the middle node between the third resistor and the first NMOS transistor, and the second end of the second bias resistor is connected to the negative input terminal of the power supply.

15. An electronic device, characterized in that: The invention comprises the electrostatic protection circuit as claimed in any one of claims 1 to 14.

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