A low electromagnetic interference isolated power supply system

Abstract

The invention discloses an isolated power supply system with low electromagnetic interference, including: an inverter circuit, a transformer, a rectifier circuit, a feedback control circuit, a spread spectrum clock generating circuit and a control driving circuit; the inverter circuit is connected to the transformer, the inverter circuit converts the input direct current into a differential high-frequency oscillation power signal and outputs it to the transformer; the transformer is connected to the rectifier circuit; the rectifier circuit is connected to the feedback control circuit, the rectifier circuit rectifies the output of the transformer; the feedback control circuit is connected to the spread spectrum clock generating circuit, the feedback control circuit feeds back the output voltage of the rectifier circuit to the spread spectrum clock generating circuit; the spread spectrum clock generating circuit is connected to the control driving circuit, the spread spectrum clock generating circuit generates a spread spectrum clock signal; the control driving circuit is connected to the inverter circuit, the control driving circuit outputs a switch control signal for controlling the inverter circuit according to the spread spectrum clock signal. The technical scheme of the invention reduces the electromagnetic interference and optimization cost of the isolated power supply system.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to an isolated power supply system with low electromagnetic interference. Background Art

[0002] Isolated power supplies are currently widely used in the fields of industry, automotive electronics, biomedicine, etc. Among them, the current isolation method can effectively eliminate pulses, glitches and potential ground loops between different voltage domains, which plays a vital role in ensuring the safe and reliable operation of the system in harsh industrial environments. Compared with the use of optical couplers or discrete transformers as isolation barriers to transmit power, the use of micro transformers in isolated power supplies can effectively reduce the size and cost, but it also requires the isolated power supply to operate at a frequency of tens or even hundreds of MHz, becoming a strong radiation source that interferes with the normal operation of other electronic equipment, that is, it brings the problem of electromagnetic interference (EMI).

[0003] The main mechanism of electromagnetic interference in traditional isolated power supply systems is dipole radiation. Common-mode displacement current is generated between the transmitter and the receiver, and circulates on the isolation barrier through the parasitic capacitance of the transformer. In order to meet the requirements of low EMI, traditional isolated power supplies reduce the length of the dipole antenna through the design of the PCB board and optimize EMI at the application level. This method greatly increases the system cost and cannot fundamentally solve the problem. Increasing the symmetry of the circuit topology at the chip level and reducing the amplitude of the common-mode current can also optimize the EMI problem, but it will greatly increase the difficulty of circuit design. Summary of the invention

[0004] The present invention provides an isolated power supply system with low electromagnetic interference to solve the problem of electromagnetic interference of the isolated power supply system.

[0005] According to one aspect of the present invention, there is provided an isolated power supply system with low electromagnetic interference, comprising: an inverter circuit, a transformer, a rectifier circuit, a feedback control circuit, a spread spectrum clock generation circuit and a control drive circuit;

[0006] The inverter circuit is connected to the transformer, and the inverter circuit is used to convert the input direct current into a differential high-frequency oscillation power signal and output it to the transformer;

[0007] The transformer is connected to the rectifier circuit;

[0008] The rectifier circuit is connected to the feedback control circuit, and the rectifier circuit is used to rectify the output of the transformer;

[0009] The feedback control circuit is connected to the spread spectrum clock generating circuit, and the feedback control circuit is used to feed back the output voltage of the rectifier circuit to the spread spectrum clock generating circuit;

[0010] The spread spectrum clock generating circuit is connected to the control driving circuit, and the spread spectrum clock generating circuit is used to generate a spread spectrum clock signal;

[0011] The control driving circuit is connected to the inverter circuit, and the control driving circuit is used to output a switch control signal for controlling the inverter circuit according to the spread spectrum clock signal.

[0012] Optionally, the spread spectrum clock generation circuit includes a random code generation module, a random voltage generation module, an oscillator module and a frequency division module;

[0013] The random code generation module is connected to the random voltage generation module, and the random code generation module is used to generate a pseudo-random code with a repetitive period;

[0014] The random voltage generating module is connected to the oscillator module, and the random voltage generating module is used to generate a continuously randomly fluctuating output voltage;

[0015] The oscillator module is connected to the frequency division module;

[0016] The frequency division module is connected to the oscillator module and the random code generation module, and is used to generate a frequency division signal as a clock signal of the random code generation module to drive it to generate a random code.

[0017] Optionally, the random voltage generating module includes a plurality of switches, a binary resistor array, a sixth resistor, a first current source and a first capacitor;

[0018] The plurality of switches are connected in parallel with the plurality of resistors in the binary resistor array in a one-to-one correspondence; the sixth resistor is connected between the first current source and the binary resistor array;

[0019] A first end of the first capacitor is connected to a first end of the sixth resistor, and a second end of the first capacitor is grounded.

[0020] Optionally, the binary resistor array includes a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor;

[0021] The multiple switches include a first switch, a second switch, a third switch, a fourth switch and a fifth switch, which are connected in series in sequence, the first switch is connected in parallel with the fifth resistor, the second switch is connected in parallel with the fourth resistor, the third switch is connected in parallel with the third resistor, the fourth switch is connected in parallel with the second resistor, the fifth switch is connected in parallel with the first resistor, a first end of the sixth resistor is connected to the first current source, and a second end of the sixth resistor is connected to a first end of the fifth resistor and a first end of the first switch.

[0022] Optionally, the oscillator module includes a second current source, a comparator, a second capacitor, a MOS tube and a first D trigger, the first end of the second current source is connected to a power supply signal, the second end of the second current source is connected to the first end of the second capacitor, the second end of the second capacitor is grounded, the first input end of the comparator is connected to the output end of the random voltage generation module, the second input end of the comparator is connected to the first end of the second capacitor and the first electrode of the MOS tube, the gate of the MOS tube is connected to the second electrode of the second capacitor and grounded, the second electrode of the MOS tube is connected to the output end of the comparator and connected to the second input end of the first D trigger, and the output end of the first D trigger is connected to the first input end of the first D trigger.

[0023] Optionally, the random code generation module includes a linear feedback shift register, a first NOR gate, a second NOR gate, a third NOR gate, a fourth NOR gate, a first OR gate and a first XOR gate;

[0024] The linear feedback shift register includes a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop and a sixth D flip-flop;

[0025] The first input end of the first NOR gate inputs the output signal of the second D flip-flop, the second input end of the first NOR gate inputs the output signal of the third D flip-flop, the first input end of the second NOR gate inputs the output signal of the fourth D flip-flop, the second input end of the second NOR gate inputs the output signal of the fifth D flip-flop, the first input end of the third NOR gate inputs the output signal of the first NOR gate, the second input end of the third NOR gate inputs the output signal of the second NOR gate, the first input end of the fourth NOR gate inputs the output signal of the sixth D flip-flop, the second input end of the fourth NOR gate inputs the output signal of the third NOR gate, the first input end of the first OR gate inputs the output signal of the fourth NOR gate, the second input end of the first OR gate inputs the output signal of the sixth D flip-flop, the first input end of the first XOR gate inputs the output signal of the first OR gate, and the second input end of the first XOR gate inputs the output signal of the fourth D flip-flop.

[0026] Optionally, the random code generation module generates a pseudo-random code sequence with a repetition period according to a characteristic polynomial of the linear feedback shift register.

[0027] Optionally, the output voltage of the random voltage generating module is generated according to the first current source flowing through the binary resistor array.

[0028] Optionally, the capacitance value of the first capacitor is adjustable.

[0029] Optionally, the oscillation frequency of the oscillator module fluctuates continuously and randomly according to the voltage of the random voltage generating module, and the generated clock signal serves as a switch control signal of the inverter circuit.

[0030] According to the technical solution of the embodiment of the present invention, the inverter circuit converts the input direct current into a differential high-frequency oscillation power signal and outputs it to the transformer. The transformer performs step-up or step-down according to different requirements and then outputs it to the rectifier circuit. The rectifier circuit rectifies the high-frequency oscillation AC voltage output by the transformer into a direct current voltage and outputs it to the feedback control circuit. The feedback control circuit processes the output voltage of the rectifier circuit and modulates the stable output voltage to feedback to the spread spectrum clock generation circuit. The spread spectrum clock generation circuit generates a spread spectrum clock signal and outputs it to the control drive circuit. The control drive circuit outputs a switch control signal for controlling the inverter circuit according to the spread spectrum clock signal. According to the technical solution of the present invention, the spread spectrum clock generation circuit can provide the inverter circuit with a clock signal whose frequency changes continuously and randomly over time. The switching frequency of the inverter circuit, the transformer and the rectifier circuit will no longer be a fixed frequency. The frequency of the dipole radiation will also change continuously and randomly over time, reducing the electromagnetic interference of the isolated power supply system. In addition, the spread spectrum clock generation circuit has a small scale and low power consumption, which reduces the optimization cost of the isolated power supply system.

[0031] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 It is a structural schematic diagram of an isolated power supply system provided according to relevant technologies;

[0034] Figure 2is a schematic diagram of a dipole radiation mechanism of an isolated power system adopted according to the related art;

[0035] Figure 3 is a structural schematic diagram of an isolated power supply system provided according to an embodiment of the present invention;

[0036] Figure 4 is a structural schematic diagram of another isolated power supply system provided according to an embodiment of the present invention;

[0037] Figure 5 is a schematic diagram of waveforms generated by a spread spectrum clock generating circuit provided in an embodiment of the present invention;

[0038] Figure 6 A circuit schematic diagram of a spread spectrum clock generating circuit is provided according to an embodiment of the present invention;

[0039] Figure 7 is a waveform in the time domain of the continuous random spread spectrum scheme and other spread spectrum schemes proposed according to an embodiment of the present invention;

[0040] Figure 8 This is the spreading effect of the continuous random spreading scheme proposed according to the embodiment of the present invention and other spreading schemes on the electromagnetic interference energy in the frequency domain. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] Figure 1 It is a structural schematic diagram of an isolated power supply system provided according to relevant technologies. Figure 2Schematic diagram of the dipole radiation mechanism of the isolated power system according to the related art. Figure 1 As shown, the system includes: an inverter circuit 101, a transformer 102, a rectifier circuit 103, a feedback control circuit, an oscillator 105 and a control drive circuit 106. Among them, Lp and Ls are the primary coil and the secondary coil of the transformer, the first input terminal of the inverter circuit 101 is connected to the power signal VIN, and the second input terminal is grounded GND1, the first input terminal of the rectifier circuit 103 is connected to the output voltage VISO, and the second input terminal of the rectifier circuit 103 is grounded GND2. The main mechanism of electromagnetic interference is dipole radiation, such as Figure 2 As shown. A common-mode displacement current is generated between the transmitter and the receiver, circulating on the isolation barrier through the parasitic capacitance of the transformer. Radiated energy P rad for:

[0044]

[0045] Among them, I CM , f CM is the amplitude and frequency of the common-mode current flowing through the dipole antenna, L ant is the length of the dipole antenna.

[0046] Figure 1 In order to meet the requirement of low EMI, the power system shown in the figure reduces the length of the dipole antenna through the design of the PCB board and optimizes EMI from the application level. This method greatly increases the system cost and cannot fundamentally solve the problem. Increasing the symmetry of the circuit topology and reducing the amplitude of the common-mode current at the chip level can also optimize the EMI problem, but it will greatly increase the difficulty of circuit design.

[0047] Figure 3 The present invention provides a schematic diagram of the structure of an isolated power supply system. This embodiment can be applied to reduce the electromagnetic interference of the isolated power supply system. The isolated power supply system can be implemented in the form of hardware and / or software. The system can be configured in the fields of industry, automotive electronics, biomedicine, etc. Figure 3 As shown, the system includes: an inverter circuit 201, a transformer 202, a rectifier circuit 203, a feedback control circuit 204, a spread spectrum clock generation circuit 205 and a control drive circuit 206;

[0048] The inverter circuit 201 is connected to the transformer 202, and the inverter circuit 201 is used to convert the input direct current into a differential high-frequency oscillation power signal and output it to the transformer 202; the transformer 202 is connected to the rectifier circuit 203; the rectifier circuit 203 is connected to the feedback control circuit 204, and the rectifier circuit 203 is used to rectify the output of the transformer 202; the feedback control circuit 204 is connected to the spread spectrum control clock generating circuit 205, and the feedback control circuit 204 is used to feed back the output voltage of the rectifier circuit 203 to the spread spectrum clock generating circuit 205; the spread spectrum clock generating circuit 205 is connected to the control drive circuit 206, and the spread spectrum clock generating circuit 205 is used to generate a spread spectrum clock signal; the control drive circuit 206 is connected to the inverter circuit 201, and the control drive circuit 206 is used to output a switch control signal for controlling the inverter circuit 201 according to the spread spectrum clock signal.

[0049] Among them, the inverter circuit 201 converts the input direct current into a differential high-frequency oscillation power signal. The inverter circuit 201 can be a full-bridge inverter circuit, a half-bridge inverter circuit, etc. The full-bridge inverter circuit is composed of four switching devices (usually MOSFET or IGBT) through the full-bridge inverter circuit to form a full-bridge structure. By controlling the on and off of the four switching devices, the conversion of direct current to alternating current can be achieved. The half-bridge inverter circuit consists of two power switches connected in series and two capacitors connected in series. When one switch tube is turned on, the energy on the capacitor is released to the load, and the output voltage is positive; when the other switch tube is turned on, the energy on the other capacitor is released to the load, and the output voltage is negative. By alternating the conduction of the two switch tubes, the load obtains AC power. The inverter circuit 201 is connected to the transformer 202, and the AC output of the inverter circuit 201 is stepped up or stepped down through the transformer 202 to adapt to different load requirements. The transformer 202 is connected to the rectifier circuit 203, and the AC power output by the secondary winding of the transformer 202 is directly connected to the input end of the rectifier circuit 203. The rectifier circuit 203 is connected to the feedback control circuit 204, and the rectifier circuit 203 can rectify the high-frequency oscillating AC voltage output by the secondary coil of the transformer into a DC voltage and provide it to the feedback control circuit 204. The feedback control circuit 204 is connected to the spread spectrum control clock generation circuit 205, and the feedback control circuit 204 can adjust and control the output of the rectifier circuit 203 to ensure the stability of the output voltage, and feed back the stable output voltage to the spread spectrum clock generation circuit. The spread spectrum clock generation circuit 205 is connected to the control drive circuit 206, and the spread spectrum clock generation circuit 205 generates a spread spectrum clock signal, which can be a clock signal whose frequency changes continuously and randomly over time. The spread spectrum clock generation circuit 205 disperses the energy of the clock signal into a certain spectrum range, thereby effectively reducing the EMI generated by the signal. The control driving circuit 206 is connected to the inverter circuit 201. The control driving circuit 206 can generate a switch control signal for controlling the power tube in the inverter circuit 201 according to the spread spectrum clock signal. At the same time, the spread spectrum clock signal generates a switch control signal with driving capability after passing through the control driving circuit 206. At this time, the switching frequency of the inverter circuit, transformer and rectifier circuit will no longer be a fixed frequency, and the frequency of the dipole radiation will also change continuously and randomly over time. Compared with traditional isolated power supplies, such as Figure 2 As described above, the peak energy of the electromagnetic interference of a single frequency will be dispersed, thereby reducing the electromagnetic interference.

[0050] The technical solution of the embodiment of the present invention is through an inverter circuit, a transformer, a rectifier circuit, a feedback control circuit, a spread spectrum clock generation circuit and a control drive circuit. The inverter circuit converts the input direct current into a differential high-frequency oscillation power signal and outputs it to the transformer. The transformer performs step-up or step-down according to different requirements and then outputs it to the rectifier circuit. The rectifier circuit rectifies the high-frequency oscillation AC voltage output by the transformer into a direct current voltage and outputs it to the feedback control circuit. The feedback control circuit processes the output voltage of the rectifier circuit and modulates the stable output voltage to feed back to the spread spectrum clock generation circuit. The spread spectrum clock generation circuit generates a spread spectrum clock signal and outputs it to the control drive circuit. The control drive circuit outputs a switch control signal for controlling the inverter circuit according to the spread spectrum clock signal. The technical solution of the present invention provides a clock signal whose frequency changes continuously and randomly over time for the inverter circuit through the spread spectrum clock generation circuit. The switching frequency of the power stage will no longer be a fixed frequency, and the frequency of the dipole radiation will also change continuously and randomly over time, thereby reducing the electromagnetic interference of the isolated power supply system. The spread spectrum clock generation circuit is small in scale and low in power consumption, thereby reducing the optimization cost of the isolated power supply system.

[0051] Figure 4 A structural schematic diagram of another isolated power supply system is provided for an embodiment of the present invention. Figure 5 is a schematic diagram of waveforms generated by a spread spectrum clock generating circuit according to an embodiment of the present invention. In some optional embodiments of the present invention, such as Figure 4 As shown, the spread spectrum clock generating circuit 205 includes a random code generating module 2051, a random voltage generating module 2052, an oscillator module 2053 and a frequency dividing module 2054;

[0052] The random code generation module 2051 is connected to the random voltage generation module 2052, and the random code generation module 2051 is used to generate a pseudo-random code Code with a repetitive period;

[0053] The random voltage generating module 2052 is connected to the oscillator module 2053, and the random voltage generating module 2052 is used to generate a continuously randomly fluctuating output voltage Vssm;

[0054] The oscillator module 2053 is connected to the frequency division module 2054; the frequency division module 2054 is connected to the oscillator module 2053 and the random code generation module 2051, and is used to generate a frequency division signal and serve as a clock signal of the random code generation module 2051 to drive it to generate a random code.

[0055] Among them, the random code generation module 2051 can generate a pseudo-random code Code with a repetitive period through the shift register in the linear feedback shift register (LFSR) and a specific feedback function (usually an XOR operation), and the pseudo-random code Code has a periodic binary sequence. The random voltage generation module 2052 can generate a continuously randomly fluctuating output voltage Vssm through a binary resistor array according to the pseudo-random code Code of the random code generation module 2051. The oscillation frequency of the oscillator module 2053 generates corresponding continuous random fluctuations according to the output voltage Vssm of the random voltage generation module 2052, thereby realizing continuous random spread spectrum. The first clock signal CLK generated by the oscillator module 2053 generates a switch control signal for controlling the power tube in the inverter circuit 201 after passing through the control drive circuit 205, and expands the originally fixed switching frequency into a switching frequency that fluctuates within a set range. The energy of electromagnetic interference will be dispersed, thereby reducing electromagnetic interference. The frequency division module 2054 can generate a frequency division signal and use it as the second clock signal CLK' of the random code generation module 1051 to drive it to generate a pseudo-random code Code. The specific waveform diagram is as follows: Figure 5 shown. Figure 5 f shown in CLK is the frequency waveform of the first clock signal CLK generated by the oscillator module 2053. Figure 4 , the first input terminal of the inverter circuit 201 is connected to the power signal VIN, and the second input terminal is grounded GND1, the first input terminal of the rectifier circuit 203 is connected to the output voltage VISO, and the second input terminal of the rectifier circuit 103 is grounded GND2. Where Lp and Ls are the primary coil and secondary coil of the transformer 202. The voltage node V PP Connect the TX of transformer 202 P port, voltage node V PN Connect the TX of transformer 202 N port, while also allowing V PP (V PN ) and TX P (TX N ) uses an indirect connection method, such as connecting a capacitor between the two.

[0056] The existing spread spectrum clock generation circuit is based on the principle of spread spectrum. It achieves energy dispersion by fine-tuning the clock cycle, keeping the total number of cycles unchanged while changing the local cycle. The modulation speed determines the frequency of the cycle. The phase-locked loop structure and voltage-controlled oscillator are used to realize the spread spectrum clock. By reasonably designing the phase-locked loop, an external filter is used to perform triangular wave modulation on the control voltage of the voltage-controlled oscillator to obtain the required spread spectrum clock. In order to obtain the spread spectrum clock, the ΔΣ modulator (DSM) is used to randomize the frequency division ratio, shape the quantization noise, push the noise to the high frequency, eliminate the spurious caused by the fractional frequency division, and improve the in-band signal-to-noise ratio. When designing, it is necessary to comprehensively consider reducing EMI and maintaining circuit stability, and realize the spread spectrum of the clock signal by optimizing the circuit module and providing a stable power supply. Finally, the designed spread spectrum clock generation circuit is verified by circuit-level simulation to ensure that it meets the performance requirements while reducing the fundamental frequency and harmonic energy, effectively reducing electromagnetic interference, and maintaining circuit performance and stability. The spread spectrum clock generation circuit of the embodiment of the present invention utilizes the coordinated work of a random code generation module, a random voltage generation module, an oscillator module and a frequency division module to achieve the dispersion of clock signal energy within a wide spectrum range, thereby reducing electromagnetic interference while ensuring the stability and accuracy of the clock signal.

[0057] Figure 6 A circuit schematic diagram of a spread spectrum clock generating circuit is provided for an embodiment of the present invention. In some optional embodiments of the present invention, for example, Figure 6 As shown, the random voltage generating module 2052 includes a plurality of switches, a binary resistor array, a sixth resistor R5, a first current source I1 and a first capacitor Cssm;

[0058] The plurality of switches are connected in parallel with the plurality of resistors in the binary resistor array in a one-to-one correspondence; the sixth resistor R5 is connected between the first current source I1 and the binary resistor array;

[0059] A first end of the first capacitor Cssm is connected to a first end of the sixth resistor R5 , and a second end of the first capacitor Cssm is grounded.

[0060] The binary resistor array includes a series of resistors arranged according to binary weights, and the resistor array is composed of a base resistor R and a double value resistor 2R, and each digital bit corresponds to a combination of R and 2R. Multiple switches are connected in parallel with multiple resistors in the binary resistor array in a one-to-one correspondence, and the first capacitor Cssm can adjust its capacitance within a certain range, and the capacitance value of the capacitor can be changed by changing the interval, area or dielectric material between the two electrodes.

[0061] Continue to refer Figure 6 In some optional embodiments of the present invention, the binary resistor array includes a first resistor R0, a second resistor R1, a third resistor R2, a fourth resistor R3 and a fifth resistor R4;

[0062] The multiple switches include a first switch S0, a second switch S1, a third switch S2, a fourth switch S3 and a fifth switch S4. The first switch S0, the second switch S1, the third switch S2, the fourth switch S3 and the fifth switch S4 are connected in series in sequence. The first switch S0 is connected in parallel with the fifth resistor S4, the second switch S1 is connected in parallel with the fourth resistor R3, the third switch S2 is connected in parallel with the third resistor R2, the fourth switch S3 is connected in parallel with the second resistor R1, the fifth switch S4 is connected in parallel with the first resistor R0, a first end of the sixth resistor R5 is connected to the first current source I1, and a second end of the sixth resistor R5 is connected to a first end of the fifth resistor R4 and a first end of the first switch S0.

[0063] Exemplarily, the resistance of the first resistor R0 is R, the resistance of the second resistor R1 is 2R, the resistance of the third resistor R2 is 4R, the resistance of the fourth resistor R3 is 8R, and the resistance of the fifth resistor R4 is 16R. The sixth resistor R5 is connected between the first current source I1 and the binary resistor array, and the output voltage Vssm of the random voltage generating module 2052 can be generated according to the first current source I1 flowing through the binary resistor array.

[0064] Continue to refer Figure 6 In some optional embodiments of the present invention, the oscillator module 2053 includes a second current source I2, a comparator P1, a second capacitor C1, a MOS tube M1 and a first D trigger D5, a first end of the second current source I2 is connected to a power signal, a second end of the second current source I2 is connected to a first end of the second capacitor C1, a second end of the second capacitor C2 is grounded, a first input end of the comparator P1 is connected to an output end of the random voltage generating module 2052, a second input end of the comparator P1 is connected to a first end of the second capacitor C1 and a first electrode of the MOS tube M1, a gate of the MOS tube M1 is connected to a second electrode of the second capacitor C1 and is grounded, a second electrode of the MOS tube M1 is connected to an output end of the comparator P1 and is connected to a second input end of the first D trigger D5, and an output end of the first D trigger D5 is connected to a first input end of the first D trigger D5.

[0065] Among them, the MOS tube M1 can be an NMOS tube, the source of the MOS tube M1 is connected to the output end of the comparator P1 and connected to the second input end of the first D trigger D5, the gate of the MOS tube M1 is connected to the second electrode of the second capacitor C1 and grounded, the drain of the MOS tube M1 is connected to the second input end of the comparator P1 and the first end of the second capacitor C1, and the MOS tube M1 can be used for discharging the second capacitor C1. The second capacitor C1 can be charged by the second current source I2, and the charging voltage is compared with the output voltage Vssm of the random voltage generating module 2052 input to the comparator P1. When the charging voltage of the second capacitor C1 is greater than the output voltage Vssm of the random voltage generating module 2052, the charging voltage of the second capacitor C1 is discharged through the MOS tube M1, and this process is repeated to achieve oscillation. The oscillator module 2053 adopts an RC oscillator, and its frequency is negatively correlated with the value of the output voltage Vssm of the random voltage generating module 2052. The oscillation frequency fluctuates continuously and randomly according to the output voltage Vssm of the random voltage generating module 2052, and this fluctuation is continuously and randomly changed.

[0066] Continue to refer Figure 6 In some optional embodiments of the present invention, the random code generation module 2051 includes a linear feedback shift register, a first NOR gate NOR0, a second NOR gate NOR1, a third NOR gate NOR2, a fourth NOR gate NOR3, a first OR gate OR0 and a first XOR gate XOR0;

[0067] The linear feedback shift register includes a second D flip-flop D0, a third D flip-flop D1, a fourth D flip-flop D2, a fifth D flip-flop D3 and a sixth D flip-flop D4;

[0068] The first input terminal of the first NOR gate NOR0 inputs the output signal B0 of the second D flip-flop D0, the second input terminal of the first NOR gate NOR0 inputs the output signal B1 of the third D flip-flop D1, the first input terminal of the second NOR gate NOR1 inputs the output signal B2 of the fourth D flip-flop D2, the second input terminal of the second NOR gate NOR1 inputs the output signal B3 of the fifth D flip-flop D3, the first input terminal of the third NOR gate NOR2 inputs the output signal of the first NOR gate NOR0, and the second input terminal of the third NOR gate NOR2 inputs the output signal B1 of the second D flip-flop D1. The first input end of the fourth NOR gate NOR3 inputs the output signal B4 of the sixth D flip-flop D4, the second input end of the fourth NOR gate NOR3 inputs the output signal of the third NOR gate NOR2, the first input end of the first OR gate OR0 inputs the output signal of the fourth NOR gate NOR3, the second input end of the first OR gate OR0 inputs the output signal B4 of the sixth D flip-flop D4, the first input end of the first XOR gate XOR0 inputs the output signal of the first OR gate OR0, and the second input end of the first XOR gate XOR0 inputs the output signal B2 of the fourth D flip-flop D2.

[0069] In each clock cycle, the output bit of the linear feedback shift register is shifted and a new output bit is generated according to a specific feedback logic. The feedback logic is determined by a polynomial, called the feedback polynomial, such as Figure 6 As shown, the random code generation module 2051 includes 5-stage D flip-flops forming a 5-bit linear feedback shift register, whose polynomial satisfies P(x)=x 5 +x 3 +1, that is, the feedback signal is the XOR of the outputs of the 5th flip-flop and the 3rd flip-flop. The sequence length of the LFSR is 31, which can generate a repetition period of 2 5 The present invention takes level 5 as an example and can also be applied to linear feedback shift registers of other levels. The frequency division module 2054 generates a frequency division signal as the second clock signal CLK' of the random code generation module 2051 and inputs it to the second D flip-flop D0, the third D flip-flop D1, the fourth D flip-flop D2, the fifth D flip-flop D3 and the sixth D flip-flop D4.

[0070] Continue to refer Figure 6 Optionally, the random code generation module generates a pseudo-random code sequence with a repetition period according to the characteristic polynomial of the linear feedback shift register.

[0071] The linear feedback shift register in the random code generation module 2051 has a characteristic polynomial satisfying P(x)=x 5 +x 3 +1, can produce a repetition period of 2 5 -1 pseudo-random code sequence.

[0072] Continue to refer Figure 6 Optionally, the output voltage Vssm of the random voltage generating module 2052 is generated according to the first current source I1 flowing through the binary resistor array.

[0073] The first current source I1 provides a constant current, which is distributed to different paths according to different switches. When the current source I1 flows through the resistor array, different resistor combinations will produce different voltage drops. The voltage contribution of each resistor depends on whether it is connected in series to the output node and its resistance value.

[0074] Continue to refer Figure 6 , Optionally, the capacitance value of the first capacitor Cssm is adjustable.

[0075] The capacitance of the first capacitor Cssm can be adjusted within a certain range, and the capacitance of the capacitor can be changed by changing the interval, area or dielectric material between the two electrodes. The first capacitor Cssm is controlled by a pseudo-random code and has a variable resistance value between 0 and (2 5 -1)*R, by selecting a suitable R value, a specific voltage variable range can be set, which is set to ±7% here. The change speed of the output voltage Vssm of the random voltage generation module 2052 is determined by the time constant of the node, and the time constant of the node can be further controlled by adjusting the size of Cssm.

[0076] Continue to refer Figure 6 Optionally, the oscillation frequency of the oscillator module 2053 fluctuates continuously and randomly according to the voltage of the random voltage generating module 2052, and the generated clock signal is used as the switch control signal of the inverter circuit.

[0077] The oscillator module 2053 uses an RC oscillator, and its frequency is negatively correlated with the value of the output voltage Vssm of the random voltage generating module 2052. The oscillation frequency fluctuates according to the output voltage Vssm of the random voltage generating module 2052, and the fluctuation is continuously and randomly changed.

[0078] Specifically, after the random code B0 generated by the second D flip-flop D0, the random code B1 generated by the third D flip-flop D1, the random code B2 generated by the fourth D flip-flop D2, the random code B3 generated by the fifth D flip-flop D3, and the random code B4 generated by the sixth D flip-flop D4 are respectively input to the first NOR gate NOR0, the second NOR gate NOR1, the third NOR gate NOR2, the fourth NOR gate NOR3, the first OR gate OR0, and the first XOR gate XOR0, the first XOR gate XOR0 outputs a high-level signal to the second D flip-flop D0, the frequency division module 2054 generates the second clock signal CLK' as the clock signal of the second D flip-flop D0, and the random code B0 generated by the second D flip-flop D0 and the second clock signal CLK' are used as the input of the third D flip-flop D1. And so on. The random code B0 generated by the second D flip-flop D0, the random code B1 generated by the third D flip-flop D1, the random code B2 generated by the fourth D flip-flop D2, the random code B3 generated by the fifth D flip-flop D3, and the random code B4 generated by the sixth D flip-flop D4 are respectively connected to the first switch S0, the second switch S1, the third switch S2, the fourth switch S3, and the fifth switch S4. When the random code is at a high level, the corresponding switch is closed. The first current source I1 flows through the binary resistor array to generate the output voltage Vssm of the random voltage generating module 2052. The change speed of the output voltage Vssm of the random voltage generating module 2052 is determined by the time constant of the node, and the time constant of the point can be further controlled by adjusting the size of the first capacitor Cssm. The second capacitor C1 can be charged by the second current source I2, and the charging voltage is input to the comparator P1 for comparison with the output voltage Vssm of the random voltage generating module 2052. When the charging voltage of the second capacitor C1 is greater than the output voltage Vssm of the random voltage generating module 2052, the charging voltage of the second capacitor C1 is discharged through the MOS tube M1, and this process is repeated to achieve oscillation. The oscillator module 2053 adopts an RC oscillator, and its frequency is negatively correlated with the value of the output voltage Vssm of the random voltage generating module 2052. The oscillation frequency fluctuates continuously and randomly according to the output voltage Vssm of the random voltage generating module 2052, and this fluctuation is continuously and randomly changed. The output voltage of the comparator P1 is input to the first D flip-flop D5 to generate the first clock signal CLK, and the first clock signal CLK generated by the first D flip-flop D5 is used as the input clock signal of the first D flip-flop D5. The first clock signal CLK generated by the first D flip-flop D5 is generated by the frequency dividing module 2054 to generate the second clock signal CLK', which can be used as the input clock signal of the second D flip-flop D0, the third D flip-flop D1, the fourth D flip-flop D2, the fifth D flip-flop D3 and the sixth D flip-flop D4.

[0079] Figure 7 is a waveform in the time domain of the continuous random spread spectrum scheme and other spread spectrum schemes proposed according to an embodiment of the present invention; Figure 8This is the spreading effect of the continuous random spreading scheme proposed in the embodiment of the present invention on the electromagnetic interference energy in the frequency domain compared with other spreading schemes. Figure 7 and Figure 8 As shown in FIG. 1 , the effect comparison between the continuous random spread spectrum scheme proposed by the present invention and the traditional spread spectrum scheme is shown. The traditional periodic triangular wave modulation has a single modulation frequency, so Figure 8 The EMI noise after spread spectrum modulation will produce f m The EMI noise energy is not evenly dispersed, which limits the effect of spread spectrum. Digital spread spectrum uses discrete digital signals to distribute the switching frequency in the frequency domain. Figure 8 The mid-frequency spectrum produces discrete spectrum peaks, which limits the effect of spectrum spreading. The present invention proposes a continuous random spectrum spreading scheme, which has a uniform and continuous time domain waveform, can ensure that the frequency is evenly distributed in the frequency domain; and has a complex modulation frequency component, which can eliminate the peaks related to the modulation frequency in the spectrum. Therefore, the scheme of the present invention obtains a flat and uniform spectrum distribution, which is closest to the ideal spectrum spreading effect and reduces the electromagnetic interference problem in the isolated power supply system.

[0080] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0081] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A low electromagnetic interference isolated power supply system, characterized in that: include: Inverter circuit, transformer, rectifier circuit, feedback control circuit, spread spectrum clock generation circuit and control drive circuit; The inverter circuit is connected to the transformer, and the inverter circuit is used to convert the input direct current into a differential high-frequency oscillation power signal and output it to the transformer; The transformer is connected to the rectifier circuit; The rectifier circuit is connected to the feedback control circuit, and the rectifier circuit is used to rectify the output of the transformer; The feedback control circuit is connected to the spread spectrum clock generating circuit, and the feedback control circuit is used to feed back the output voltage of the rectifier circuit to the spread spectrum clock generating circuit; The spread spectrum clock generating circuit is connected to the control driving circuit, and the spread spectrum clock generating circuit is used to generate a spread spectrum clock signal; The control driving circuit is connected to the inverter circuit, and the control driving circuit is used to output a switch control signal for controlling the inverter circuit according to the spread spectrum clock signal.

2. The system according to claim 1, characterized in that The spread spectrum clock generation circuit includes a random code generation module, a random voltage generation module, an oscillator module and a frequency division module; The random code generation module is connected to the random voltage generation module, and the random code generation module is used to generate a pseudo-random code with a repetitive period; The random voltage generating module is connected to the oscillator module, and the random voltage generating module is used to generate a continuously randomly fluctuating output voltage; The oscillator module is connected to the frequency division module; The frequency division module is connected to the oscillator module and the random code generation module, and is used to generate a frequency division signal as a clock signal of the random code generation module to drive it to generate a random code.

3. The system according to claim 2, characterized in that The random voltage generating module includes a plurality of switches, a binary resistor array, a sixth resistor, a first current source and a first capacitor; The plurality of switches are connected in parallel with the plurality of resistors in the binary resistor array in a one-to-one correspondence; the sixth resistor is connected between the first current source and the binary resistor array; A first end of the first capacitor is connected to a first end of the sixth resistor, and a second end of the first capacitor is grounded.

4. The system according to claim 3, characterized in that The binary resistor array includes a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor; The multiple switches include a first switch, a second switch, a third switch, a fourth switch and a fifth switch, which are connected in series in sequence, the first switch is connected in parallel with the fifth resistor, the second switch is connected in parallel with the fourth resistor, the third switch is connected in parallel with the third resistor, the fourth switch is connected in parallel with the second resistor, the fifth switch is connected in parallel with the first resistor, a first end of the sixth resistor is connected to the first current source, and a second end of the sixth resistor is connected to a first end of the fifth resistor and a first end of the first switch.

5. The system according to claim 2, characterized in that The oscillator module includes a second current source, a comparator, a second capacitor, a MOS tube and a first D trigger, wherein the first end of the second current source is connected to a power supply signal, the second end of the second current source is connected to the first end of the second capacitor, the second end of the second capacitor is grounded, the first input end of the comparator is connected to the output end of the random voltage generation module, the second input end of the comparator is connected to the first end of the second capacitor and the first electrode of the MOS tube, the gate of the MOS tube is connected to the second electrode of the second capacitor and is grounded, the second electrode of the MOS tube is connected to the output end of the comparator and connected to the second input end of the first D trigger, and the output end of the first D trigger is connected to the first input end of the first D trigger.

6. The system according to claim 2, characterized in that The random code generation module includes a linear feedback shift register, a first NOR gate, a second NOR gate, a third NOR gate, a fourth NOR gate, a first OR gate and a first XOR gate; The linear feedback shift register includes a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop and a sixth D flip-flop; The first input end of the first NOR gate inputs the output signal of the second D flip-flop, the second input end of the first NOR gate inputs the output signal of the third D flip-flop, the first input end of the second NOR gate inputs the output signal of the fourth D flip-flop, the second input end of the second NOR gate inputs the output signal of the fifth D flip-flop, the first input end of the third NOR gate inputs the output signal of the first NOR gate, the second input end of the third NOR gate inputs the output signal of the second NOR gate, the first input end of the fourth NOR gate inputs the output signal of the sixth D flip-flop, the second input end of the fourth NOR gate inputs the output signal of the third NOR gate, the first input end of the first OR gate inputs the output signal of the fourth NOR gate, the second input end of the first OR gate inputs the output signal of the sixth D flip-flop, the first input end of the first XOR gate inputs the output signal of the first OR gate, and the second input end of the first XOR gate inputs the output signal of the fourth D flip-flop.

7. The system according to claim 6, characterized in that The random code generation module generates a pseudo-random code sequence with a repetition period according to the characteristic polynomial of the linear feedback shift register.

8. The system according to claim 3, characterized in that The output voltage of the random voltage generating module is generated according to the first current source flowing through the binary resistor array.

9. The system according to claim 3, characterized in that The capacitance value of the first capacitor is adjustable.

10. The system according to claim 4, characterized in that The oscillation frequency of the oscillator module fluctuates continuously and randomly according to the voltage of the random voltage generating module, and the generated clock signal is used as the switch control signal of the inverter circuit.

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