Negative pressure detection circuit and adaptive dead-time control system

Abstract

The present invention provides a negative voltage detection circuit and an adaptive dead time control system. Among them, the negative voltage detection circuit includes: a first-side negative voltage detection module, which obtains a first-side sampling voltage based on the gate voltage of the low-side switching transistor in the half-bridge circuit, and generates a first-side negative voltage signal when the first-side sampling voltage is less than the reference voltage; a second-side negative voltage detection module, which obtains a second-side sampling voltage based on the node voltage of the high-side switching transistor and the low-side switching transistor in the half-bridge circuit, and generates a second-side negative voltage signal when the second-side sampling voltage is less than the reference voltage. Through the negative voltage detection circuit and the adaptive dead time control system provided by the present invention, the problems of low accuracy and the like existing in the traditional negative voltage detection circuit are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a negative voltage detection circuit and an adaptive dead time control system. Background Art

[0002] With the continuous improvement of the performance and power density requirements of electronic devices, the high efficiency, small size, and high power density of switched-mode power supplies have become research hotspots; the synchronous rectifier buck conversion circuit, as a type of high-frequency switched-mode power supply, has been widely used in fields such as communication equipment, data centers, and consumer electronics.

[0003] The performance of traditional silicon-based power devices in high-frequency switched-mode power supplies is gradually approaching its limit. Gallium nitride power devices have become the core devices of the next-generation power electronics technology due to their low on-resistance, high switching speed, and high-frequency operation ability. In high-frequency switched-mode power supplies, the setting of dead time has an important impact on system efficiency and reliability. An unreasonable dead time may lead to reduced efficiency, distorted switching waveforms, and high-frequency interference problems. Traditional fixed dead time control circuits are difficult to adapt to the changes in the switching characteristics of gallium nitride power devices under different loads and operating conditions, while adaptive dead time control circuits can reduce the reverse conduction loss of gallium nitride power devices and improve system efficiency, but have high requirements for the accuracy of the negative voltage detection circuit. However, most traditional negative voltage detection circuits have complex structures and low accuracy, making it difficult to meet the requirements.

[0004] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art merely because these solutions are described in the background art section of the present invention. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a negative voltage detection circuit and an adaptive dead time control system to solve the problems such as low accuracy existing in traditional negative voltage detection circuits.

[0006] To achieve the above purpose and other related purposes, the present invention provides a negative voltage detection circuit, which includes:

[0007] A first-side negative voltage detection module, which obtains a first-side sampling voltage based on the gate voltage of the low-side switch tube in the half-bridge circuit and generates a first-side negative voltage signal when the first-side sampling voltage is less than the reference voltage;

[0008] A second-side negative voltage detection module, which obtains a second-side sampling voltage based on the node voltage of the high-side switch tube and the low-side switch tube in the half-bridge circuit and generates a second-side negative voltage signal when the second-side sampling voltage is less than the reference voltage.

[0009] Optionally, the first-side negative-pressure detection module includes:

[0010] A first-side pulse unit, configured to generate a first-side pulse signal at the falling edge of the gate voltage of the low-side switching transistor;

[0011] A first-side sampling unit, connected to the first-side pulse unit, and configured to sample the node voltage to obtain the first-side sampling voltage when the first-side pulse signal is valid;

[0012] A first-side comparison unit, connected to the first-side sampling unit, and configured to generate the first-side negative-pressure signal based on a comparison result between the first-side sampling voltage and the reference voltage.

[0013] Optionally, the first-side pulse unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first capacitor, a second capacitor, a first Schmitt trigger, and a first NAND gate. The input terminal of the first inverter receives the gate voltage of the low-side switching transistor. The output terminal of the first inverter is connected to the first input terminal of the first NAND gate and is sequentially connected to the input terminal of the first Schmitt trigger through the second inverter and the third inverter. The output terminal of the first inverter is also sequentially connected to the input terminal of the first Schmitt trigger through the first capacitor and the second capacitor. The output terminal of the first Schmitt trigger is connected to the second input terminal of the first NAND gate through the fourth inverter. The output terminal of the first NAND gate outputs the first-side pulse signal, where a connection node of the first capacitor and the second capacitor is connected to the reference ground.

[0014] Optionally, the first-side sampling unit includes a third capacitor, a fourth capacitor, a first NMOS transistor, a second NMOS transistor, and a first PMOS transistor. Among them, the first end of the third capacitor receives the node voltage, the second end of the third capacitor is connected to the drains of the first NMOS transistor and the second NMOS transistor, the gate of the first NMOS transistor is connected to the gate voltage of the low-side switch transistor, the source of the first NMOS transistor is connected to the drain of the first PMOS transistor, the gate of the first PMOS transistor is connected to the inverted signal of the gate voltage of the low-side switch transistor, the source of the first PMOS transistor is connected to a first voltage, the gate of the second NMOS transistor receives the first-side pulse signal, and the source of the second NMOS transistor is connected to the reference ground through the fourth capacitor and outputs the first-side sampling voltage; or, the first-side sampling unit further includes a third NMOS transistor and a fourth NMOS transistor. Among them, the gates of the third NMOS transistor and the fourth NMOS transistor are both connected to the gate voltage of the low-side switch transistor, the drain of the third NMOS transistor is connected to the source of the second NMOS transistor, the source of the third NMOS transistor is connected to the source of the fourth NMOS transistor, and the drain of the fourth NMOS transistor is connected to the reference ground.

[0015] Optionally, the second-side negative voltage detection module includes:

[0016] A voltage processing unit for step-down processing of the node voltage to obtain an intermediate voltage;

[0017] A second-side pulse unit connected to the voltage processing unit for generating a second-side pulse signal at the falling edge of the intermediate voltage;

[0018] A second-side sampling unit connected to the second-side pulse unit for sampling the node voltage to obtain the second-side sampling voltage when the second-side pulse signal is valid;

[0019] A second-side comparison unit connected to the second-side sampling unit for generating the second-side negative voltage signal based on the comparison result between the second-side sampling voltage and the reference voltage.

[0020] Optionally, the voltage processing unit includes a fifth NMOS transistor, a resistor, and a zener diode. Among them, the gate of the fifth NMOS transistor is connected to the operating voltage, the drain of the fifth NMOS transistor receives the node voltage, the source of the fifth NMOS transistor is connected to the reference ground through the resistor and outputs the intermediate voltage, and the zener diode is connected in parallel across the two ends of the resistor; or, the voltage processing unit further includes a second Schmitt trigger, and the intermediate voltage is output after being shaped by the second Schmitt trigger.

[0021] Optionally, the second-side pulse unit includes a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a fifth capacitor, a sixth capacitor, a third Schmitt trigger, and a second NAND gate. The input terminal of the fifth inverter receives the intermediate voltage. The output terminal of the fifth inverter is connected to the first input terminal of the second NAND gate and is sequentially connected to the input terminal of the third Schmitt trigger through the sixth inverter and the seventh inverter. The output terminal of the fifth inverter is also sequentially connected to the input terminal of the third Schmitt trigger through the fifth capacitor and the sixth capacitor. The output terminal of the third Schmitt trigger is connected to the second input terminal of the second NAND gate through the eighth inverter. The output terminal of the second NAND gate outputs the second-side pulse signal, where the connection node of the fifth capacitor and the sixth capacitor is connected to the reference ground.

[0022] Optionally, the second-side sampling unit includes a seventh capacitor, an eighth capacitor, a sixth NMOS transistor, a seventh NMOS transistor, and a second PMOS transistor. The first terminal of the seventh capacitor receives the node voltage. The second terminal of the seventh capacitor is connected to the drain of the sixth NMOS transistor and the drain of the seventh NMOS transistor. The gate of the sixth NMOS transistor is connected to the gate voltage of the low-side switch transistor. The source of the sixth NMOS transistor is connected to the drain of the second PMOS transistor. The gate of the second PMOS transistor is connected to the inverted signal of the gate voltage of the low-side switch transistor. The source of the second PMOS transistor is connected to the second voltage. The gate of the seventh NMOS transistor receives the second-side pulse signal. The source of the seventh NMOS transistor is connected to the reference ground through the eighth capacitor and outputs the second-side sampling voltage. Alternatively, the second-side sampling unit further includes an eighth NMOS transistor and a ninth NMOS transistor. The gates of the eighth NMOS transistor and the ninth NMOS transistor are both connected to the intermediate voltage. The drain of the eighth NMOS transistor is connected to the source of the seventh NMOS transistor. The source of the eighth NMOS transistor is connected to the source of the ninth NMOS transistor. The drain of the ninth NMOS transistor is connected to the reference ground.

[0023] Optionally, the negative pressure detection circuit further includes a reference providing module, which includes a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, and a twelfth capacitor. Among them, the gates of the tenth NMOS transistor and the eleventh NMOS transistor are both connected to the gate voltage of the low-side switching transistor. The drain of the tenth NMOS transistor receives the node voltage. The source of the tenth NMOS transistor is connected to the source of the eleventh NMOS transistor. The drain of the eleventh NMOS transistor is connected to the drain of the third PMOS transistor. The gate of the third PMOS transistor is connected to the inverted signal of the gate voltage of the low-side switching transistor through the ninth capacitor. The gate of the third PMOS transistor is also sequentially connected to its drain through the fourth PMOS transistor and the fifth PMOS transistor in diode connection. The source of the third PMOS transistor is connected to the source of the sixth PMOS transistor and is connected to the drains of the twelfth NMOS transistor and the thirteenth NMOS transistor through the tenth capacitor. The gate of the sixth PMOS transistor is connected to the gate voltage of the low-side switching transistor through the eleventh capacitor and is connected to the reference ground through the seventh PMOS transistor in diode connection. The drain of the sixth PMOS transistor is connected to the reference ground. The gate of the twelfth NMOS transistor is connected to the gate voltage of the low-side switching transistor. The source of the twelfth NMOS transistor is connected to the third voltage. The gate of the thirteenth NMOS transistor is connected to the inverted signal of the gate voltage of the low-side switching transistor. The source of the thirteenth NMOS transistor is connected to the reference ground through the twelfth capacitor and outputs the reference voltage.

[0024] The present invention also provides an adaptive dead-time control system, which includes the negative pressure detection circuit as described in any one of the above.

[0025] As described above, the negative pressure detection circuit and the adaptive dead-time control system of the present invention propose a brand-new negative pressure detection scheme through the design of the first-side negative pressure detection module and the second-side negative pressure detection module. By using a pulse signal to turn on the sampling transistor to trigger the charging process, the accuracy of the dead-time information sampling timing is guaranteed, thereby improving the detection accuracy. The present invention has the characteristics of small delay, high efficiency, high stability, and high adaptability. Description of the Drawings

[0026] Figure 1 It shows a schematic structural diagram of the negative pressure detection circuit in the embodiment of the present invention.

[0027] Figure 2 It shows a schematic structural diagram of the first-side pulse unit in the embodiment of the present invention.

[0028] Figure 3 It shows a schematic structural diagram of the first-side sampling unit in an embodiment of the present invention.

[0029] Figure 4 It shows a schematic structural diagram of the voltage processing unit in an embodiment of the present invention.

[0030] Figure 5 It shows a schematic structural diagram of the second-side pulse unit in an embodiment of the present invention.

[0031] Figure 6 It shows a schematic structural diagram of the second-side sampling unit in an embodiment of the present invention.

[0032] Figure 7 It shows a schematic structural diagram of the reference providing module in an embodiment of the present invention.

[0033] Description of component numbers: 100 negative pressure detection circuit, 110 first-side negative pressure detection module, 111 first-side pulse unit, 112 first-side sampling unit, 113 first-side comparison unit, 120 second-side negative pressure detection module, 121 voltage processing unit, 122 second-side pulse unit, 123 second-side sampling unit, 124 second-side comparison unit, 130 reference providing module, 200 dead time generation circuit, 300 low-side signal adjustment circuit, 400 high-side signal adjustment circuit, 500 low-side drive circuit, 600 high-side drive circuit, 700 half-bridge circuit. Specific embodiments

[0034] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] Please refer to Figures 1 to 7 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The forms, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout form may also be more complex.

[0036] As Figure 1 shown, this embodiment provides a negative pressure detection circuit 100, including a first-side negative pressure detection module 110 and a second-side negative pressure detection module 120. Further, it also includes a reference providing module 130.

[0037] The first-side negative voltage detection module 110 obtains a first-side sampling voltage VI1 based on the gate voltage VGL of the low-side switch tube in the half-bridge circuit, and generates a first-side negative voltage signal Q1 when the first-side sampling voltage VI1 is less than the reference voltage VREF, thereby realizing the detection of the first-side dead time. In one example, as Figures 1 to 3 shown, the first-side negative voltage detection module 110 includes a first-side pulse unit 111, a first-side sampling unit 112, and a first-side comparison unit 113.

[0038] The first-side pulse unit 111 is configured to generate a first-side pulse signal PULSE1 at the falling edge of the gate voltage VGL of the low-side switch tube. In one embodiment, as Figure 2 shown, the first-side pulse unit 111 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first capacitor C1, a second capacitor C2, a first Schmitt trigger SMBUF1, and a first NAND gate NAND1; wherein, the input terminal of the first inverter INV1 receives the gate voltage VGL of the low-side switch tube, the output terminal of the first inverter INV1 is connected to the first input terminal of the first NAND gate NAND1 and is sequentially connected to the input terminal of the first Schmitt trigger SMBUF1 through the second inverter INV2 and the third inverter INV3, the output terminal of the first inverter INV1 is also sequentially connected to the input terminal of the first Schmitt trigger SMBUF1 through the first capacitor C1 and the second capacitor C2, the output terminal of the first Schmitt trigger SMBUF1 is connected to the second input terminal of the first NAND gate NAND1 through the fourth inverter INV4, and the output terminal of the first NAND gate NAND1 serves as the output terminal of the first-side pulse unit 111 to output the first-side pulse signal PULSE1, wherein the connection node of the first capacitor C1 and the second capacitor C2 is also connected to the reference ground.

[0039] The first-side sampling unit 112 is connected to the first-side pulse unit 111, and is configured to sample the node voltage VSW to obtain the first-side sampling voltage VI1 when the first-side pulse signal PULSE1 is valid. In one embodiment, as Figure 3As shown in the figure, the first-side sampling unit 112 includes a third capacitor C3, a fourth capacitor C4, a first NMOS transistor MN1, a second NMOS transistor MN2, and a first PMOS transistor MP1. Among them, the first end of the third capacitor C3 receives the node voltage VSW. The second end of the third capacitor C3 is connected to the drain of the first NMOS transistor MN1 and the drain of the second NMOS transistor MN2. The gate of the first NMOS transistor MN1 is connected to the gate voltage VGL of the low-side switch transistor. The source of the first NMOS transistor MN1 is connected to the drain of the first PMOS transistor MP1. The gate of the first PMOS transistor MP1 is connected to the inverted signal VGLB of the gate voltage of the low-side switch transistor. The source of the first PMOS transistor MP1 is connected to the first voltage VDL1. The gate of the second NMOS transistor MN2 receives the first-side pulse signal PULSE1. The source of the second NMOS transistor MN2 is connected to the reference ground through the fourth capacitor C4 and serves as the output terminal of the first-side sampling unit 112 to output the first-side sampling voltage VI1. Further, the first-side sampling unit 112 further includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4. Among them, the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are both connected to the gate voltage VGL of the low-side switch transistor. The drain of the third NMOS transistor MN3 is connected to the source of the second NMOS transistor MN2. The source of the third NMOS transistor MN3 is connected to the source of the fourth NMOS transistor MN4. The drain of the fourth NMOS transistor MN4 is connected to the reference ground.

[0040] In this embodiment, the first NMOS transistor MN1 and the first PMOS transistor MP1 form a dual-switch structure, which can charge the right plate of the third capacitor C3 to the first voltage VDL1. Among them, when the half-bridge circuit is in the non-dead zone state, the voltage of the right plate of the third capacitor C3 is approximately VDL1 + VDSON (VDSON is the on-voltage drop of the low-side switch transistor ML). When the half-bridge circuit is in the dead zone state, the voltage of the right plate of the third capacitor C3 is approximately VDL1 + VDSON + VDT (VDT is the value of the node voltage VSW in the dead zone state). When the first-side pulse signal PULSE1 is at a high level, the second NMOS transistor MN2 conducts and starts sampling to generate the first-side sampling voltage VI1. When the gate voltage VGL of the low-side switch transistor is at a high level, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 conduct, pulling down the output to achieve the clearing function.

[0041] The first-side comparison unit 113 is connected to the first-side sampling unit 112 and generates a first-side negative voltage signal Q1 based on the comparison result between the first-side sampling voltage VI1 and the reference voltage VREF. In one embodiment, as Figure 1As shown, the first-side comparison unit 113 is implemented by the first comparator CMP1. Among them, the non-inverting input terminal of the first comparator CMP1 receives the first-side sampling voltage VI1, the inverting input terminal of the first comparator CMP1 receives the reference voltage VREF, and the output terminal of the first comparator CMP1 serves as the output terminal of the first-side comparison unit 113 to output the first-side negative voltage signal Q1.

[0042] The second-side negative voltage detection module 120 obtains the second-side sampling voltage VI2 based on the node voltage VSW of the high-side switch and the low-side switch in the half-bridge circuit, and generates the second-side negative voltage signal Q2 when the second-side sampling voltage VI2 is less than the reference voltage VREF, thereby realizing the detection of the second-side dead time. In one example, as Figure 1 、 Figures 4 to 6 shown, the second-side negative voltage detection module 120 includes a voltage processing unit 121, a second-side pulse unit 122, a second-side sampling unit 123, and a second-side comparison unit 124.

[0043] The voltage processing unit 121 is used to step down the node voltage VSW to obtain the intermediate voltage VGH1. In one implementation, as Figure 4 shown, the voltage processing unit 121 includes a fifth NMOS transistor MN5, a resistor R, and a zener diode D; among them, the gate of the fifth NMOS transistor MN5 is connected to the operating voltage VDD, the drain of the fifth NMOS transistor MN5 receives the node voltage VSW, the source of the fifth NMOS transistor MN5 is connected to the reference ground through the resistor R and outputs the intermediate voltage VGH1 (that is, the source of the fifth NMOS transistor MN5 is connected to the first end of the resistor R and outputs the intermediate voltage VGH1, and the second end of the resistor R is connected to the reference ground), and the zener diode D is connected in parallel across the two ends of the resistor R (that is, the cathode of the zener diode D is connected to the first end of the resistor R, and the anode of the zener diode D is connected to the second end of the resistor R). Further, the voltage processing unit 121 further includes a second Schmidt trigger SMBUF2, where the input terminal of the second Schmidt trigger SMBUF2 is connected to the source of the fifth NMOS transistor MN5, and the output terminal of the second Schmidt trigger SMBUF2 serves as the output terminal of the voltage processing unit 121. At this time, the intermediate voltage VGH1 is output after being shaped by the second Schmidt trigger SMBUF2. By processing the signal in the floating domain through the voltage processing unit 121 of this implementation, the signal delay can be smaller and the signal edge can be more accurate.

[0044] The second-side pulse unit 122 is connected to the voltage processing unit 121 and is used to generate the second-side pulse signal PULSE2 at the falling edge of the intermediate voltage VGH1. In one implementation, as Figure 5As shown, the second-side pulse unit 122 includes a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a fifth capacitor C5, a sixth capacitor C6, a third Schmitt trigger SMBUF3, and a second NAND gate NAND2. Among them, the input terminal of the fifth inverter INV5 receives the intermediate voltage VGH1. The output terminal of the fifth inverter INV5 is connected to the first input terminal of the second NAND gate NAND2 and is sequentially connected to the input terminal of the third Schmitt trigger SMBUF3 through the sixth inverter INV6 and the seventh inverter INV7. The output terminal of the fifth inverter INV5 is also sequentially connected to the input terminal of the third Schmitt trigger SMBUF3 through the fifth capacitor C5 and the sixth capacitor C6. The output terminal of the third Schmitt trigger SMBUF3 is connected to the second input terminal of the second NAND gate NAND2 through the eighth inverter INV8. The output terminal of the second NAND gate NAND2 serves as the output terminal of the second-side pulse unit 122 to output the second-side pulse signal PULSE2. Among them, the connection node of the fifth capacitor C5 and the sixth capacitor C6 is also connected to the reference ground.

[0045] The second-side sampling unit 123 is connected to the second-side pulse unit 122 and is used to sample the node voltage VSW to obtain the second-side sampling voltage VI2 when the second-side pulse signal PULSE2 is valid. In one embodiment, as Figure 6 shown, the second-side sampling unit 123 includes a seventh capacitor C7, an eighth capacitor C8, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and a second PMOS transistor MP2. Among them, the first end of the seventh capacitor C7 receives the node voltage VSW. The second end of the seventh capacitor C7 is connected to the drain of the sixth NMOS transistor MN6 and the drain of the seventh NMOS transistor MN7. The gate of the sixth NMOS transistor MN6 is connected to the gate voltage VGL of the low-side switch transistor. The source of the sixth NMOS transistor MN6 is connected to the drain of the second PMOS transistor MP2. The gate of the second PMOS transistor MP2 is connected to the inverted signal VGLB of the gate voltage of the low-side switch transistor. The source of the second PMOS transistor MP2 is connected to the second voltage VDL2. The gate of the seventh NMOS transistor MN7 receives the second-side pulse signal PULSE2. The source of the seventh NMOS transistor MN7 is connected to the reference ground through the eighth capacitor C8 and serves as the output terminal of the second-side sampling unit 123 to output the second-side sampling voltage VI2. Further, the second-side sampling unit 123 further includes an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9. Among them, the gates of the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are both connected to the intermediate voltage VGH1. The drain of the eighth NMOS transistor MN8 is connected to the source of the seventh NMOS transistor MN7. The source of the eighth NMOS transistor MN8 is connected to the source of the ninth NMOS transistor MN9. The drain of the ninth NMOS transistor MN9 is connected to the reference ground.

[0046] In this embodiment, the sixth NMOS transistor MN6 and the second PMOS transistor MP2 form a double-switch structure, which can charge the right plate of the seventh capacitor C7 to the second voltage VDL2. Among them, when the half-bridge circuit is in the non-dead zone state, the voltage of the right plate of the seventh capacitor C7 is approximately VDL2 + VDSON (VDSON is the conduction voltage drop of the low-side switch transistor ML). When the half-bridge circuit is in the dead zone state, the voltage of the right plate of the seventh capacitor C7 is approximately VDL2 + VDSON + VDT (VDT is the value of the node voltage VSW in the dead zone state). When the second-side pulse signal PULSE2 is at a high level, the seventh NMOS transistor MN7 conducts and starts sampling to generate the second-side sampling voltage VI2. When the intermediate voltage VGH1 is at a high level, the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 conduct, pulling down the output to achieve the clear function.

[0047] The second-side comparison unit 124 is connected to the second-side sampling unit 123, and generates a second-side negative voltage signal Q2 based on the comparison result between the second-side sampling voltage VI2 and the reference voltage VREF. In one embodiment, as Figure 1 shown, the second-side comparison unit 124 is implemented by using a second comparator CMP2. Among them, the non-inverting input terminal of the second comparator CMP2 receives the second-side sampling voltage VI2, the inverting input terminal of the second comparator CMP2 receives the reference voltage VREF, and the output terminal of the second comparator CMP2 serves as the output terminal of the second-side comparison unit 124 to output the second-side negative voltage signal Q2.

[0048] The reference providing module 130 is used to provide the reference voltage VREF. In practical applications, the reference providing module 130 generates the reference voltage VREF based on the node voltage VSW.

[0049] In one embodiment, as Figure 7As shown, the reference providing module 130 includes a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, and a twelfth capacitor C12; wherein, the gates of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are both connected to the gate voltage VGL of the low-side switching transistor, the drain of the tenth NMOS transistor MN10 receives the node voltage VSW, the source of the tenth NMOS transistor MN10 is connected to the source of the eleventh NMOS transistor MN11, the drain of the eleventh NMOS transistor MN11 is connected to the drain of the third PMOS transistor MP3, the gate of the third PMOS transistor MP3 is connected to the inverted signal VGLB of the gate voltage of the low-side switching transistor via the ninth capacitor C9, and the gate of the third PMOS transistor MP3 is also connected to the drain of the third PMOS transistor MP3 (i.e., the gate of the third PMOS transistor MP3 is also connected to the drain of the fourth PMOS transistor MP4, the gate and source of the fourth PMOS transistor MP4 are connected to each other and connected to the drain of the fifth PMOS transistor MP5, and the gate and source of the fifth PMOS transistor MP5 are connected to each other and connected to the drain of the third PMOS transistor MP3) via the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 connected in diode configuration, the source of the third PMOS transistor MP3 is connected to the source of the sixth PMOS transistor MP6 and connected to the drain of the twelfth NMOS transistor MN12 and the drain of the thirteenth NMOS transistor MN13 via the tenth capacitor C10, the gate of the sixth PMOS transistor MP6 is connected to the gate voltage VGL of the low-side switching transistor via the eleventh capacitor C11 and connected to the reference ground via the seventh PMOS transistor MP7 connected in diode configuration (i.e., the gate of the sixth PMOS transistor MP6 is also connected to the drain of the seventh PMOS transistor MP7, and the gate and source of the seventh PMOS transistor MP7 are connected to each other and connected to the reference ground), the drain of the sixth PMOS transistor MP6 is connected to the reference ground, the gate of the twelfth NMOS transistor MN12 is connected to the gate voltage VGL of the low-side switching transistor, the source of the twelfth NMOS transistor MN12 is connected to the third voltage VDL3, the gate of the thirteenth NMOS transistor MN13 is connected to the inverted signal VGLB of the gate voltage of the low-side switching transistor, and the source of the thirteenth NMOS transistor MN13 is connected to the reference ground via the twelfth capacitor C12 and serves as the output terminal of the reference providing module 130 to output the reference voltage VREF. As an alternative, the voltage values of the third voltage VDL3 and the first voltage VDL1 are equal and less than the voltage value of the second voltage VDL2. It should be noted that a PMOS transistor connected in diode configuration means that the drain of the PMOS transistor serves as the anode of the diode, and the gate and source of the PMOS transistor are connected to each other to serve as the cathode of the diode.

[0050] Correspondingly, as Figure 1 shown, this embodiment also provides an adaptive dead-time control system, including a negative pressure detection circuit 100. Further, it further includes a dead-time generation circuit 200, a low-side signal adjustment circuit 300, a high-side signal adjustment circuit 400, a low-side drive circuit 500, a high-side drive circuit 600, and a half-bridge circuit 700.

[0051] The negative pressure detection circuit 100 is implemented by the circuit structure described above. It is used to monitor the change of the node voltage VSW of the high-side switch tube MH and the low-side switch tube ML in the half-bridge circuit 700 in real time, and sample the node voltage VSW based on the first-side pulse signal PULSE1 to detect the first-side dead time, and sample the node voltage VSW based on the second-side pulse signal PULSE2 to detect the second-side dead time, so as to make the adjustment of the dead time more accurate and dynamic. It should be noted that the first side and the second side are referenced by the node voltage VSW. Usually, the first side refers to the left side of the node voltage VSW, and the second side refers to the right side of the node voltage VSW.

[0052] The dead-time generation circuit 200 generates a low-side initial signal PWML and a high-side initial signal PWMH based on the input signal; among them, the low-side initial signal PWML and the high-side initial signal PWMH are a group of non-overlapping signals, and there is a dead time between them.

[0053] The low-side signal adjustment circuit 300 receives the low-side initial signal PWML and the second-side negative pressure signal Q2, and adjusts the waveform of the low-side initial signal PWML based on the second-side negative pressure signal Q2. For example, it delays the rising edge of the low-side initial signal PWML and keeps the falling edge of the low-side initial signal PWML unchanged, thereby reducing the dead time.

[0054] The high-side signal adjustment circuit 400 receives the high-side initial signal PWMH and the first-side negative pressure signal Q1, and adjusts the waveform of the high-side initial signal PWMH based on the first-side negative pressure signal Q1. For example, it delays the rising edge of the high-side initial signal PWMH and keeps the falling edge of the high-side initial signal PWMH unchanged, thereby reducing the dead time.

[0055] The low-side drive circuit 500 generates a low-side drive signal based on the adjusted low-side initial signal to drive the low-side switch tube ML in the half-bridge circuit 700.

[0056] The high-side drive circuit 600 generates a high-side drive signal based on the adjusted high-side initial signal to drive the high-side switch tube MH in the half-bridge circuit 700.

[0057] Through the collaborative work of the above-mentioned various circuits, the dead time of the half-bridge circuit composed of gallium nitride power devices can be monitored and adjusted in real time, effectively improving the overall performance and reliability of the system; by adjusting the dead time through the negative voltage detection circuit 100 of this embodiment, the dead time on both sides of the node voltage VSW can be controlled within 2 ns, approaching "zero dead time".

[0058] In summary, for a negative voltage detection circuit and an adaptive dead time control system of the present invention, through the design of the first-side negative voltage detection module and the second-side negative voltage detection module, a brand-new negative voltage detection scheme is proposed. The sampling tube is triggered by a pulse signal to start the charging process, ensuring the accuracy of the dead time information sampling timing, thereby improving the detection accuracy; the present invention has the characteristics of small delay, high efficiency, high stability, and high adaptability. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0059] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A negative pressure detection circuit, characterized in that: The negative pressure detection circuit comprises: A first-side negative voltage detection module, which obtains a first-side sampling voltage based on a gate voltage of a low-side switch tube in a half-bridge circuit, and generates a first-side negative voltage signal when the first-side sampling voltage is less than a reference voltage; A second-side negative pressure detection module, which obtains a second-side sampled voltage based on a node voltage of a high-side switch tube and a low-side switch tube in a half-bridge circuit, and generates a second-side negative pressure signal when the second-side sampled voltage is less than the reference voltage; Wherein, the first-side negative pressure detection module includes: A first side pulse unit, used for generating a first side pulse signal at a falling edge of the gate voltage of the low-side switch tube; A first side sampling unit, connected to the first side pulse unit, and configured to sample the node voltage to obtain the first side sampling voltage when the first side pulse signal is valid; a first-side comparison unit connected to the first-side sampling unit, and generating the first-side negative voltage signal based on a comparison result between the first-side sampling voltage and the reference voltage; The second side negative pressure detection module comprises: A voltage processing unit, used for performing voltage reduction processing on the node voltage to obtain an intermediate voltage; A second side pulse unit, connected to the voltage processing unit, and configured to generate a second side pulse signal at a falling edge of the intermediate voltage; A second-side sampling unit, connected to the second-side pulse unit, and configured to sample the node voltage to obtain the second-side sampling voltage when the second-side pulse signal is valid; The second-side comparison unit is connected to the second-side sampling unit, and generates the second-side negative voltage signal based on a comparison result between the second-side sampling voltage and the reference voltage.

2. The negative pressure detection circuit according to claim 1, characterized in that: The first side pulse unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first capacitor, a second capacitor, a first Schmitt trigger and a first NAND gate, wherein the input end of the first inverter receives the gate voltage of the low-side switch tube, the output end of the first inverter is connected to the first input end of the first NAND gate and is connected to the input end of the first Schmitt trigger in sequence through the second inverter and the third inverter, the output end of the first inverter is also connected to the input end of the first Schmitt trigger in sequence through the first capacitor and the second capacitor, the output end of the first Schmitt trigger is connected to the second input end of the first NAND gate through the fourth inverter, and the output end of the first NAND gate outputs the first side pulse signal, wherein the connection node of the first capacitor and the second capacitor is connected to the reference ground.

3. The negative pressure detection circuit according to claim 1, characterized in that: The first side sampling unit includes a third capacitor, a fourth capacitor, a first NMOS tube, a second NMOS tube and a first PMOS tube, wherein the first end of the third capacitor receives the node voltage, the second end of the third capacitor is connected to the drain of the first NMOS tube and the drain of the second NMOS tube, the gate of the first NMOS tube is connected to the gate voltage of the low-side switch tube, the source of the first NMOS tube is connected to the drain of the first PMOS tube, the gate of the first PMOS tube is connected to the inverted signal of the gate voltage of the low-side switch tube, and the source of the first PMOS tube is connected to the first voltage , the gate of the second NMOS tube receives the first side pulse signal, the source of the second NMOS tube is connected to the reference ground via the fourth capacitor and outputs the first side sampling voltage; or, the first side sampling unit also includes a third NMOS tube and a fourth NMOS tube, wherein the gate of the third NMOS tube and the gate of the fourth NMOS tube are both connected to the gate voltage of the low-side switch tube, the drain of the third NMOS tube is connected to the source of the second NMOS tube, the source of the third NMOS tube is connected to the source of the fourth NMOS tube, and the drain of the fourth NMOS tube is connected to the reference ground.

4. The negative pressure detection circuit according to claim 1, characterized in that: The voltage processing unit includes a fifth NMOS tube, a resistor and a voltage regulator diode, wherein the gate of the fifth NMOS tube is connected to the working voltage, the drain of the fifth NMOS tube receives the node voltage, the source of the fifth NMOS tube is connected to the reference ground via the resistor and outputs the intermediate voltage, and the voltage regulator diode is connected in parallel to both ends of the resistor; or, the voltage processing unit also includes a second Schmitt trigger, and the intermediate voltage is output after being shaped by the second Schmitt trigger.

5. The negative pressure detection circuit according to claim 1, characterized in that: The second side pulse unit includes a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a fifth capacitor, a sixth capacitor, a third Schmitt trigger and a second NAND gate, wherein the input end of the fifth inverter receives the intermediate voltage, the output end of the fifth inverter is connected to the first input end of the second NAND gate and is connected to the input end of the third Schmitt trigger via the sixth inverter and the seventh inverter in sequence, the output end of the fifth inverter is also connected to the input end of the third Schmitt trigger via the fifth capacitor and the sixth capacitor in sequence, the output end of the third Schmitt trigger is connected to the second input end of the second NAND gate via the eighth inverter, and the output end of the second NAND gate outputs the second side pulse signal, wherein the connection node of the fifth capacitor and the sixth capacitor is connected to the reference ground.

6. The negative pressure detection circuit according to claim 1, characterized in that: The second-side sampling unit includes a seventh capacitor, an eighth capacitor, a sixth NMOS tube, a seventh NMOS tube and a second PMOS tube, wherein the first end of the seventh capacitor receives the node voltage, the second end of the seventh capacitor is connected to the drain of the sixth NMOS tube and the drain of the seventh NMOS tube, the gate of the sixth NMOS tube is connected to the gate voltage of the low-side switch tube, the source of the sixth NMOS tube is connected to the drain of the second PMOS tube, the gate of the second PMOS tube is connected to the inverted signal of the gate voltage of the low-side switch tube, and the source of the second PMOS tube is connected to the The second side sampling unit further comprises an eighth NMOS tube and a ninth NMOS tube, wherein the gate of the eighth NMOS tube and the gate of the ninth NMOS tube are both connected to the intermediate voltage, the drain of the eighth NMOS tube is connected to the source of the seventh NMOS tube, the source of the eighth NMOS tube is connected to the source of the ninth NMOS tube, and the drain of the ninth NMOS tube is connected to the reference ground.

7. The negative pressure detection circuit according to any one of claims 1 to 6, characterized in that: The negative voltage detection circuit also includes a reference providing module, including a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a ninth capacitor, a tenth capacitor, an eleventh capacitor and a twelfth capacitor, wherein the gate of the tenth NMOS tube and the gate of the eleventh NMOS tube are both connected to the gate voltage of the low-side switch tube, the drain of the tenth NMOS tube receives the node voltage, the source of the tenth NMOS tube is connected to the source of the eleventh NMOS tube, the drain of the eleventh NMOS tube is connected to the drain of the third PMOS tube, the gate of the third PMOS tube is connected to the inverted signal of the gate voltage of the low-side switch tube via the ninth capacitor, and the gate of the third PMOS tube The drains of the fourth PMOS tube and the fifth PMOS tube connected in sequence are connected via diodes, the source of the third PMOS tube is connected to the source of the sixth PMOS tube and is connected to the drain of the twelfth NMOS tube and the drain of the thirteenth NMOS tube via the tenth capacitor, the gate of the sixth PMOS tube is connected to the gate voltage of the low-side switch tube via the eleventh capacitor and is connected to the reference ground via the seventh PMOS tube connected in diodes, the drain of the sixth PMOS tube is connected to the reference ground, the gate of the twelfth NMOS tube is connected to the gate voltage of the low-side switch tube, the source of the twelfth NMOS tube is connected to the third voltage, the gate of the thirteenth NMOS tube is connected to the inverted signal of the gate voltage of the low-side switch tube, and the source of the thirteenth NMOS tube is connected to the reference ground via the twelfth capacitor and outputs the reference voltage.

8. An adaptive dead time control system, characterized in that: The adaptive dead time control system comprises: a negative pressure detection circuit as described in any one of claims 1 to 7.

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