Common mode level generation circuit with buffer module, electronic circuit and electronic equipment

Abstract

The invention provides a common-mode level generation circuit with a buffer module, an electronic circuit and electronic equipment. The circuit comprises the buffer module, a transconductance operational amplifier module and a first resistor. The buffer module carries out level shift on the first output voltage and the second output voltage output by the integrator and the first reference voltage and the second reference voltage and outputs the voltages to the operational transconductance amplifier, and the operational transconductance amplifier is used for carrying out transconductance amplification on the input voltages and adding the voltages to obtain a first current and a second current. And if the first current is greater than the second current, the transconductance operational amplifier module outputs a step-down current, and the step-down current flows through the first resistor to generate voltage drop so as to reduce the output common-mode level. Therefore, according to the single-side modulation technology, the power consumption of the power supply is greatly reduced under the no-load condition of the D-type power amplifier, the efficiency is greatly improved when the D-type power amplifier is low in power, and the THDN performance of the circuit is prevented from being influenced by oversaturation of the first output voltage and the second output voltage.

Description

Technical Field

[0001] The invention relates to the field of class D amplifiers, and in particular to a common-mode level generating circuit with a buffer module, an electronic circuit and an electronic device. Background Art

[0002] The operation of the Class D amplifier requires converting the output analog signal into a pulse width modulated signal. It does this by modulating the input sinusoidal signal through an integrator and then comparing it with a higher frequency triangle wave through a comparator. If the voltage of the sinusoidal signal is higher than the triangle wave at a certain moment, the comparator outputs a high level, otherwise it outputs a low level. The duration of the high and low levels is determined by the time the difference between the two is generated. Therefore, a continuous sinusoidal signal will be modulated into a continuous pulse width modulated wave of different widths.

[0003] The prior art can achieve unilateral modulation by adjusting the output common-mode level of the integrator of the class D amplifier, so that the class D amplifier outputs a relatively small duty cycle when in an idle state, thereby saving power consumption; however, when the input signal increases, unilateral signal clipping is easily generated, resulting in a decrease in the quality of the audio signal; therefore, there is an urgent need for a dynamic and economical common-mode level generating circuit that can achieve a small duty cycle in the idle state and avoid the THDN increase problem when the output signal power increases. Summary of the invention

[0004] The present invention provides a common-mode level generating circuit with a buffer module, an electronic circuit and an electronic device, which are used to output a dynamic common-mode level according to a first output voltage and a second output voltage output by an integrator in a class D amplifier and an input reference common-mode level. The circuit comprises:

[0005] A buffer module, wherein the buffer module is used for:

[0006] Level-shifting the first output voltage and the second output voltage respectively to output a first output buffer voltage and a second output buffer voltage;

[0007] Level-shifting the first reference voltage and the second reference voltage respectively to output a first reference buffer voltage and a second reference buffer voltage;

[0008] A transconductance operational amplifier module, the transconductance operational amplifier module is used to perform transconductance amplification on the first output buffer voltage and the second output buffer voltage and then add them, and the resulting variable is recorded as a first current; the transconductance operational amplifier module is also used to perform transconductance amplification on the first reference buffer voltage and the second reference buffer voltage and then add them, and the resulting variable is recorded as a second current, and the transconductance operational amplifier module is also used to compare the first current with the second current, and if the first current is greater than the second current, the transconductance operational amplifier module outputs a step-down current;

[0009] A first resistor, wherein a first end of the first resistor is connected to an input reference common-mode level, a second end of the first resistor is connected to an output end of the transconductance operational amplifier module and serves as an output end of the common-mode level generating circuit with a buffer module, the step-down current flows through the first resistor, and the common-mode level is output from the second end of the first resistor.

[0010] Optionally, the buffer module includes a first buffer unit, a second buffer unit, a third buffer unit and a fourth buffer unit;

[0011] The first buffer unit is used to level-shift the first output voltage and output the first output buffer voltage;

[0012] The second buffer unit is used for level shifting the second output voltage and outputting the second output buffer voltage;

[0013] The third buffer unit is used for level shifting the first reference voltage and outputting the first reference buffer voltage;

[0014] The fourth buffer unit is used for level-shifting the second reference voltage and outputting the second reference buffer voltage.

[0015] Optionally, the first buffer unit includes a first MOS transistor and a first current source, the gate terminal of the first MOS transistor is connected to the first output voltage, the drain terminal of the first MOS transistor is connected to the power supply voltage of the integrator, the source terminal of the first MOS transistor is connected to the positive terminal of the first current source and the output terminal of the first output buffer voltage, and the negative terminal of the first current source is grounded;

[0016] The second buffer unit includes a second MOS transistor and a second current source, the gate terminal of the second MOS transistor is connected to the second output voltage, the drain terminal of the second MOS transistor is connected to the power supply voltage of the integrator, the source terminal of the second MOS transistor is connected to the positive terminal of the second current source and the output terminal of the second output buffer voltage, and the negative terminal of the second current source is grounded;

[0017] The third buffer unit includes a third MOS tube and a third current source, the gate end of the third MOS tube is connected to the first reference voltage, the drain end of the third MOS tube is connected to the power supply voltage of the integrator, the source end of the third MOS tube is connected to the positive end of the third current source and the output end of the first reference buffer voltage, and the negative end of the third current source is grounded;

[0018] The fourth buffer unit includes a fourth MOS tube and a fourth current source, the gate end of the fourth MOS tube is connected to the second reference voltage, the drain end of the fourth MOS tube is connected to the power supply voltage of the integrator, the source end of the fourth MOS tube is connected to the positive end of the fourth current source and the output end of the second reference buffer voltage, and the negative end of the fourth current source is grounded;

[0019] Optionally, the transconductance operational amplifier module includes:

[0020] a voltage-to-current conversion unit, the voltage-to-current conversion unit being used to convert the sum of the first output buffer voltage and the second output buffer voltage into a first current and output the first current, and also being used to convert the first reference buffer voltage and the second reference buffer voltage into a second current and output the second current;

[0021] a first current mirror unit, wherein the first current mirror unit is used to compare the first current with the second current, and if the first current is smaller than the second current, the first current mirror unit outputs a third current;

[0022] A second current mirror unit is used for converting the third current into the buck current output.

[0023] Optionally, the value of the third current is equal to the difference between the first current and the second current, and the value of the third current is equal to the value of the buck current.

[0024] Optionally, the voltage-current conversion unit includes a fifth current source, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a second resistor and a third resistor;

[0025] The positive end of the fifth current source is connected to the power supply voltage of the integrator, and the negative end of the fifth current source is respectively connected to the first end of the second resistor and the first end of the third resistor; the second end of the second resistor is respectively connected to the source end of the fifth MOS tube and the source end of the sixth MOS tube, and the second end of the third resistor is respectively connected to the source end of the ninth MOS tube and the source end of the tenth MOS tube, the gate end of the fifth MOS tube and the gate end of the eighth MOS tube are both connected to the buffer voltage of the first output voltage, the gate end of the sixth MOS tube and the gate end of the seventh MOS tube are both connected to the buffer voltage of the second output voltage, and the gate end of the ninth MOS tube and the gate end of the twelfth MOS tube are both connected to the buffer voltage of the second output voltage. A buffer voltage of the first reference voltage is connected, the gate end of the tenth MOS tube and the gate end of the eleventh MOS tube are both connected to the buffer voltage of the second reference voltage, the drain end of the fifth MOS tube is connected to the source end of the seventh MOS tube, the drain end of the sixth MOS tube is connected to the source end of the eighth MOS tube, the drain end of the ninth MOS tube is connected to the source end of the eleventh MOS tube, the drain end of the tenth MOS tube is connected to the source end of the twelfth MOS tube, the source end of the seventh MOS tube and the source end of the eighth MOS tube jointly output the first current, and the source end of the eleventh MOS tube and the source end of the twelfth MOS tube jointly output the second current.

[0026] Optionally, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube are all complementary MOS tubes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube;

[0027] If the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube all include PMOS tubes, then the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube all include NMOS tubes;

[0028] If the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube all include NMOS tubes, the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube all include PMOS tubes.

[0029] Optionally, the first current mirror unit includes a thirteenth MOS tube and a fourteenth MOS tube, the gate end of the thirteenth MOS tube is connected to the drain end and connected to the output end of the first current, the gate end of the thirteenth MOS tube is also connected to the gate end of the fourteenth MOS tube; the drain end of the fourteenth MOS tube is connected to the second current, and the source end of the thirteenth MOS tube and the source end of the fourteenth MOS tube are both grounded;

[0030] The second current mirror unit includes a fifteenth MOS tube and a sixteenth MOS tube, the gate end and the drain end of the fifteenth MOS tube are connected and connected to the gate end of the sixteenth MOS tube, the drain end of the fifteenth MOS tube is connected to the output end of the second current, the source end of the fifteenth MOS tube and the source end of the sixteenth MOS tube are both grounded, and the drain end of the sixteenth MOS tube outputs the step-down current.

[0031] When the first current is greater than the second current, the step-down current flows through the fifteenth MOS tube and the sixteenth MOS tube; when the first current is less than or equal to the second current, the fifteenth MOS tube and the sixteenth MOS tube are both turned off.

[0032] According to a second aspect of the present invention, there is provided an electronic circuit, characterized in that it comprises the common-mode level generating circuit with the buffer module.

[0033] According to a third aspect of the present invention, there is provided an electronic device, characterized in that it comprises the electronic circuit.

[0034] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0035] A common-mode level generating circuit with a buffer module provided by an embodiment of the present invention comprises a buffer module, a transconductance operational amplifier module and a first resistor, wherein the buffer module is used to level-shift the first output voltage and the second output voltage and the first reference voltage and the second reference voltage to ensure that the input stage of the transconductance operational amplifier module will not be saturated or cut off. The transconductance operational amplifier module is used to compare a first current and a second current; the first current is used to characterize the summed variable obtained after the first output voltage and the second output voltage output by the integrator are respectively amplified by the transconductance operational amplifier module, and the second current is used to characterize the summed variable obtained after the first reference voltage and the second reference voltage are respectively amplified by the transconductance operational amplifier module. If the first current is greater than the second current, the transconductance operational amplifier module outputs a step-down current. The step-down current generates a voltage drop through the first resistor, so that the output common-mode level is lower than the input reference common-mode level, thereby affecting the output voltage of the integrator. Therefore, the unilateral modulation technology of the present invention not only reduces the power consumption of the power supply when the class D power amplifier is unloaded, but also improves the output efficiency when the class D power amplifier is low-power, and avoids affecting the THDN performance of the circuit due to the oversaturation of the first output voltage and the second output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a circuit block diagram of a common-mode level generating circuit with a buffer module provided in an embodiment of the present invention;

[0037] Figure 2 FIG1 is a circuit structure diagram of a common-mode level generating circuit with a buffer module provided in an embodiment of the present invention;

[0038] Figure 3 Schematic diagram of the circuit structure of a common-mode level generating circuit with a buffer module provided in an embodiment of the present invention Figure 2 ;

[0039] Figure 4 Schematic diagram of the circuit structure of a common-mode level generating circuit with a buffer module provided in an embodiment of the present invention Figure 3 ;

[0040] Figure 5 Schematic diagram of the circuit structure of a common-mode level generating circuit with a buffer module provided in an embodiment of the present invention Figure 4 .

[0041] Reference numerals:

[0042] OUTN- first output voltage;

[0043] OUTP-second output voltage;

[0044] REFN-first reference voltage;

[0045] REFP-second reference voltage;

[0046] VREF-input reference common mode level;

[0047] VCOM-common mode level;

[0048] OUTN_BUF - first output buffer voltage;

[0049] OUTP_BUF - second output buffer voltage;

[0050] REFN_BUF - first reference buffer voltage;

[0051] REFP_BUF - second reference buffer voltage;

[0052] AVDD - supply voltage of the integrator;

[0053] Q1-first MOS tube;

[0054] Q2-second MOS tube;

[0055] Q3-the third MOS tube;

[0056] Q4-the fourth MOS tube;

[0057] Q5-fifth MOS tube;

[0058] Q6-sixth MOS tube;

[0059] Q7-seventh MOS tube;

[0060] Q8-eighth MOS tube;

[0061] Q9-9th MOS tube;

[0062] Q10-the tenth MOS tube;

[0063] Q11-eleventh MOS tube;

[0064] Q12-12th MOS tube;

[0065] Q13-thirteenth MOS tube;

[0066] Q14-fourteenth MOS tube;

[0067] Q15-the fifteenth MOS tube;

[0068] Q16-sixteenth MOS tube;

[0069] D1-first current source;

[0070] D2-second current source;

[0071] D3-third current source;

[0072] D4-fourth current source;

[0073] D5-fifth current source;

[0074] I1-first current;

[0075] I2-second current;

[0076] I3-third current;

[0077] I4- step-down current;

[0078] R1-first resistor;

[0079] R2-second resistor;

[0080] R3 - the third resistor. DETAILED DESCRIPTION

[0081] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the embodiments in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention. The terms "first", "second", "third", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0082] As described in the background technology, in order to achieve lower power consumption in the idle state, the common-mode level of the integrator is generally preset to a fixed value, and a common-mode level higher than 1 / 2 of the power supply voltage is selected to achieve unilateral modulation. However, when the power increases, the output is prone to unilateral clipping, which causes the THD+N index to decrease, and it is impossible to take into account both the idle power consumption and the THDN performance at high power.

[0083] In view of this, the present invention creatively proposes a new common-mode level generating circuit with a buffer module.

[0084] in, Figure 1The circuit block diagram of a common-mode level generating circuit with a buffer module provided in an embodiment of the present invention.

[0085] Please refer to Figure 1 An embodiment of the present invention provides a common-mode level generating circuit with a buffer module, which is used to output a dynamic common-mode level according to a first output voltage and a second output voltage output by an integrator in a class D amplifier and an input reference common-mode level. The circuit includes:

[0086] A buffer module 2, wherein the buffer module 2 is used for:

[0087] Level-shifting the first output voltage OUTN and the second output voltage OUTP respectively to output a first output buffer voltage OUTN_BUF and a second output buffer voltage OUTP_BUF;

[0088] Level-shifting the first reference voltage REFN and the second reference voltage REFP respectively to output a first reference buffer voltage REFN_BUF and a second reference buffer voltage REFP_BUF;

[0089] A transconductance operational amplifier module 1, the transconductance operational amplifier module 1 is used to perform transconductance amplification on the first output buffer voltage OUTN_BUF and the second output buffer voltage OUTP_BUF and then add them, and the resulting variable is recorded as a first current; the transconductance operational amplifier module is also used to perform transconductance amplification on the first reference buffer voltage REFN_BUF and the second reference buffer voltage REFP_BUF and then add them, and the resulting variable is recorded as a second current, and the transconductance operational amplifier module 1 is also used to compare the first current with the second current, if the first current is greater than the second current, the transconductance operational amplifier module outputs a step-down current;

[0090] A first resistor R1, wherein a first end of the first resistor R1 is connected to an input reference common-mode level VREF, a second end of the first resistor R1 is also connected to an output end of the transconductance operational amplifier module 1, a second end of the first resistor R1 is connected to the output end of the transconductance operational amplifier module 1 and serves as an output end of the common-mode level generating circuit with a buffer module, and the first resistor R1 is used to receive a step-down current of the transconductance operational amplifier module 1 and output the common-mode level.

[0091] As the output end of the common mode level generating circuit with buffer module, the common mode level VCOM is output.

[0092] Through the above technical means, the embodiment of the present invention can provide a common-mode level generating circuit with a buffer module, which can not only achieve a small duty cycle in the idle state, but also avoid the THDN increase problem when the output signal power increases. The specific principle is as follows:

[0093] In the common-mode level generating circuit with a buffer module in the embodiment of the present invention, a transconductance operational amplifier module 1 and a first resistor R1 are provided. The transconductance operational amplifier module 1 is used to perform transconductance amplification on the first output buffer voltage OUTN_BUF and the second output buffer voltage OUTP_BUF and then add them, and the obtained variable is recorded as the first current; the transconductance operational amplifier module is also used to perform transconductance amplification on the first reference buffer voltage REFN_BUF and the second reference buffer voltage REFP_BUF and then add them, and the obtained variable is recorded as the second current. The transconductance operational amplifier module 1 is also used to compare the first current and the second current. Before the output of the integrator is saturated, if the first current is less than the second current, the transconductance operational amplifier module 1 will not output current, so the common-mode level of the integrator is still the input reference common-mode level VREF of the integrator, so as to reduce the duty cycle of the output of the class D amplifier, thereby greatly reducing the power consumption of the power supply when the class D amplifier is unloaded, and greatly improving the output efficiency when the class D amplifier is low power. When the output of the integrator is saturated, the first current is greater than the second current, and the transconductance operational amplifier module 1 outputs a step-down current. The step-down current generates a voltage drop through the first resistor R1, so that the common-mode level generating circuit outputs a new common-mode level VCOM that is less than the input reference common-mode level VREF, thereby reducing the input reference common-mode level VREF of the integrator, thereby avoiding the increase of THDN of the class D amplifier, and the embodiment of the present invention does not need to adjust the common-mode level of the triangle wave.

[0094] At the same time, since the integrator generally adopts a differential common mode structure, the range of the first output voltage OUTN and the second output voltage OUTP output by the integrator fluctuates between 0V and the power supply voltage. Therefore, whether the transconductance operational amplifier 1 adopts an NMOS input pair or a sampling PMOS input pair, the first output voltage OUTN and the second output voltage OUTP will exceed the working range of the input pair of the transconductance operational amplifier 1, resulting in the transconductance operational amplifier 1 not being able to work normally within the full swing range. Therefore, the buffer module 2 performs level shifting on the first output voltage OUTN and the second output voltage OUTP and the first reference voltage REFN and the second reference voltage REFP to ensure that the transconductance operational amplifier module 1 can work normally within the full swing range.

[0095] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0096] As a specific implementation, the buffer module includes a first buffer unit 21, a second buffer unit 22, a third buffer unit 23 and a fourth buffer unit 24;

[0097] The first buffer unit 21 is used for level shifting the first output voltage OUTN and outputting the first output buffer voltage OUTN_BUF;

[0098] The second buffer unit 22 is used for level shifting the second output voltage OUTP and outputting the second output buffer voltage OUTP_BUF;

[0099] The third buffer unit 23 is used for level shifting the first reference voltage REFN and outputting the first reference buffer voltage REFN_BUF;

[0100] The fourth buffer unit 24 is configured to level-shift the second reference voltage REFP and output the second reference buffer voltage REFP_BUF.

[0101] in, Figure 2 FIG1 is a circuit structure diagram of a common-mode level generating circuit with a buffer module provided in an embodiment of the present invention.

[0102] Please refer to Figure 2 The first buffer unit 21 includes a first MOS transistor Q1 and a first current source D1, the gate terminal of the first MOS transistor Q1 is connected to the first output voltage, the drain terminal of the first MOS transistor Q1 is connected to the power supply voltage AVDD of the integrator, the source terminal of the first MOS transistor Q1 is connected to the positive terminal of the first current source D1 and the output terminal of the first output buffer voltage OUTN_BUF, and the negative terminal of the first current source D1 is grounded;

[0103] The second buffer unit 22 includes a second MOS transistor Q2 and a second current source D2, the gate terminal of the second MOS transistor Q2 is connected to the second output voltage, the drain terminal of the second MOS transistor Q2 is connected to the power supply voltage AVDD of the integrator, the source terminal of the second MOS transistor Q2 is connected to the positive terminal of the second current source D2 and the output terminal of the second output buffer voltage OUTP_BUF, and the negative terminal of the second current source D2 is grounded;

[0104] The third buffer unit 23 includes a third MOS transistor Q3 and a third current source D3, the gate end of the third MOS transistor Q3 is connected to the first reference buffer voltage REFN_BUF, the drain end of the third MOS transistor Q3 is connected to the power supply voltage AVDD of the integrator, the source end of the third MOS transistor Q3 is connected to the positive end of the third current source D3 and the output end of the first reference buffer voltage REFN_BUF, and the negative end of the third current source D3 is grounded;

[0105] The fourth buffer unit 24 includes a fourth MOS transistor Q4 and a fourth current source D4, the gate end of the fourth MOS transistor Q4 is connected to the second reference buffer voltage REFP_BUF, the drain end of the fourth MOS transistor Q4 is connected to the power supply voltage AVDD of the integrator, the source end of the fourth MOS transistor Q4 is connected to the positive end of the fourth current source D4 and the output end of the second reference buffer voltage REFP_BUF, and the negative end of the fourth current source D4 is grounded.

[0106] Figure 3 Schematic diagram of the circuit structure of a common-mode level generating circuit with a buffer module provided in an embodiment of the present invention Figure 2 .

[0107] Please refer to Figure 3 As a specific implementation, the transconductance operational amplifier module 1 includes:

[0108] a voltage-current conversion unit 11, the voltage-current conversion unit 11 is used to perform transconductance amplification on the first output buffer voltage OUTN_BUF and the second output buffer voltage OUTP_BUF, add them together, and output the first current I1, and is also used to perform transconductance amplification on the first reference buffer voltage REFN_BUF and the second reference buffer voltage REFP_BUF, add them together, and output the second current I2;

[0109] a first current mirror unit 12, wherein the first current mirror unit 12 is used to compare the first current I1 with the second current I2, and if the first current I1 is smaller than the second current I2, the first current mirror unit 12 outputs a third current I3;

[0110] The second current mirror unit 13 is used for converting the third current I3 into the step-down current I4 for output.

[0111] The value of the third current I3 is equal to the difference between the first current I1 and the second current I2 , and the value of the third current I3 is equal to the value of the step-down current I4 .

[0112] Figure 4 Schematic diagram of the circuit structure of a common-mode level generating circuit with a buffer module provided in an embodiment of the present invention Figure 3 .

[0113] Please refer to Figure 4As a specific implementation, the voltage-current conversion unit 11 includes a fifth current source D5, a fifth MOS tube Q5, a sixth MOS tube Q6, a seventh MOS tube Q7, an eighth MOS tube Q8, a ninth MOS tube Q9, a tenth MOS tube Q10, an eleventh MOS tube Q11, a twelfth MOS tube Q12, a second resistor R2 and a third resistor R3;

[0114] The positive end of the fifth current source D5 is connected to the power supply voltage AVDD of the integrator, and the negative end of the fifth current source D5 is respectively connected to the first end of the second resistor R2 and the first end of the third resistor R3; the second end of the second resistor R2 is respectively connected to the source end of the fifth MOS tube Q5 and the source end of the sixth MOS tube Q6, and the second end of the third resistor R3 is respectively connected to the source end of the ninth MOS tube Q9 and the source end of the tenth MOS tube Q10, the gate end of the fifth MOS tube Q5 and the gate end of the eighth MOS tube Q8 are both connected to the first output buffer voltage OUTN_BUF, the gate end of the sixth MOS tube Q6 and the gate end of the seventh MOS tube Q7 are both connected to the second output buffer voltage OUTP_BUF, the gate end of the ninth MOS tube Q9 and the gate end of the twelfth MOS tube Q12 are both connected to the first output buffer voltage OUTN_BUF, and the gate end of the ninth MOS tube Q9 and the gate end of the twelfth MOS tube Q12 are both connected to the first output buffer voltage OUTP_BUF. The first reference buffer voltage REFN_BUF is connected, the gate end of the tenth MOS tube Q10 and the gate end of the eleventh MOS tube Q11 are both connected to the second reference buffer voltage REFP_BUF, the drain end of the fifth MOS tube Q5 is connected to the source end of the seventh MOS tube Q7, the drain end of the sixth MOS tube Q6 is connected to the source end of the eighth MOS tube Q8, the drain end of the ninth MOS tube Q9 is connected to the source end of the eleventh MOS tube Q11, the drain end of the tenth MOS tube Q10 is connected to the source end of the twelfth MOS tube Q12, the source end of the seventh MOS tube Q7 and the source end of the eighth MOS tube Q8 jointly output the first current I1, and the source end of the eleventh MOS tube Q11 and the source end of the twelfth MOS tube Q12 jointly output the second current I2.

[0115] The type of MOS tube in the voltage-current conversion unit and the type of MOS tube in the buffer module are complementary, thereby ensuring that the transconductance operational amplifier can work normally within the full swing range.

[0116] Specifically, if the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube all include PMOS tubes, the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube all include NMOS tubes, so as to shift the first output voltage and the second output voltage as well as the first reference voltage and the second reference voltage downward.

[0117] If the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube all include NMOS tubes, the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube all include PMOS tubes, so as to shift the first output voltage and the second output voltage as well as the first reference voltage and the second reference voltage upward.

[0118] Figure 5 Schematic diagram of the circuit structure of a common-mode level generating circuit with a buffer module provided in an embodiment of the present invention Figure 4 .

[0119] Please refer to Figure 5 As a specific implementation, the first current mirror unit 12 includes a thirteenth MOS transistor Q13 and a fourteenth MOS transistor Q14, the gate end of the thirteenth MOS transistor Q13 and the gate end of the fourteenth MOS transistor Q14, the drain end of the thirteenth MOS transistor Q13 are respectively connected to the output end of the first current I1 and the gate end of the thirteenth MOS transistor Q13, the drain end of the fourteenth MOS transistor Q14 is connected to the second current I2, and the source end of the thirteenth MOS transistor Q13 and the source end of the fourteenth MOS transistor Q14 are both grounded;

[0120] The second current mirror unit 13 includes a fifteenth MOS transistor Q15 and a sixteenth MOS transistor Q16, a gate end of the fifteenth MOS transistor Q15 and a gate end of the sixteenth MOS transistor Q16, a drain end of the fifteenth MOS transistor Q15 are respectively connected to the gate end of the fifteenth MOS transistor Q15 and the drain end of the fourteenth MOS transistor Q14, a source end of the fifteenth MOS transistor Q15 and a source end of the sixteenth MOS transistor Q16 are both grounded, and a drain end of the sixteenth MOS transistor Q16 outputs the step-down current I4.

[0121] The thirteenth MOS transistor Q13, the fourteenth MOS transistor Q14, the fifteenth MOS transistor Q15 and the sixteenth MOS transistor Q16 include N-channel MOS transistors.

[0122] Please refer to Figure 5 The working principle of the common-mode level generating circuit with buffer module is as follows:

[0123] Before the output of the integrator is saturated, the value of the first current is less than the second current, so that the first current I1 output by the voltage-current conversion module is greater than the second current I2. Since the thirteenth MOS transistor Q13 and the fourteenth MOS transistor Q14 constitute the first current mirror unit 12, the current flowing through the thirteenth MOS transistor Q13 will be mirrored to the fourteenth MOS transistor Q14, but because the first current is greater than the second current, no current large enough can flow into the fourteenth MOS transistor Q14, so the current flowing through the thirteenth MOS transistor Q13 cannot be mirrored to the fourteenth MOS transistor Q14, then the current flowing into the fourteenth MOS transistor Q14 is the second current I2, and no current will flow into the fifteenth MOS transistor Q15, so that the transconductance operational amplifier module 1 has no step-down current I4 output, at this time the common mode level of the integrator is equal to the input reference common mode level VREF, the input reference common mode level VREF is a fixed value between AVDD / 2 and AVDD, wherein the second current value is used to characterize the output voltage value of the integrator when it is critically saturated.

[0124] After the output of the integrator is saturated, the first current is greater than the second current, so that the first current I1 output by the voltage-current conversion module is less than the second current I2. Since the thirteenth MOS transistor Q13 and the fourteenth MOS transistor Q14 constitute a first current mirror unit 12, the current flowing through the thirteenth MOS transistor Q13 will be mirrored to the fourteenth MOS transistor Q14, and the current flowing into the fourteenth MOS transistor Q14 is equal to the value of the first current I1, and the remaining current flows into the fifteenth MOS transistor Q15, that is, the third current I3. Since the sixteenth MOS transistor Q16 and the fifteenth MOS transistor Q15 constitute a second current mirror unit 13, the third current I3 flowing through the fifteenth MOS transistor Q15 will be mirrored to the sixteenth MOS transistor Q16 and output through the drain end of the sixteenth MOS transistor Q16, that is, the step-down current I4. The step-down current I4 generates a voltage drop when passing through the first resistor R1. The voltage drop generated by the first resistor R1 is proportional to the difference between the first current and the second current, so that a new common-mode level VCOM smaller than the input reference common-mode level VREF is output, and the output common-mode level VCOM will not be lower than AVDD / 2.

[0125] In summary, the common-mode level generating circuit with a buffer module in the embodiment of the present invention is provided with three parts, namely, a buffer module, a transconductance operational amplifier module and a first resistor. The transconductance operational amplifier module is used to perform transconductance amplification on the first output voltage and the second output voltage output by the integrator in the class D amplifier and then add them, and the obtained variable is recorded as the first current; the transconductance operational amplifier module is also used to perform transconductance amplification on the first reference voltage and the second reference voltage and then add them, and the obtained variable is recorded as the second current. The transconductance operational amplifier module is also used to compare the first current and the second current. Before the output of the integrator is saturated, if the first current is less than the second current, the transconductance operational amplifier module will not output current, so the common-mode level of the integrator is still the input reference common-mode level of the integrator, so as to reduce the duty cycle of the output of the class D amplifier, thereby greatly reducing the power consumption of the power supply when the class D amplifier is unloaded, and greatly improving the output efficiency when the class D amplifier is low power. When the output of the integrator is saturated, the first current is greater than the second current, and the transconductance operational amplifier module outputs a step-down current. The step-down current generates a voltage drop through the first resistor, so that the common-mode level generating circuit outputs a new common-mode level that is less than the input reference common-mode level, thereby reducing the input reference common-mode level of the integrator, thereby avoiding an increase in the THDN of the class D amplifier, and the embodiment of the present invention does not need to adjust the common-mode level of the triangle wave.

[0126] At the same time, the first output voltage and the second output voltage as well as the first reference voltage and the second reference voltage are level-shifted by the buffer module to ensure that the transconductance operational amplifier module can work normally within the full swing range.

[0127] An embodiment of the present invention further provides an electronic circuit, which includes the common-mode level generating circuit with the buffer module and other parts of the electronic circuit.

[0128] An embodiment of the present invention further provides an electronic device, which includes the electronic circuit and other parts of the electronic device.

[0129] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A common-mode level generating circuit with a buffer module, characterized in that: The circuit is used to output a dynamic common mode level according to a first output voltage and a second output voltage output by an integrator in a class D amplifier and an input reference common mode level, and the circuit comprises: A buffer module, wherein the buffer module is used for: Level-shifting the first output voltage and the second output voltage respectively to output a first output buffer voltage and a second output buffer voltage; Level-shifting the first reference voltage and the second reference voltage respectively to output a first reference buffer voltage and a second reference buffer voltage; A transconductance operational amplifier module, the transconductance operational amplifier module is used to perform transconductance amplification on the first output buffer voltage and the second output buffer voltage and then add them, and the resulting variable is recorded as a first current; the transconductance operational amplifier module is also used to perform transconductance amplification on the first reference buffer voltage and the second reference buffer voltage and then add them, and the resulting variable is recorded as a second current, and the transconductance operational amplifier module is also used to compare the first current with the second current, and if the first current is greater than the second current, the transconductance operational amplifier module outputs a step-down current; A first resistor, wherein a first end of the first resistor is connected to an input reference common-mode level, a second end of the first resistor is connected to an output end of the transconductance operational amplifier module and serves as an output end of the common-mode level generating circuit with a buffer module, the step-down current flows through the first resistor, and the common-mode level is output from the second end of the first resistor.

2. The common-mode level generating circuit with a buffer module according to claim 1, characterized in that: The buffer module includes a first buffer unit, a second buffer unit, a third buffer unit and a fourth buffer unit; The first buffer unit is used to level-shift the first output voltage and output the first output buffer voltage; The second buffer unit is used for level shifting the second output voltage and outputting the second output buffer voltage; The third buffer unit is used for level shifting the first reference voltage and outputting the first reference buffer voltage; The fourth buffer unit is used for level-shifting the second reference voltage and outputting the second reference buffer voltage.

3. The common-mode level generating circuit with a buffer module according to claim 2, wherein the common-mode level generating circuit with a buffer module is characterized in that: The first buffer unit includes a first MOS transistor and a first current source, the gate end of the first MOS transistor is connected to the first output voltage, the drain end of the first MOS transistor is connected to the power supply voltage of the integrator, the source end of the first MOS transistor is connected to the positive end of the first current source and the output end of the first output buffer voltage, and the negative end of the first current source is grounded; The second buffer unit includes a second MOS transistor and a second current source, the gate terminal of the second MOS transistor is connected to the second output voltage, the drain terminal of the second MOS transistor is connected to the power supply voltage of the integrator, the source terminal of the second MOS transistor is connected to the positive terminal of the second current source and the output terminal of the second output buffer voltage, and the negative terminal of the second current source is grounded; The third buffer unit includes a third MOS tube and a third current source, the gate end of the third MOS tube is connected to the first reference voltage, the drain end of the third MOS tube is connected to the power supply voltage of the integrator, the source end of the third MOS tube is connected to the positive end of the third current source and the output end of the first reference buffer voltage, and the negative end of the third current source is grounded; The fourth buffer unit includes a fourth MOS tube and a fourth current source, the gate end of the fourth MOS tube is connected to the second reference voltage, the drain end of the fourth MOS tube is connected to the power supply voltage of the integrator, the source end of the fourth MOS tube is connected to the positive end of the fourth current source and the output end of the second reference buffer voltage, and the negative end of the fourth current source is grounded.

4. The common mode level generating circuit with a buffer module according to claim 1, characterized in that: The transconductance operational amplifier module comprises: a voltage-to-current conversion unit, the voltage-to-current conversion unit being used to convert the sum of the first output buffer voltage and the second output buffer voltage into a first current and output the first current, and also being used to convert the first reference buffer voltage and the second reference buffer voltage into a second current and output the second current; a first current mirror unit, wherein the first current mirror unit is used to compare the first current with the second current, and if the first current is smaller than the second current, the first current mirror unit outputs a third current; A second current mirror unit is used for converting the third current into the buck current output.

5. The common-mode level generating circuit with a buffer module according to claim 4, characterized in that: The value of the third current is equal to the difference between the first current and the second current, and the value of the third current is equal to the value of the step-down current.

6. The common-mode level generating circuit with a buffer module according to claim 5, characterized in that: The voltage-current conversion unit includes a fifth current source, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a second resistor and a third resistor; The positive end of the fifth current source is connected to the power supply voltage of the integrator, and the negative end of the fifth current source is respectively connected to the first end of the second resistor and the first end of the third resistor; the second end of the second resistor is respectively connected to the source end of the fifth MOS tube and the source end of the sixth MOS tube, and the second end of the third resistor is respectively connected to the source end of the ninth MOS tube and the source end of the tenth MOS tube, the gate end of the fifth MOS tube and the gate end of the eighth MOS tube are both connected to the buffer voltage of the first output voltage, the gate end of the sixth MOS tube and the gate end of the seventh MOS tube are both connected to the buffer voltage of the second output voltage, and the gate end of the ninth MOS tube and the gate end of the twelfth MOS tube are both connected to the buffer voltage of the second output voltage. A buffer voltage of the first reference voltage is connected, the gate end of the tenth MOS tube and the gate end of the eleventh MOS tube are both connected to the buffer voltage of the second reference voltage, the drain end of the fifth MOS tube is connected to the source end of the seventh MOS tube, the drain end of the sixth MOS tube is connected to the source end of the eighth MOS tube, the drain end of the ninth MOS tube is connected to the source end of the eleventh MOS tube, the drain end of the tenth MOS tube is connected to the source end of the twelfth MOS tube, the drain end of the seventh MOS tube and the drain end of the eighth MOS tube jointly output the first current, and the drain end of the eleventh MOS tube and the drain end of the twelfth MOS tube jointly output the second current.

7. The common-mode level generating circuit with a buffer module according to claim 6, wherein the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube are all complementary MOS tubes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube; If the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube all include PMOS tubes, then the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube all include NMOS tubes; If the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube all include NMOS tubes, the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube all include PMOS tubes.

8. The common mode level generating circuit with a buffer module according to claim 4, characterized in that: The first current mirror unit includes a thirteenth MOS tube and a fourteenth MOS tube, the gate end and the drain end of the thirteenth MOS tube are connected, and connected to the output end of the first current, and the gate end of the thirteenth MOS tube is also connected to the gate end of the fourteenth MOS tube; the drain end of the fourteenth MOS tube is connected to the second current, and the source end of the thirteenth MOS tube and the source end of the fourteenth MOS tube are both grounded; The second current mirror unit includes a fifteenth MOS tube and a sixteenth MOS tube, the gate end and the drain end of the fifteenth MOS tube are connected and connected to the gate end of the sixteenth MOS tube, the drain end of the fifteenth MOS tube is connected to the output end of the second current, the source end of the fifteenth MOS tube and the source end of the sixteenth MOS tube are both grounded, and the drain end of the sixteenth MOS tube outputs the step-down current. When the first current is greater than the second current, the step-down current flows through the fifteenth MOS tube and the sixteenth MOS tube; when the first current is less than or equal to the second current, the fifteenth MOS tube and the sixteenth MOS tube are both turned off.

9. An electronic circuit, characterized in that: A common-mode level generating circuit with a buffer module comprising any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the electronic circuit of claim 9.

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