Terminal impedance matching adjusting system

Abstract

The invention discloses a terminal impedance matching adjusting system, which is characterized in that an impedance matching network inputs an impedance matching target value and an impedance matching control signal, and adjusts the size of a parallel resistor in the impedance matching network according to the impedance matching control signal to match the target value so as to realize an impedance adjusting function; the high-speed comparator compares the impedance matching state level with the reference level generated by the voltage division module, and outputs a comparison result to the impedance matching control signal generation module; the impedance matching control signal generation module generates a comparator control signal to the high-speed comparator, generates an impedance matching control signal to the impedance matching network and the port driving circuit, and generates a latch signal to be output to the port driving circuit; and the port driving circuit adjusts self impedance according to the impedance matching control signal and the latch signal to realize an expected impedance matching effect. According to the invention, two impedance matching adjusting modes of manual operation and automatic operation can be realized, the flexibility and applicability are high, and the method can be widely applied to various transmission line terminal devices.

Description

Technical Field

[0001] The invention relates to the technical field of electrical circuits, and in particular to a terminal impedance matching adjustment system. Background Art

[0002] As signal rates continue to increase, high-frequency signal transmission has higher and higher requirements for signal integrity. In the high-frequency field, signal reflection is the main factor affecting signal integrity in a single signal network. When the signal wavelength is at the same order of magnitude as the transmission line length, the reflected signal is easily mixed with the original signal, affecting the signal quality. When the signal encounters reflections caused by connection nodes, load changes, or connection terminals on the transmission line, part of the energy will be reflected in the opposite direction of propagation. Signal reflection may cause overshoot, ringing, jitter, and other phenomena in the original signal.

[0003] Assume that a high-frequency signal propagates from left to right along a transmission line to a certain node. Due to some reason, the transient impedance changes and part of the energy is reflected in the opposite direction of propagation. The amount of reflected energy is determined by the difference in characteristic impedance between the left and right end regions of the node. Let Vi be the incident voltage, Vr be the reflected voltage, Vo be the output voltage, Z1 represent the impedance of the left region of the node, and Z2 represent the impedance of the right region of the node. The reflection coefficient ρ is: According to Kirchhoff's current law: The transmission coefficient T is obtained: It can be seen from the above formula that the greater the difference between Z1 and Z2, the greater the reflection coefficient, the greater the reflected voltage, and the smaller the final output voltage. Only when Z1=Z2, the reflection coefficient is 0 and the transmission coefficient is 1, which means that no signal reflection is generated, that is, the impedance matching state. In the impedance matching state, the signal transmission power can be maximized and the energy conversion performance can be improved; the signal reflection in the circuit can be reduced, the signal quality and transmission efficiency can be improved; it can ensure the stable transmission of the signal in the system to avoid signal distortion and performance degradation.

[0004] In high-speed PCB design, digital signal routing is considered to have uniform characteristic impedance. Therefore, the node where signal reflection is most likely to occur is the connection between the transmission line and the terminal device port. Therefore, if the transmission line end device has impedance matching adjustment capability so that it can match the transmission line, the signal integrity problem caused by signal reflection can be effectively solved. Summary of the invention

[0005] The purpose of the present invention is to provide a terminal impedance matching adjustment system to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a terminal impedance matching adjustment system, including an impedance matching network, a voltage dividing module, a high-speed comparator, an impedance matching control signal generating module and a port driving circuit; The impedance matching network inputs an impedance matching target value and an impedance matching control signal, and adjusts the size of the parallel resistance in the impedance matching network according to the impedance matching control signal to match the impedance matching target value, thereby realizing an impedance adjustment function; The voltage division module generates a fixed reference level to the high-speed comparator through resistor voltage division; The high-speed comparator compares the impedance matching state level with the reference level, and outputs the comparison result to the impedance matching control signal generating module; The impedance matching control signal generating module generates a comparator control signal to the high-speed comparator according to the comparison result, generates an impedance matching control signal to the impedance matching network and the port driving circuit, and generates a latch signal to output to the port driving circuit; The port driving circuit adjusts its own impedance according to the impedance matching control signal and the latch signal generated by the impedance matching control signal generating module to achieve the expected impedance matching effect.

[0007] In one embodiment, the impedance matching network includes a PMOS impedance matching network and an NMOS impedance matching network; The PMOS impedance matching network includes PMOS tubes PM1-PM28, resistors R2, R3 and fourteen resistors R1; wherein the first end of the resistor R2 and the first end of the resistor R3 are connected to the output terminal OUT, and the second end of the resistor R2 and the second end of the resistor R3 are grounded; the source electrodes of the PMOS tubes PM1-PM28 are connected to the power supply VDD; the drain electrodes of every two adjacent PMOS tubes in the PMOS tubes PM1-PM28 are connected to the output terminal OUT through a resistor R1; the output terminal OUT is connected to the high-speed comparator; The NMOS impedance matching network includes NMOS tubes NM1~NM28, resistors R5, R6 and fourteen resistors R4; wherein the first end of the resistor R5 and the first end of the resistor R6 are commonly connected to VDD, and the second end of the resistor R5 and the second end of the resistor R6 are commonly connected to the output terminal OUT; the source electrodes of the NMOS tubes NM1~NM28 are all connected to the ground GND; the drain electrodes of every two adjacent NMOS tubes in the NMOS tubes NM1~NM28 are commonly connected to the output terminal OUT through a resistor R4; and the output terminal OUT is connected to a high-speed comparator.

[0008] In one embodiment, the high-speed comparator includes a PMOS high-speed comparator and an NMOS high-speed comparator, both of which have the same structure and are respectively composed of PMOS tubes PM29-PM32, NMOS tubes NM29-NM33, capacitors C1-C2, inverters INV1-INV2 and NAND gates NAND1-NAND2; The sources of PMOS tubes PM29 to PM32 are all connected to the power supply VDD, the gate of PMOS tube PM29 is connected to its own drain and to the drain of PMOS tube PM30; the gate of PMOS tube PM32 is connected to its own drain and to the drain of PMOS tube PM31; the gate of PMOS tube PM30 is connected to the drain of PMOS tube PM31, and the gate of PMOS tube PM31 is connected to the drain of PMOS tube PM30; the gate of NMOS tube NM31 is connected to the drain of NMOS tube NM32, and the gate of NMOS tube NM The source of NMOS tube NM31 is connected to the drain of NMOS tube NM29; the gate of NMOS tube NM32 is connected to the drain of NMOS tube NM31, and the source of NMOS tube NM32 is connected to the drain of NMOS tube NM30; the source of NMOS tube NM29 and the source of NMOS tube NM30 are connected to the drain of NMOS tube NM33; the gate of NMOS tube NM29 is connected to the input pin VM, and the gate of NMOS tube NM30 is connected to the input pin VP; the gate of NMOS tube NM33 is connected to the input pin VREF, and the drain is connected to the ground GND; The drain of the PMOS tube PM30 is connected to the first end of the capacitor C1, and the drain of the PMOS tube PM31 is connected to the first end of the capacitor C2; the second end of the capacitor C1 and the second end of the capacitor C2 are both connected to the drain of the NMOS tube NM33; the first end of the capacitor C1 is connected to the input end of the inverter INV1, and the first end of the capacitor C2 is connected to the input end of the inverter INV2; the output end of the inverter INV1 is connected to the first input end of the NAND gate NAND1, and the output end of the inverter INV2 is connected to the first input end of the NAND gate NAND2; the output end of the NAND gate NAND1 is connected to the second input end of the NAND gate NAND2, and the output end of the NAND gate NAND2 is connected to the second input end of NAND1; the output end of the NAND gate NAND1 is taken as the output of the high-speed comparator and sent to the impedance matching control signal generation module.

[0009] In one implementation, the impedance matching control signal generation module includes two modes: manual adjustment and automatic adjustment; During manual adjustment, the relevant circuits for automatic impedance matching are bypassed, and the latch signal and impedance matching control signal are manually configured in sequence; During automatic adjustment, the relevant circuit is mainly composed of a multi-bit counter that can be set and control logic. The counter is reused in the order of adjusting the PMOS impedance matching network first and then adjusting the NMOS impedance matching network; the impedance matching control signal generation module generates an impedance matching control signal to the impedance matching network and the port drive circuit according to the output result of the high-speed comparator, generates a comparator control signal to the high-speed comparator, and synchronously outputs a latch signal to the port drive circuit after the adjustment is completed.

[0010] In one implementation, the port driving circuit includes PMOS tubes PM33 to PM60, NMOS tubes NM34 to NM61, 14 resistors R7, and control modules Ctrl1 and Ctrl2; The sources of the PMOS tubes PM33 to PM60 are all connected to the power supply VDD; the sources of the NMOS tubes NM34 to NM60 are all connected to the ground GND; The drains of every two adjacent PMOS tubes in the PMOS tubes PM33 to PM60 and the drains of every two adjacent NMOS tubes in the NMOS tubes NM34 to NM60 are connected, and are connected to the output terminal DATA_OUT through a resistor R7; After the impedance matching control signal generation module completes the impedance adjustment, the impedance matching control signal and the latch signal are simultaneously input to the control modules Ctrl1 and Ctrl2. The impedance matching control signal is C PMOS [4:0] and C NMOS [4:0], latch signal is L PMOS and L NMOS ; Latch signal L PMOS Control module Ctrl1 latches impedance matching control signal C PMOS [4:0], output CP[4:0], control data input DATA_IN to the PMOS impedance matching network, the high potential in the data is driven output through the PMOS impedance matching network; latch signal L NMOS Control module Ctrl2 latches impedance matching control signal C NMOS [4:0], output CN[4:0], control data input DATA_IN to the NMOS impedance matching network, the low potential in the data is driven output through the NMOS impedance matching network, and finally the number of parallel resistors is adjusted to achieve the impedance matching effect.

[0011] The present invention provides a terminal impedance matching adjustment system, which has the following beneficial effects: (1) It can be realized by using common PMOS and NMOS tubes in CMOS process and standard cells in digital cell library, with simple structure and easy to promote; (2) The high-speed comparator can quickly obtain the comparison result, the impedance matching adjustment process is fast, and the result is reliable; (3) The data paths used for PMOS and NMOS regulation are partially reused, which can save layout area; (4) Impedance matching control has two adjustment modes: automatic and manual. Impedance matching can be achieved in different hardware environments. It has high flexibility and applicability and can be widely used in various types of transmission line terminal equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the structure of the terminal impedance matching adjustment system provided by the present invention.

[0013] Figure 2 It is a schematic diagram of the structure of the NMOS impedance matching network provided by the present invention.

[0014] Figure 3 It is a schematic diagram of the PMOS impedance matching network structure provided by the present invention.

[0015] Figure 4 It is a schematic diagram of the structure of the voltage divider module provided by the present invention.

[0016] Figure 5 The figure is a schematic diagram of the circuit structure of the high-speed comparator provided by the present invention.

[0017] Figure 6 It is a schematic diagram of the working process of the impedance matching control signal generating module provided by the present invention.

[0018] Figure 7 It is a structural schematic diagram of the port drive output circuit provided by the present invention. DETAILED DESCRIPTION

[0019] The following is a further detailed description of a terminal impedance matching adjustment system proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0020] The present invention provides a terminal impedance matching adjustment system, such as Figure 1As shown, it includes an impedance matching network, a voltage division module, a high-speed comparator, an impedance matching control signal generating module and a port driving circuit. The impedance matching network includes a PMOS impedance matching network and an NMOS impedance matching network, and the high-speed comparator includes a PMOS high-speed comparator and an NMOS high-speed comparator. The PMOS impedance matching target value and the PMOS impedance matching control signal are input to the PMOS impedance matching network, and the NMOS impedance matching target value and the NMOS impedance matching control signal are input to the NMOS impedance matching network; the PMOS impedance matching network outputs the PMOS impedance matching state level to the PMOS high-speed comparator, and the NMOS impedance matching network outputs the NMOS impedance matching state level to the NMOS high-speed comparator. The voltage division module generates a fixed reference level through resistor voltage division and outputs it to the PMOS high-speed comparator and the NMOS high-speed comparator. The PMOS high-speed comparator is used to compare the PMOS impedance matching state level with the fixed reference level generated by the voltage division module, and the NMOS high-speed comparator is used to compare the NMOS impedance matching state level with the fixed reference level generated by the voltage division module; the PMOS high-speed comparator and the NMOS high-speed comparator output the comparison results to the impedance matching control signal generating module. The impedance matching control signal generation module generates a PMOS high-speed comparator control signal and an NMOS high-speed comparator control signal according to the comparison result, and outputs them to the PMOS high-speed comparator and the NMOS high-speed comparator respectively to control their working states, and generates a PMOS impedance matching control signal to output to the PMOS impedance matching network and the port drive circuit, generates an NMOS impedance matching control signal to output to the NMOS impedance matching network and the port drive circuit, and synchronously generates a PMOS latch signal and an NMOS latch signal to output to the port drive circuit after the adjustment is completed. The port drive circuit adjusts its own impedance according to the PMOS impedance matching control signal, the NMOS impedance matching control signal, the PMOS latch signal, and the NMOS latch signal, and finally achieves the expected impedance matching effect.

[0021] Impedance matching network analysis: Input impedance matching target value and the 5-bit impedance matching control signal generated by the impedance matching control signal generation module. According to the 5-bit impedance matching control signal, the parallel resistance in the impedance matching network is adjusted to match the target value, thereby realizing the impedance adjustment function.

[0022] Figure 2 The figure is a schematic diagram of the structure of the NMOS impedance matching network. The NMOS impedance matching network consists of two parts, the upper part is an adjustable resistor network, which is configured by the user. Eight impedance selections can be achieved through the three-bit control signal Q[2:0]. The lower part is an adaptive impedance adjustment network composed of 28 NMOS tubes (NM1~NM28) and 14 resistors R4. Each resistor R4 connects two NMOS tubes, such as Figure 2There are five control signals C[4:0] generated by the impedance matching control signal generation module. The control signal C[0] controls one NMOS tube and resistor, the control signal C[1] controls two NMOS tubes and resistors, the control signal C[2] controls four NMOS tubes and resistors, the control signal C[3] controls seven NMOS tubes and resistors, and the control signal C[4] controls all NMOS tubes and resistors. Through different signal control, stepless adjustment of 0 to 14 resistors in parallel can be achieved. For example, if 8 resistors are required in parallel, the control signal should be C[4:0]=01001. Figure 3 It is a structural diagram of a PMOS impedance matching network, and its circuit structure and principle are consistent with those of an NMOS impedance matching network adjustment circuit.

[0023] Voltage divider module analysis: Figure 4 As shown, a fixed level is generated by resistor voltage division, which is used as a reference level for judging whether the impedance matching adjustment is completed, and its voltage is half of the power supply voltage VDD.

[0024] Comparator analysis: Figure 5 As shown, the structure is a high-speed comparator, including a PMOS high-speed comparator and an NMOS high-speed comparator, both of which have the same structure, and are mainly composed of a comparison stage and a latch output stage, wherein the gate of the NMOS tube NM29 and the gate of the NMOS tube NM30 are two input ports VP and VM of the comparator, the gate of the NMOS tube NM31 and the gate of the NMOS tube NM32 are cross-interconnected to each other's drain, and the source of the NMOS tube NM31 and the source of the NMOS tube NM32 are respectively connected to the drain of the input tube NM29 and the drain of NM30; the gate of the PMOS tube PM30 and the gate of PM31 are cross-interconnected to each other's drain, and the drain of the PMOS tube PM30 and the drain of the PMOS tube PM31 are respectively connected to the drain of the NMOS tube NM31 and the drain of NM32 to form positive feedback, so that the potential of the A point and the B point changes faster, thereby realizing the function of high-speed comparison. PMOS tubes PM29 and PM32 are diode-connected (drain connected to gate, source connected to power supply), which is used to shunt current so that the voltage variation range of points A and B is larger. Capacitors C1 and C2 are filter capacitors. The two NAND gates NAND1 and NAND2 are cross-interconnected to form an interlocking structure and form the output stage of the comparator together with inverters INV1 and INV2 respectively. The function of the comparator is to compare the impedance matching state level with the reference level. If the two levels are different, the comparison result is judged as a high level; if the two levels are the same, the comparison result is judged as a low level.

[0025] Analysis of the impedance matching control signal generation module: The workflow of this module is as follows Figure 6As shown in the figure: the impedance matching control signal has two modes: manual adjustment and automatic adjustment. When the impedance matching control signal is manually adjusted, the related circuits for automatic impedance matching are bypassed. The latch signals of PMOS and NMOS need to be manually configured in sequence. After configuring the PMOS latch signal, manually configure the PMOS impedance matching control signal, and the port drive circuit can latch the current PMOS impedance matching control signal. Repeat the same operation process for manual adjustment of NMOS impedance matching to complete the manual configuration of the impedance matching control signal.

[0026] The logic body of the automatic impedance matching control signal is a multi-bit counter that can be set. Specifically, assuming that the number of bits of the counter is n, the impedance adjustable gear is 2 n -1 gear. It should be noted that the impedance matching control signal cannot be all 0, otherwise the port drive circuit cannot drive the output. The counter is reused in the order of adjusting PMOS first and then adjusting NMOS, so as to save the layout area. When the automatic impedance matching adjustment starts, it is necessary to manually set the PMOS and NMOS impedance matching target values ​​as the input signal of the impedance matching network. This target value is equivalent to the transmission line characteristic impedance value that can match the port drive circuit in this system. The counter starts counting from 1, and the initial value of the impedance matching control signal is 1. Then, the level state of the comparator signal generated by the PMOS high-speed comparator in the analog circuit and sent to the impedance matching control signal generation module is judged. If it is judged to be a high level, it means that the impedance network adjustment result in the analog circuit has not been matched yet, and it needs to continue to be adjusted, so the counter is increased by one. At the same time, a comparator control signal is generated and fed back to the PMOS high-speed comparator module to enable it to continue working. The updated PMOS high-speed comparator signal value is judged again. Repeat the above operation until the comparator signal is judged to be a low level, which means that the impedance network adjustment result in the analog circuit has been matched. At this time, the comparator control signal generated is fed back to the PMOS high-speed comparator to stop it from working. In addition, a PMOS latch signal is generated and sent to the port drive circuit together with the five-bit impedance matching control signal. The port drive circuit uses the PMOS latch signal to latch the current impedance matching control signal, thereby realizing the configuration of the PMOS impedance matching network in the port drive circuit. After the PMOS impedance matching is completed, the NMOS impedance matching adjustment is started, and the counter is reset to 1. Then repeat the judgment and operation process described above to realize the configuration of the NMOS impedance network and complete the automatic configuration of the impedance matching control signal.

[0027] Port drive circuit analysis: The port drive circuit adjusts its own impedance according to the impedance matching control signal and latch signal, and finally achieves the expected impedance matching effect. The structure of the port drive circuit is as follows: Figure 7The PMOS network in the upper part is consistent with the above-mentioned PMOS impedance matching network, and the NMOS network in the lower part is consistent with the N-type impedance matching network. The principle is that after the impedance matching control signal generation module completes the impedance adjustment, the control signal and the latch signal are simultaneously input to the control modules Ctrl1 and Ctrl2 of the port matching circuit. The control signal is C PMOS [4:0] and C NMOS [4:0], latch signal is L PMOS and L NMOS .L PMOS Control Ctrl1 module latch C PMOS [4:0] control signal, output CP[4:0], control data input DATA_IN to the PMOS impedance matching network, the high potential in the data is driven output through the upper part of the PMOS impedance matching network. NMOS Control Ctrl2 module latch C NMOS [4:0] control signal, output CN[4:0], control data input DATA_IN to the NMOS impedance matching network, the low potential of the data is driven and output through the lower half of the NMOS impedance matching network. Finally, the number of parallel resistors is adjusted to achieve the impedance matching effect.

[0028] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A terminal impedance matching adjustment system, characterized in that: It includes an impedance matching network, a voltage divider module, a high-speed comparator, an impedance matching control signal generation module and a port driving circuit; The impedance matching network inputs an impedance matching target value and an impedance matching control signal, and adjusts the size of the parallel resistance in the impedance matching network according to the impedance matching control signal to match the impedance matching target value, thereby realizing an impedance adjustment function; The voltage division module generates a fixed reference level to the high-speed comparator through resistor voltage division; The high-speed comparator compares the impedance matching state level with the reference level, and outputs the comparison result to the impedance matching control signal generating module; The impedance matching control signal generating module generates a comparator control signal to the high-speed comparator according to the comparison result, generates an impedance matching control signal to the impedance matching network and the port driving circuit, and generates a latch signal to output to the port driving circuit; The port driving circuit adjusts its own impedance according to the impedance matching control signal and the latch signal generated by the impedance matching control signal generating module to achieve the expected impedance matching effect.

2. The terminal impedance matching adjustment system according to claim 1, characterized in that: The impedance matching network includes a PMOS impedance matching network and an NMOS impedance matching network; The PMOS impedance matching network includes PMOS tubes PM1-PM28, resistors R2, R3 and fourteen resistors R1; wherein the first end of the resistor R2 and the first end of the resistor R3 are connected to the output terminal OUT, and the second end of the resistor R2 and the second end of the resistor R3 are grounded; the source electrodes of the PMOS tubes PM1-PM28 are connected to the power supply VDD; the drain electrodes of every two adjacent PMOS tubes in the PMOS tubes PM1-PM28 are connected to the output terminal OUT through a resistor R1; the output terminal OUT is connected to the high-speed comparator; The NMOS impedance matching network includes NMOS tubes NM1~NM28, resistors R5, R6 and fourteen resistors R4; wherein the first end of the resistor R5 and the first end of the resistor R6 are commonly connected to VDD, and the second end of the resistor R5 and the second end of the resistor R6 are commonly connected to the output terminal OUT; the source electrodes of the NMOS tubes NM1~NM28 are all connected to the ground GND; the drain electrodes of every two adjacent NMOS tubes in the NMOS tubes NM1~NM28 are commonly connected to the output terminal OUT through a resistor R4; and the output terminal OUT is connected to a high-speed comparator.

3. The terminal impedance matching adjustment system according to claim 2, characterized in that: The high-speed comparator includes a PMOS high-speed comparator and an NMOS high-speed comparator, both of which have the same structure and are respectively composed of PMOS tubes PM29-PM32, NMOS tubes NM29-NM33, capacitors C1-C2, inverters INV1-INV2 and NAND gates NAND1-NAND2; The sources of PMOS tubes PM29 to PM32 are all connected to the power supply VDD, the gate of PMOS tube PM29 is connected to its own drain and to the drain of PMOS tube PM30; the gate of PMOS tube PM32 is connected to its own drain and to the drain of PMOS tube PM31; the gate of PMOS tube PM30 is connected to the drain of PMOS tube PM31, and the gate of PMOS tube PM31 is connected to the drain of PMOS tube PM30; the gate of NMOS tube NM31 is connected to the drain of NMOS tube NM32, and the gate of NMOS tube NM The source of NMOS tube NM31 is connected to the drain of NMOS tube NM29; the gate of NMOS tube NM32 is connected to the drain of NMOS tube NM31, and the source of NMOS tube NM32 is connected to the drain of NMOS tube NM30; the source of NMOS tube NM29 and the source of NMOS tube NM30 are connected to the drain of NMOS tube NM33; the gate of NMOS tube NM29 is connected to the input pin VM, and the gate of NMOS tube NM30 is connected to the input pin VP; the gate of NMOS tube NM33 is connected to the input pin VREF, and the drain is connected to the ground GND; The drain of the PMOS tube PM30 is connected to the first end of the capacitor C1, and the drain of the PMOS tube PM31 is connected to the first end of the capacitor C2; the second end of the capacitor C1 and the second end of the capacitor C2 are both connected to the drain of the NMOS tube NM33; the first end of the capacitor C1 is connected to the input end of the inverter INV1, and the first end of the capacitor C2 is connected to the input end of the inverter INV2; the output end of the inverter INV1 is connected to the first input end of the NAND gate NAND1, and the output end of the inverter INV2 is connected to the first input end of the NAND gate NAND2; the output end of the NAND gate NAND1 is connected to the second input end of the NAND gate NAND2, and the output end of the NAND gate NAND2 is connected to the second input end of NAND1; the output end of the NAND gate NAND1 is taken as the output of the high-speed comparator and sent to the impedance matching control signal generation module.

4. The terminal impedance matching adjustment system according to claim 3, characterized in that: The impedance matching control signal generation module includes two modes: manual adjustment and automatic adjustment; During manual adjustment, the relevant circuits for automatic impedance matching are bypassed, and the latch signal and impedance matching control signal are manually configured in sequence; During automatic adjustment, the relevant circuit is mainly composed of a multi-bit counter that can be set and control logic. The counter is reused in the order of adjusting the PMOS impedance matching network first and then adjusting the NMOS impedance matching network; the impedance matching control signal generation module generates an impedance matching control signal to the impedance matching network and the port drive circuit according to the output result of the high-speed comparator, generates a comparator control signal to the high-speed comparator, and synchronously outputs a latch signal to the port drive circuit after the adjustment is completed.

5. The terminal impedance matching adjustment system according to claim 4, characterized in that: The port driving circuit includes PMOS tubes PM33-PM60, NMOS tubes NM34-NM61, 14 resistors R7, and control modules Ctrl1 and Ctrl2; the sources of the PMOS tubes PM33-PM60 are all connected to the power supply VDD; the sources of the NMOS tubes NM34-NM60 are all connected to the ground GND; the drains of every two adjacent PMOS tubes in the PMOS tubes PM33-PM60 and the drains of every two adjacent NMOS tubes in the NMOS tubes NM34-NM60 are connected, and are connected to the output terminal DATA_OUT through a resistor R7; after the impedance matching control signal generation module completes the impedance adjustment, the impedance matching control signal and the latch signal are simultaneously input to the control modules Ctrl1 and Ctrl2, and the impedance matching control signal is C PMOS [4:0] and C NMOS [4:0], latch signal is L PMOS and L NMOS ; Latch signal L PMOS Control module Ctrl1 latches impedance matching control signal C PMOS [4:0], output CP[4:0], control data input DATA_IN to the PMOS impedance matching network, the high potential in the data is driven output through the PMOS impedance matching network; latch signal L NMOS Control module Ctrl2 latches impedance matching control signal C NMOS [4:0], output CN[4:0], control data input DATA_IN to the NMOS impedance matching network, the low potential in the data is driven output through the NMOS impedance matching network, and finally the number of parallel resistors is adjusted to achieve the impedance matching effect.

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