A frequency-jittering oscillator with stable duty cycle and a clock signal generation method

Abstract

The present application provides a frequency-jittering oscillator with a stable duty cycle and a clock signal generation method, which belongs to the field of oscillator technology. It includes: a charging module, a pulse signal output module, a frequency-jittering control module and a logic module; the charging module includes a current source and a current mirror, which is connected to the frequency-jittering control module and the pulse signal output module, and is used to charge the capacitor in the pulse signal output module; the pulse signal output module is connected to the logic module, and is used to output a pulse signal to the logic module; the frequency-jittering control module is connected to the pulse signal output module and the charging module, and is used to adjust the generation frequency of the pulse signal; the logic module is used to output a clock signal based on the pulse signal. Through the oscillator of the present application, a clock signal that can effectively suppress EMI interference and maintain a stable duty cycle can be emitted.

Description

Technical Field

[0001] The present application relates to the technical field of oscillators, and in particular to a frequency-jittering oscillator with a stable duty cycle and a clock signal generation method. Background Art

[0002] As a key component for providing a stable clock signal, the performance of the oscillator directly affects the working efficiency and reliability of the entire system. Currently, the oscillator technologies widely used in the market mainly include ring oscillators and RC oscillators. Although both have their own practicality in different application scenarios, they also have technical limitations that cannot be ignored:

[0003] Ring oscillator: As a common oscillator structure, the ring oscillator is widely adopted due to its advantages such as simple structure and fast startup speed. However, its biggest technical drawback is that it generates significant electromagnetic interference (EMI). When the ring oscillator works at high frequency, the current loop will generate strong electromagnetic radiation, which poses a serious challenge to the electromagnetic compatibility (EMC) of the surrounding circuits and even the entire system. Especially in high-density integration and strict requirements on the electromagnetic environment, such as medical equipment, aerospace and high-end communication equipment, the EMI problem of the ring oscillator is particularly prominent, limiting its scope of application.

[0004] RC oscillator: Compared with the ring oscillator, the RC oscillator uses the charging and discharging characteristics of resistors and capacitors to achieve oscillation, which is low-cost and flexible in design. However, a major disadvantage of the RC oscillator is its poor duty cycle stability. Since the parameters of RC components are easily affected by factors such as temperature and power supply voltage fluctuations, the rise and fall times of the oscillation waveform are inconsistent, which in turn affects the stability and accuracy of the duty cycle. This deficiency of the RC oscillator has become a major obstacle to its application in applications that require precise clock signals to maintain system synchronous operation, such as digital logic control and signal processing.

[0005] In view of the above technical status, developing an oscillator structure that can effectively suppress EMI interference and maintain a stable duty cycle has become an urgent problem to be solved in the current analog integrated circuit design field. Based on this background, this patent proposes an innovative analog chip oscillator design scheme, aiming to overcome the shortcomings of the existing technology and meet the market demand for high-performance oscillators. Summary of the invention

[0006] The purpose of the present application is to provide a frequency-jittering oscillator with a stable duty cycle and a clock signal generation method, which can generate a clock signal that can effectively suppress EMI interference and maintain a stable duty cycle.

[0007] The embodiment of the present application is implemented as follows:

[0008] In one aspect of an embodiment of the present application, a frequency-jittering oscillator with a stable duty cycle is provided, comprising: a charging module, a pulse signal output module, a frequency-jittering control module, and a logic module;

[0009] The charging module includes a current source and a current mirror, which are connected to the frequency jitter control module and the pulse signal output module, and are used to charge the capacitor in the pulse signal output module;

[0010] The pulse signal output module is connected to the logic module and is used to output a pulse signal to the logic module;

[0011] The frequency jitter control module is connected to the pulse signal output module and the charging module, and is used to adjust the generation frequency of the pulse signal;

[0012] The logic module is used to output a clock signal based on the pulse signal.

[0013] Optionally, the current mirror includes a first PMOS tube.

[0014] Optionally, the pulse signal output module includes:

[0015] A second PMOS transistor, a third PMOS transistor, a first capacitor, a second capacitor, a first NMOS transistor, a second NMOS transistor, a first comparator, and a second comparator;

[0016] The gate of the second PMOS tube is connected to the gate of the first PMOS tube, and the source is connected to the first capacitor and the negative input terminal of the first comparator, so as to charge the first capacitor;

[0017] The gate of the third PMOS tube is connected to the gate of the first PMOS tube, and the source is connected to the second capacitor and the negative input terminal of the second comparator, so as to charge the second capacitor;

[0018] The gate of the first NMOS transistor is connected to the logic module, the source is connected to the first capacitor, and the drain is connected to the other end of the first capacitor, and is used to discharge the first capacitor based on the control of the logic module;

[0019] The gate of the second NMOS tube is connected to the logic module, the source is connected to the second capacitor, and the drain is connected to the other end of the second capacitor, and is used to discharge the second capacitor based on the control of the logic module;

[0020] The positive input terminals of the first comparator and the second comparator are respectively connected to a reference voltage.

[0021] Optionally, the first comparator is used to determine the charging result of the first capacitor and send it to the logic module;

[0022] The second comparator is used to determine the charging result of the second capacitor and send the result to the logic module.

[0023] Optionally, the frequency jittering control module includes: a frequency jittering signal sending unit, a first switch, a second switch, a third switch, a fourth switch, a first current source, a second current source, a third current source, and a fourth current source;

[0024] The frequency-jittering signal sending unit is respectively connected to the first switch, the second switch, the third switch and the fourth switch, and is used to control the states of the switches;

[0025] The first switch is connected to the first current source, the second switch is connected to the second current source, the third switch is connected to the third current source, and the fourth switch is connected to the fourth current source.

[0026] Another aspect of the embodiments of the present application provides a method for generating a frequency-jittering clock signal with a stable duty cycle, which is applied to a frequency-jittering oscillator with a stable duty cycle, comprising:

[0027] Obtaining the voltage of the first capacitor or the second capacitor, and when the voltage of the capacitor is greater than the reference voltage, controlling the comparator corresponding to the capacitor to output a pulse signal to the logic module, and controlling the switch corresponding to the capacitor to open for discharge;

[0028] The logic module combines the pulse signals sent by the first comparator and the second comparator into a clock signal with a stable duty cycle;

[0029] Based on the preset frequency jittering logic, the first switch, the second switch, the third switch and the fourth switch are controlled to be opened in sequence, and the signal frequency of the clock signal with a stable duty cycle in the control logic module is controlled to obtain a frequency jittering clock signal with a stable duty cycle.

[0030] Optionally, controlling the capacitor corresponding to the switch to open and discharge further includes:

[0031] When the first switch is turned on for discharge, the second switch is controlled to be turned off to charge the second capacitor. When the second switch is turned on for discharge, the first switch is controlled to be turned off to charge the first capacitor.

[0032] Optionally, the clock signal combined into a duty cycle stable clock signal further includes:

[0033] The pulse signal sent by the first comparator and the second comparator is transmitted through a frequency divider to obtain the clock signal with a stable duty cycle.

[0034] Optionally, the preset frequency jittering logic includes:

[0035] The switch state is changed every 10 clock cycles;

[0036] The order of changing the switch state is a four-bit binary order of the first switch, the second switch, the third switch and the fourth switch, from large to small and then from small to large.

[0037] According to a third aspect of an embodiment of the present application, a computer-readable storage medium is provided, wherein a computer program is stored on the storage medium, and when the computer program is executed by a processor, the steps of a method for generating a frequency-jittering clock signal with a stable duty cycle are implemented.

[0038] The beneficial effects of the embodiments of the present application include:

[0039] The embodiments of the present application provide a frequency-jittering oscillator with a stable duty cycle and a clock signal generation method, which can generate a clock signal that can effectively suppress EMI interference and maintain a stable duty cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 A schematic diagram of the structure of a frequency-jittering oscillator with a stable duty cycle provided in an embodiment of the present application;

[0042] Figure 2 A schematic diagram of the structure of a frequency-jittering oscillator with a stable duty cycle provided by another embodiment of the present application;

[0043] Figure 3 A flow chart of a method for generating a frequency-jittering clock signal with a stable duty cycle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0045] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0046] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0047] In the description of the present application, it should be noted that the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0048] In one aspect of an embodiment of the present application, a frequency-jittering oscillator with a stable duty cycle is provided, comprising: a charging module, a pulse signal output module, a frequency-jittering control module, and a logic module;

[0049] like Figure 1 As shown, Figure 1 The structural schematic diagram of the frequency-jittering oscillator with a stable duty cycle provided in the embodiment of the present application is easy to understand. The present embodiment is mainly to provide an oscillator structure that can both suppress EMI interference and maintain a stable duty cycle. Therefore, a stable duty cycle is maintained through a pulse signal output module, and EMI interference is suppressed through a frequency-jittering control module. Based on this, a frequency-jittering oscillator with a stable duty cycle is constructed.

[0050] The charging module includes a current source and a current mirror, which are connected to the frequency jitter control module and the pulse signal output module, and are used to charge the capacitor in the pulse signal output module;

[0051] In this embodiment, the charging module is used to charge the internal capacitor of the pulse signal output module. The current source can provide current, and the current mirror proportionally copies the current to the pulse signal output module and charges the capacitor in the pulse signal output module. It is easy to understand that there are multiple capacitors in the pulse signal output module, so a current mirror needs to be set to charge the capacitor.

[0052] The pulse signal output module is connected to the logic module and is used to output a pulse signal to the logic module;

[0053] It is easy to understand that the pulse signal output module is based on the charging and discharging results of the capacitor, and then compares the comparison results through the built-in comparator, outputs the comparison results as a pulse signal, and then outputs the pulse signal to the logic module for processing as a clock signal.

[0054] The frequency jitter control module is connected to the pulse signal output module and the charging module, and is used to adjust the generation frequency of the pulse signal;

[0055] In this embodiment, the frequency jitter control module is used to adjust the current size of the current source in the charging module, further change the charging current size of the capacitor in the pulse signal output module, change the output frequency of the pulse signal through different charging times, and further change the clock frequency of the output clock signal of the logic module.

[0056] The logic module is used to output a clock signal based on the pulse signal.

[0057] It is easy to understand that for every pulse signal, the logic signal will generate a pulse output. When there are two pulse signals, they will be merged into one pulse signal, and finally it can be output as a clock signal with a stable duty cycle. By adjusting the frequency of the pulse signal through the frequency jittering control module, it can output a clock signal with a stable duty cycle and frequency jittering.

[0058] Optionally, the current mirror includes a first PMOS tube.

[0059] In this embodiment, the first PMOS tube and the other PMOS tubes are respectively formed into current mirrors, so that the same current can be copied to charge multiple branches. Figure 2 As shown,.

[0060] Optionally, the pulse signal output module includes: a second PMOS tube, a third PMOS tube, a first capacitor, a second capacitor, a first NMOS tube, a second NMOS tube, a first comparator and a second comparator; the gate of the second PMOS tube is connected to the gate of the first PMOS tube, and the source is connected to the first capacitor and the negative input end of the first comparator, so as to charge the first capacitor; the gate of the third PMOS tube is connected to the gate of the first PMOS tube, and the source is connected to the second capacitor and the negative input end of the second comparator, so as to charge the second capacitor; the gate of the first NMOS tube is connected to the logic module, the source is connected to the first capacitor, and the drain is connected to the other end of the first capacitor, so as to discharge the first capacitor based on the control of the logic module; the gate of the second NMOS tube is connected to the logic module, the source is connected to the second capacitor, and the drain is connected to the other end of the second capacitor, so as to discharge the second capacitor based on the control of the logic module; the positive input ends of the first comparator and the second comparator are respectively connected to the reference voltage.

[0061] In this embodiment, the second PMOS tube and the third PMOS tube in the pulse signal output module respectively form a current mirror with the first PMOS tube, and C1 and C2 are charged respectively through the current mirror. As the charging current increases, the upper plate voltage of capacitors C1 and C2 gradually increases until the upper plate voltage value of any capacitor exceeds the reference voltage connected to the positive ends of the two comparators. The corresponding comparator will output a high signal to the logic module, and the logic module will output a high signal and control the corresponding NMOS tube to turn on, then discharge the corresponding capacitor, and output a low signal to another capacitor to stop discharging. At this time, the other capacitor starts to charge until the upper plate voltage value of the capacitor exceeds the reference voltage, and then repeats.

[0062] In a specific embodiment, the current source I1 provides current, and the current is proportionally copied to the second PMOS tube and the branch where the third PMOS tube is located through the current mirror, and the capacitors C1 and C2 are charged respectively. With the charging current, the upper plate voltage of the capacitors C1 and C2 will gradually rise until the upper plate voltage value of any capacitor exceeds the reference voltage, and the logic circuit controls the switch state of the first NMOS tube and the second NMOS tube. For example, when the upper plate voltage value of the capacitor C1 exceeds the reference voltage, after a short delay, the comparator COM1 outputs a high signal to the logic module, and the LOGIC module outputs a high signal to control the first NMOS tube to turn on and discharge the C1 capacitor, and outputs a low signal to the second NMOS tube, and the second NMOS tube is turned off and stops discharging. At this time, the capacitor C2 starts to charge. Until the upper plate voltage value of the capacitor C2 exceeds VREF, the comparator COM2 outputs a high signal to the logic module to control the second NMOS tube to turn on and start discharging, the first NMOS tube is turned off, and the capacitor C1 starts to charge. Under the control of the logic module, the first NMOS tube and the second NMOS tube are switched on and off alternately, so the two comparators COM1 and COM2 will output pulse signals alternately.

[0063] Optionally, the first comparator is used to determine the charging result of the first capacitor and send it to the logic module; the second comparator is used to determine the charging result of the second capacitor and send it to the logic module.

[0064] It is easy to understand that one end of the comparator is connected to the reference voltage and the other end is connected to the capacitor, so the charging result of the corresponding capacitor can be determined and a high signal can be output into the logic signal.

[0065] Optionally, the frequency jittering control module includes: a frequency jittering signal sending unit, a first switch, a second switch, a third switch, a fourth switch, a first current source, a second current source, a third current source, and a fourth current source; the frequency jittering signal sending unit is respectively connected to the first switch, the second switch, the third switch and the fourth switch to control the state of the switch; the first switch is connected to the first current source, the second switch is connected to the second current source, the third switch is connected to the third current source, and the fourth switch is connected to the fourth current source.

[0066] In this embodiment, the frequency jitter control module is used to control the frequency jitter of the clock signal. First, the frequency jitter signal sending unit controls the four switches from the first switch to the fourth switch through signals. For example, after every 10 clock cycles, the switch state is changed once, and the four switches are turned on from large to small in the order of four-bit binary, and then from small to large, and then cycled. In this way, the number of current sources connected in parallel in the circuit is continuously changed, so as to change the current copied by the first PMOS tube of the current mirror, thereby changing the charging current of the capacitor, and using different charging times to output different clock frequencies.

[0067] On the other hand, an embodiment of the present application provides a method for generating a frequency-jittering clock signal with a stable duty cycle, which is applied to a frequency-jittering oscillator with a stable duty cycle, including: obtaining the voltage of the first capacitor or the second capacitor, and when the voltage of the capacitor is greater than the reference voltage, controlling the comparator corresponding to the capacitor to output a pulse signal to the logic module, and controlling the switch corresponding to the capacitor to open for discharge; the logic module combines the pulse signals sent by the first comparator and the second comparator into a clock signal with a stable duty cycle; based on a preset frequency-jittering logic, controlling the first switch, the second switch, the third switch and the fourth switch to open in sequence, controlling the signal frequency of the clock signal with a stable duty cycle in the logic module, and obtaining a frequency-jittering clock signal with a stable duty cycle.

[0068] In this embodiment, if Figure 3 As shown, Figure 3A flow chart of a method for generating a frequency-jittering clock signal with a stable duty cycle provided in an embodiment of the present application. The two capacitors in the pulse signal output module are charged in real time. When the capacitor voltage value is greater than the reference voltage, the comparator is controlled to release a pulse signal to the logic module. Therefore, it is necessary to obtain the voltage of the two capacitors. When the capacitor voltage is greater than the reference voltage, the corresponding switch needs to be controlled to discharge. The logic module combines the pulse signals sent by the comparator into a clock signal. Since it is a two-way pulse signal, the duty cycle can be stabilized at 50%. Then, the preset frequency-jittering logic module controls the charging speed of the capacitor by controlling the size of the current source. Therefore, the speed at which the pulse signal output module outputs the pulse signal can be controlled, and the clock signal frequency can be further controlled to obtain a clock signal with a stable duty cycle with frequency jittering.

[0069] The clock signal generated by the oscillator has steep rising / falling edges, which will produce relatively strong electromagnetic radiation and electromagnetic interference. If the clock signal has a fixed frequency, such as 10MHz, these radiations and interferences will be superimposed on this frequency, and will eventually show a strong peak at this frequency of the EMI detection equipment. By continuously changing the output clock frequency through the frequency-jittering switch, for example, outputting a CLK signal of 8 to 12MHz, the interference and radiation of EMI will be superimposed within this frequency band, and will eventually show a much lower peak within this frequency band of the EMI detection equipment, thereby improving the EMI spike problem.

[0070] Optionally, controlling the capacitor corresponding to the switch to open and discharge further includes: when the first switch is opened and discharged, controlling the second switch to close to charge the second capacitor; when the second switch is opened and discharged, controlling the first switch to close to charge the first capacitor.

[0071] It is easy to understand that when the first switch is turned on, the second switch is turned off to avoid discharge. Similarly, when the second switch is turned on, the first switch is turned off.

[0072] Optionally, merging into a clock signal with a stable duty cycle also includes: based on the pulse signal sent by the first comparator and the second comparator, and then transmitting through a frequency divider, to obtain the clock signal with a stable duty cycle.

[0073] In this embodiment, after the two pulse signals are combined into one pulse signal, they still need to be transmitted through a frequency divider before they can be output as a clock signal.

[0074] Optionally, the preset frequency jittering logic includes: changing the switch state once every 10 clock cycles; the order of changing the switch state is in the order of the four-bit binary of the first switch, the second switch, the third switch and the fourth switch, from large to small and then from small to large.

[0075] It is easy to understand that when a clock signal of 8 to 12 MHz needs to be output, the switch is cyclically controlled in a sequence of ten clock cycles and four binary bits. When a clock signal in another clock frequency range needs to be output, the switch is cyclically controlled in a sequence of other clock cycles and sequences.

[0076] The following describes the apparatus, device, storage medium, etc. corresponding to the method for generating a frequency-jittered clock signal with a stable duty cycle provided by the present application. The specific implementation process and technical effects are described above and will not be repeated below.

[0077] The above-mentioned device is used to execute the method provided by the aforementioned embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0078] The above modules may be one or more integrated circuits configured to implement the above duty cycle stable frequency jitter clock signal generation method, such as: one or more specific integrated circuits (Application Specific Integrated Circuit, referred to as ASIC), or, one or more microprocessors, or, one or more field programmable gate arrays (Field Programmable Gate Array, referred to as FPGA), etc. For another example, when a module above is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, referred to as CPU) or other processors that can call program codes. For another example, these modules can be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0079] The third aspect of the embodiments of the present application provides a computer-readable storage medium, characterized in that a computer program is stored on the storage medium, and when the computer program is executed by the processor, the steps of the method for generating a frequency-jittering clock signal with a stable duty cycle are implemented. In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0080] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0081] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0082] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform some steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (English: Read-Only Memory, abbreviated: ROM), random access memory (English: RandomAccess Memory, abbreviated: RAM), disk or optical disk and other media that can store program codes.

[0083] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0084] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A frequency-jittering oscillator with a stable duty cycle, characterized in that: include: Charging module, pulse signal output module, frequency jitter control module and logic module; The charging module includes a current source and a current mirror, which are connected to the frequency jitter control module and the pulse signal output module, and are used to charge the capacitor in the pulse signal output module; The pulse signal output module is connected to the logic module and is used to output a pulse signal to the logic module; The frequency jitter control module is connected to the pulse signal output module and the charging module, and is used to adjust the generation frequency of the pulse signal; The logic module is used to output a clock signal based on the pulse signal.

2. The duty cycle-stabilized frequency-jittering oscillator according to claim 1, characterized in that: The current mirror includes a first PMOS tube.

3. The duty cycle-stabilized frequency-jittering oscillator according to claim 1, characterized in that: The pulse signal output module comprises: A second PMOS transistor, a third PMOS transistor, a first capacitor, a second capacitor, a first NMOS transistor, a second NMOS transistor, a first comparator, and a second comparator; The gate of the second PMOS tube is connected to the gate of the first PMOS tube, and the source is connected to the first capacitor and the negative input terminal of the first comparator, so as to charge the first capacitor; The gate of the third PMOS tube is connected to the gate of the first PMOS tube, and the source is connected to the second capacitor and the negative input terminal of the second comparator, so as to charge the second capacitor; The gate of the first NMOS transistor is connected to the logic module, the source is connected to the first capacitor, and the drain is connected to the other end of the first capacitor, and is used to discharge the first capacitor based on the control of the logic module; The gate of the second NMOS tube is connected to the logic module, the source is connected to the second capacitor, and the drain is connected to the other end of the second capacitor, and is used to discharge the second capacitor based on the control of the logic module; The positive input terminals of the first comparator and the second comparator are respectively connected to a reference voltage.

4. The duty cycle-stabilized frequency-jittering oscillator according to claim 3, characterized in that: The first comparator is used to determine the charging result of the first capacitor and send it to the logic module; The second comparator is used to determine the charging result of the second capacitor and send the result to the logic module.

5. The duty cycle-stabilized frequency-jittering oscillator according to claim 1, characterized in that: The frequency jittering control module includes: a frequency jittering signal sending unit, a first switch, a second switch, a third switch, a fourth switch, a first current source, a second current source, a third current source, and a fourth current source; The frequency-jittering signal sending unit is respectively connected to the first switch, the second switch, the third switch and the fourth switch, and is used to control the states of the switches; The first switch is connected to the first current source, the second switch is connected to the second current source, the third switch is connected to the third current source, and the fourth switch is connected to the fourth current source.

6. A method for generating a frequency-jittering clock signal with a stable duty cycle, applied to a frequency-jittering oscillator with a stable duty cycle, characterized in that: include: Obtaining the voltage of the first capacitor or the second capacitor, and when the voltage of the capacitor is greater than the reference voltage, controlling the comparator corresponding to the capacitor to output a pulse signal to the logic module, and controlling the switch corresponding to the capacitor to open for discharge; The logic module combines the pulse signals sent by the first comparator and the second comparator into a clock signal with a stable duty cycle; Based on the preset frequency jittering logic, the first switch, the second switch, the third switch and the fourth switch are controlled to be opened in sequence, and the signal frequency of the clock signal with a stable duty cycle in the control logic module is controlled to obtain a frequency jittering clock signal with a stable duty cycle.

7. The method for generating a frequency-jittering clock signal with a stable duty cycle as claimed in claim 6, characterized in that: The controlling the capacitor to correspond to the switch to open and discharge also includes: When the first switch is turned on for discharge, the second switch is controlled to be turned off to charge the second capacitor. When the second switch is turned on for discharge, the first switch is controlled to be turned off to charge the first capacitor.

8. The method for generating a frequency-jittering clock signal with a stable duty cycle as claimed in claim 6, characterized in that: The clock signal merged into a stable duty cycle also includes: The pulse signal sent by the first comparator and the second comparator is transmitted through a frequency divider to obtain the clock signal with a stable duty cycle.

9. The method for generating a frequency-jittering clock signal with a stable duty cycle as claimed in claim 6, characterized in that: The preset frequency jittering logic includes: The switch state is changed every 10 clock cycles; The order of changing the switch state is a four-bit binary order of the first switch, the second switch, the third switch and the fourth switch, from large to small and then from small to large.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, which, when executed by a processor, implements the steps of the method described in any one of claims 6 to 9.

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