Clock buffer and clock module

Abstract

The invention discloses a clock buffer and a clock module, and relates to the technical field of clock circuits. The clock buffer comprises a first capacitor, a first transistor, a second transistor, a current mirror and a hysteresis comparator, dC of externally input clock signals is removed through DC blocking of a first capacitor, the clock signals are biased to DC voltage provided by a first branch of the current mirror through a first transistor, and the clock signals are biased to DC voltage provided by a second branch of the current mirror through a reference voltage follower circuit formed by a second transistor and the second branch of the current mirror. The DC bias voltage in the composite signal input to the hysteresis comparator is maintained to be equal to the reference voltage under different operation conditions, and the clock buffer can ensure that the duty ratio of the output signal of the hysteresis comparator is kept to be 50%.

Description

Technical Field

[0001] The present invention relates to the technical field of clock circuits, and in particular to a clock buffer and a clock module. Background Art

[0002] In electronic systems, clock signals play a vital role. They provide a synchronization reference for digital circuits and ensure that various components work in coordination. However, electromagnetic interference from the environment, power supply noise, ground bounce, etc. will have a negative impact on the clock signal, resulting in signal distortion or instability. In order to ensure the performance of the system, effective measures must be taken to process the clock signal. In the related art, the clock signal is processed by a clock buffer that converts a sine wave into a square wave. The conversion of the clock signal sine wave into a square wave is mainly achieved in two ways: (1) selectively passing the signal within a specific frequency range through a filter; (2) using a detector or threshold circuit to remove noise below the set amplitude. Based on this, when designing a clock buffer for converting a sine wave into a square wave, several commonly used MOS integrated circuit architectures are as follows: (1) Single limit comparator architecture like Figure 1 As shown in the figure, a MOS comparator is used to compare the sine wave input with the fixed reference voltage (vref) generated by other modules. When the clock signal is higher than vref, the comparator outputs a high level; otherwise, it outputs a low level. However, since the vref inside the MOS comparator cannot follow the intermediate voltage fluctuation of the sine wave output by the crystal oscillator, the output clock duty cycle will change.

[0003] (2) Schmitt trigger architecture like Figure 2 As shown in the figure, the Schmitt trigger is a logic gate circuit with hysteresis characteristics that can effectively convert a sine wave into a square wave. It controls the switching of the output state through built-in high and low threshold voltages, providing fast response and resistance to amplitude interference problems. The Schmitt trigger is suitable for high-speed clock signal processing due to its high noise immunity and fast response time. However, since the duty cycle of the output signal changes with different points of the sine waveform, it may be unstable or even erroneous.

[0004] It can be seen that when the DC value of the sine wave output by the external crystal oscillator is not fixed and the power supply voltage changes, if a dual-input comparator + fixed vref architecture is used, the duty cycle may deviate significantly from 50% due to vref mismatch; if a Schmitt trigger architecture is selected, when the threshold flip point does not match the clock signal, the duty cycle of the output signal will also be unstable, affecting the synchronization effect and performance of the system. Summary of the invention

[0005] Based on this, it is necessary to provide a clock buffer and a clock module that can keep the output square wave signal at a stable duty cycle in order to solve the above technical problems.

[0006] A clock buffer comprises a first capacitor, a first transistor, a second transistor, a current mirror and a hysteresis comparator; One end of the first capacitor is connected to the clock signal, and the other end of the first capacitor inputs the alternating current of the clock signal into the gate of the first transistor (MN0); The current mirror comprises a first branch and a second branch composed of transistors, the input end of the first branch and the input end of the second branch are respectively connected to a working power supply; the output end of the first branch of the current mirror is connected to the drain of the first transistor and connected to the negative input end of the hysteresis comparator; the output end of the second branch of the current mirror is connected to the drain of the second transistor and connected to the positive input end of the hysteresis comparator; The gate and drain of the second transistor are short-circuited; the source of the first transistor and the source of the second transistor are grounded respectively; The output terminal of the hysteresis comparator outputs a clock signal; Among them, the negative input end of the hysteresis comparator is a composite signal; the positive input end of the hysteresis comparator is a reference voltage; the composite signal is generated by superimposing the DC bias voltage output by the first branch and the AC quantity output by the first transistor; the reference voltage is the same as the DC bias voltage.

[0007] A clock module comprises a clock generating circuit and the clock buffer in the above solution.

[0008] The clock buffer and clock module above remove the DC quantity of the clock signal through the first capacitor, and then bias the clock signal to a new DC voltage through the first transistor and the first branch of the current mirror, so that the composite signal obtained by superimposing the AC quantity of the clock signal and the DC bias quantity is used as one end input of the hysteresis comparator. With the cooperation of the second branch of the current mirror and the second transistor, the second branch of the current mirror can generate the same DC voltage as the other end input of the hysteresis comparator, thereby ensuring that the reference signal of the hysteresis comparator is always in the middle of the waveform corresponding to the composite signal, so that the hysteresis comparator can output a square wave signal with a stable duty cycle, thereby improving the stability and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a single-limit comparator architecture in the related art; Figure 2 A schematic diagram of a Schmitt trigger architecture in the related art; Figure 3 A schematic diagram of the structure of a clock buffer in one embodiment; Figure 4 is a schematic diagram of waveforms of an input signal and an output signal of a hysteresis comparator in one embodiment; Figure 5 is a schematic diagram of the structure of a current mirror in one embodiment; Figure 6 is another structural schematic diagram of a current mirror in one embodiment; Figure 7 is another structural schematic diagram of a gain network in one embodiment; Figure 8 is a disassembled schematic diagram of a gain network in one embodiment; Fig. 9 A schematic diagram of frequency domain transmission characteristics of a gain network in one embodiment; Fig.10 It is a schematic diagram of the time domain transmission characteristics of the gain network within the working frequency in one embodiment; Fig.11 It is a schematic diagram of the time domain transmission characteristics of the gain network outside the working frequency in one embodiment; Fig.12 is a simplified schematic diagram of an overall circuit of a first capacitor, a second capacitor, a resistor and a first transistor in one embodiment; Fig.13 is another structural schematic diagram of a gain network in an embodiment; Fig.14 A waveform processing schematic diagram of a hysteresis comparator in one embodiment; Figure numerals: first capacitor C1, second capacitor C2, resistor R1, comparator CMP, positive input terminal V+ of the comparator, negative input terminal V- of the comparator, composite signal bufout, reference voltage vref, first transistor MN0, second transistor MN1, third transistor MP0, fourth transistor MP1, fifth transistor MP2, sixth transistor MP3, seventh transistor MP4, eighth transistor MP5. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0011] The implementation details of the technical solution of the embodiment of the present application are described in detail below.

[0012] In one embodiment, Figure 3 As shown, Figure 3A schematic diagram of the structure of a clock buffer is shown. The clock buffer includes a first capacitor C1, a first transistor MN0, a second transistor MN1, a current mirror and a hysteresis comparator CMP. The connection relationship and working principle between the various components included in the clock buffer are described below.

[0013] The clock signal can be generated by different clock sources (such as crystal oscillators, RC oscillators, LC oscillators, etc.). In this embodiment, a crystal oscillator is used as a clock source to generate a sinusoidal clock signal. One end of the first capacitor C1 is connected to the clock signal, and the clock signal first passes through the first capacitor C1. In practical applications, the focus is on the AC component of the clock signal. The DC component may affect the validity of the signal, and the DC component of the clock signal may be superimposed with noise. The first capacitor C1 has the function of allowing the AC signal to pass through while blocking the DC component. When the clock signal is applied to the first capacitor C1, the first capacitor C1 will charge and discharge, so that the DC component in the clock signal is blocked, and only the AC component can pass through the first capacitor C1, thereby removing the DC component of the clock signal. Here, the presence of the first capacitor C1 ensures that the subsequent circuit only receives the AC component of the clock signal.

[0014] The other end of the first capacitor C1 is connected to the gate of the first transistor MN0, so that the clock signal enters the gate of the first transistor MN0 after passing through the first capacitor C1. The first transistor MN0 here is an N-type MOS tube, and its source is grounded. The gate voltage of the first transistor MN0 is controlled by the clock signal, which determines the conduction state of the first transistor MN0. When the amplitude of the clock signal reaches a certain threshold, the first transistor MN0 will be turned on, allowing current to flow, thereby amplifying the clock signal, so that the amplitude of the clock signal is enhanced, the clarity of the clock signal is improved, and noise and distortion are reduced. The gain characteristics of the first transistor MN0 enable the amplitude of the output signal to be adjusted according to the change of the clock signal. Finally, the amplified signal is output from the drain of the first transistor MN0 to form an enhanced clock signal.

[0015] The current mirror is used to replicate the input current and provide the same or proportional current at the output. Here, the current mirror is mainly composed of transistors, and the characteristics of the transistors are used to make the input current pass through one or more transistors to generate the same current at the output. Here, the current mirror includes a first branch and a second branch, the input ends of the first branch and the second branch are respectively connected to the working power supply, and the output ends of the first branch and the second branch are connected to the load. The current of the first branch is used as a reference current. Since the first branch and the second branch have the same composition structure, the current of the second branch will replicate the current of the first branch.

[0016] The output end of the first branch is connected to the drain of the first transistor MN0, and then connected to the negative input end V- of the hysteresis comparator CMP. The first branch provides a new DC bias voltage for the clock signal. The clock signal can be biased to the new DC voltage through the first branch and the first transistor MN0, so that after the DC amount of the clock signal is removed, a DC bias amount can be re-superimposed on the AC amount of the clock signal. Based on this, the negative input end V- of the hysteresis comparator CMP is a composite signal obtained by superimposing the AC amount output by the first transistor MN0 and the DC bias amount output by the first branch (i.e. Figure 3 bufout in .

[0017] The output end of the second branch is connected to the drain of the second transistor MN1, and then connected to the positive input terminal V+ of the hysteresis comparator CMP. The second transistor MN1 is an N-type MOS tube, whose source is grounded and the gate and drain are short-circuited, which means that the second transistor MN1 operates in a diode connection mode. Since the gate and drain of the second transistor MN1 are short-circuited, the gate voltage of the second transistor MN1 is equal to the drain voltage, so that the second transistor MN1 is always in the saturation region and maintains a stable working state. In this working mode, the second transistor MN1 acts as a current source controlled by the second branch, and a stable reference voltage (vref) is established at the same time. Since the drain and gate of the second transistor MN1 are connected to the output end of the second branch, it means that the drain voltage of the second transistor MN1 is vref. In the current mirror, the current output by the second branch is basically stable, so that the second transistor MN1 can stabilize vref.

[0018] Since the first branch and the second branch in the current mirror are in the same current working condition, the first branch and the second branch can output equal voltages, that is, the DC bias voltage output by the first branch is equal to the reference voltage output by the second branch.

[0019] The hysteresis comparator CMP is a comparator with hysteresis characteristics. Different comparator topologies can be selected to implement the hysteresis comparator CMP with dual-end input and single-end output. The hysteresis comparator CMP compares the composite signal with the reference voltage and outputs the corresponding square wave (i.e. Figure 3 CKO in the figure). When the composite signal is higher than the reference voltage, the output state of the hysteresis comparator CMP becomes high (logic 1); when the composite signal is lower than the reference voltage, the output state of the hysteresis comparator CMP becomes low (logic 0). Since the reference voltage is equal to the DC bias voltage in the composite signal, the reference voltage can always be located in the middle of the sine wave corresponding to the composite signal, so that the hysteresis comparator CMP can output Figure 4 The square wave signal with a duty cycle of 50% provides a more stable clock signal for use in subsequent modules.

[0020] In the clock buffer in the above embodiment, the DC amount of the external input clock signal is removed by isolating the DC through the first capacitor C1, and the clock signal is biased to the DC voltage provided by the first branch of the current mirror through the first transistor MN0. The reference voltage follower circuit composed of the second transistor MN1 and the current mirror maintains the DC bias voltage in the composite signal input to the hysteresis comparator CMP equal to the reference voltage under different operating conditions, thereby ensuring that the reference voltage is always located in the middle position of the waveform corresponding to the composite signal, thereby ensuring that the square wave signal output by the hysteresis comparator CMP can maintain a 50% duty cycle, providing a stable and reliable clock source for subsequent modules.

[0021] In practical applications, the first branch and the second branch of the current mirror may be formed by different numbers of transistors. The specific circuit structure of the current mirror is described below through two embodiments.

[0022] In one embodiment, Figure 5 As shown, the design of the current mirror can be formed by a single P-type MOS tube, that is, the current mirror includes two transistors, and only the third transistor MP0 and the fourth transistor MP1 are used to provide the current mirror. There is a third transistor MP0 in the first branch, and there is a fourth transistor MP1 in the second branch. The third transistor MP0 and the fourth transistor MP1 are P-type MOS tubes. In the first branch, the drain of the third transistor MP0 is used as the input end of the first branch, and is connected to the working power supply, which is a high-voltage positive power supply voltage. The source of the third transistor MP0 is used as the output end of the first branch, connected to the drain of the first transistor MN0, and provides a DC bias voltage for the AC component output by the first transistor MN0, and is connected to the negative input terminal V- of the hysteresis comparator CMP. In the second branch, the drain of the fourth transistor MP1 serves as the input terminal of the second branch and is connected to a working power supply, which is also a high-voltage positive power supply voltage. The source of the fourth transistor MP1 serves as the output terminal of the second branch and is connected to the drain of the second transistor MN1 and is connected to the positive input terminal V+ of the hysteresis comparator CMP to provide a reference voltage for the hysteresis comparator CMP.

[0023] The gate of the third transistor MP0 and the gate of the fourth transistor MP1 are both connected to the first bias voltage, which is used to set the working state of the transistor so that it can work in the saturation region. By controlling the gate voltage, the current flowing through the transistor can be accurately controlled. During the operation of the circuit, when the third transistor MP0 is turned on, the current flowing through the third transistor MP0 will be set as a reference current. Since the gate voltage of the third transistor MP0 is the same as that of the fourth transistor MP1, and their drain voltages are also the same, the source current of the fourth transistor MP1 will be equal to or proportional to the current of the third transistor MP0. This current replication feature enables the current mirror to stably replicate the input current to the output end.

[0024] The current mirror in the above embodiment uses a single P-type MOS tube to implement the current replication function. The working power supply and bias voltage of the two P-type MOS tubes are the same, so that the current mirror can maintain the stability of the output current under different load conditions, which is conducive to making the DC bias voltage equal to the reference voltage.

[0025] In one embodiment, Figure 6 As shown, the current mirror includes four transistors, a third transistor MP0 and a fifth transistor MP2 are present in the first branch, and a fourth transistor MP1 and a sixth transistor MP3 are present in the second branch. These four transistors are all P-type MOS tubes. In the first branch, the drain of the third transistor MP0 is connected to the working power supply as the input end of the first branch. The source of the third transistor MP0 is connected to the drain of the fifth transistor MP2, and the source of the fifth transistor MP2 is connected to the drain of the first transistor MN0 as the output end of the first branch, providing a DC bias voltage for the AC component output by the first transistor MN0, and connected to the negative input terminal V- of the hysteresis comparator CMP.

[0026] In the second branch, the drain of the fourth transistor MP1 is connected to the working power supply as the input of the second branch. The source of the fourth transistor MP1 is connected to the drain of the sixth transistor MP3. The source of the sixth transistor MP3 is connected to the drain of the second transistor MN1 as the output of the second branch and is connected to the positive input V+ of the hysteresis comparator CMP as the reference voltage of the hysteresis comparator CMP.

[0027] In the current mirror, the gate of the third transistor MP0 and the gate of the fourth transistor MP1 are both connected to the first bias voltage, and the first bias voltage controls the gate voltage of the third transistor MP0 and the fourth transistor MP1, so that they work in the saturation region. The main function of the third transistor MP0 and the fourth transistor MP1 is to provide a constant current. Since the gate voltage of the third transistor MP0 and the fourth transistor MP1 is the same and the drain voltage is also the same, their currents are equal or proportional. The third transistor MP0 and the fourth transistor MP1 provide a constant current that is respectively transmitted to the fifth transistor MP2 and the sixth transistor MP3. The gate of the fifth transistor MP2 and the gate of the sixth transistor MP3 are both connected to the second bias voltage. The second bias voltage controls the gate voltage of the fifth transistor MP2 and the sixth transistor MP3, so that they work in the saturation region. The main function of the fifth transistor MP2 and the sixth transistor MP3 is to transfer the current from the third transistor MP0 and the fourth transistor MP1 to the load.

[0028] Since the gate voltage of the fifth transistor MP2 and the drain voltage of the sixth transistor MP3 are the same, the currents therebetween are equal or in a proportional relationship. Based on this, the currents of the first branch and the second branch are equal or in a proportional relationship, thereby copying the current to the second branch, so that the current mirror can maintain the stability of the output current under different load conditions, which is conducive to making the DC bias voltage equal to the reference voltage.

[0029] The current mirror in the above embodiment has a two-stage structure. Two MOS tubes are added on the basis of two MOS tubes to form a wide swing current mirror, thereby achieving higher output impedance, larger output swing and higher current matching accuracy.

[0030] In one embodiment, the width ratio of the first transistor MN0 to the second transistor MN1 is limited to satisfy N:1, and the width ratio of the transistor in the first branch to the transistor in the second branch of the current mirror also satisfies N:1, thereby ensuring that the DC bias voltage and the reference voltage can remain equal.

[0031] The width of the first transistor MN0 is N times that of the second transistor MN1, so under the same gate-source voltage, the current of the first transistor MN0 is N times that of the second transistor MN1. Assuming that the current mirror includes a third transistor MP0 and a fourth transistor MP1, since the width of the third transistor MP0 is N times that of the fourth transistor MP1, under the same gate-source voltage, the current of the third transistor MP0 is N times that of the fourth transistor MP1. The source of the fourth transistor MP1 is connected to the drain of the second transistor MN1, and the current flowing through the fourth transistor MP1 is the current of the second transistor MN1. Due to the proportional relationship between the first transistor MN0 and the second transistor MN1, and the width ratio of the third transistor MP0 to the fourth transistor MP1 is N:1, which makes the gate-source voltage of the third transistor MP0 equal to that of the fourth transistor MP1, therefore, the source voltage of the third transistor MP0 and the fourth transistor MP1 should be equal in an ideal case, that is, the DC bias voltage output by the first branch is equal to the reference voltage output by the second branch. Likewise, when the current mirror includes four transistors, the DC bias voltage output by the first branch is equal to the reference voltage output by the second branch.

[0032] In one embodiment, Figure 7 As shown, in order to have greater advantages in terms of gain stability, frequency response, noise suppression, etc., a second capacitor C2 and a resistor R1 are also introduced into the clock buffer, and the gain bias part is realized based on the NMOS bias and the resistor-capacitor network. The second capacitor C2 and the resistor R1 are connected in parallel to form a frequency-dependent impedance network, which is connected between the gate and the drain of the first transistor MN0, providing a negative feedback loop. This negative feedback loop will affect the gain characteristics of the first transistor MN0, making its gain dependent on the frequency.

[0033] It should be noted that in Figure 7 Based on the circuit shown in the figure, the current mirror can be constructed using a single P-type MOS tube (such as Figure 5 The specific structure of the current mirror shown in FIG. 1 ) can also be a two-stage structure (such as Figure 6 Specific structure of the current mirror shown).

[0034] exist Figure 7 Based on this, the gain network can be further decomposed into Figure 8 As shown in the structure diagram, parasitic capacitance refers to the non-ideal capacitance caused by the device structure, layout and connection in the circuit. In the MOS tube, there is an electric field between the source, drain and gate, which will form parasitic capacitance. Figure 8 In the figure, V1 represents the original waveform of the clock signal, and V2 represents the waveform of the clock signal after being amplified by the gain network. Fig. 9 As shown, Fig. 9The frequency domain transmission characteristics of the gain network composed of NMOS, resistor R1, and capacitor are shown. Fig. 9 The first inflection point in is the low-frequency bandwidth mainly composed of the first capacitor C1, the second capacitor C2 and the resistor R1, which can be adjusted by controlling the values ​​of the first capacitor C1, the second capacitor C2 and the resistor R1. The second inflection point is the inflection point generated by the output parasitic capacitance and the working bandwidth of the first transistor MN0, which can be adjusted by increasing the driving capability of the first transistor MN0.

[0035] Within the operating frequency, the gain network can amplify the clock signal, and its time domain transmission characteristics are as follows: Fig.10 As shown in the figure, the time domain transmission characteristic is manifested as signal amplification. Outside the operating frequency, the clock signal is attenuated, and its time domain transmission characteristic is as follows Fig.11 As shown, the time domain transmission characteristic is manifested as a weakening of the signal. In practical applications, the small signal of the overall circuit of the first capacitor C1, the second capacitor C2, the resistor R1 and the first transistor MN0 can be simplified as follows: Fig.12 The circuit diagram is shown in Fig.12 In the figure, Vin represents the input clock signal, Vout represents the amplified clock signal, V1 represents the original waveform of the clock signal, and the transfer function from input to output of the gain network is:

[0036] in, is the complex impedance of the circuit.

[0037] In the above formula, is a complex frequency variable, represents the capacitance value of the first capacitor C1, represents the output impedance of the first transistor MN0, represents the transconductance of the first transistor MN0, represents the resistance value of resistor R1, represents the capacitance value of the second capacitor C2.

[0038] From the above formula, we can see that when the selected resistance R1 is much larger than 1 (such as ),but It can be simplified to:

[0039] When choosing the appropriate first capacitor C1 and second capacitor C2 (such as 100 fF level) and transconductance (1~2mS) later, Generally, it is in the hundreds of k level. Based on this, in the operating range of the crystal oscillator, such as 8 to 24 MHz, the result of the variable part of the denominator is much less than 1 (such as 0.03 to 0.09), thus obtaining:

[0040] In summary, the transfer function is can be simplified to:

[0041] Through the simplified transfer function, it can be determined that the gain is approximately related to the ratio of the first capacitor C1 to the second capacitor C2. This allows the gain variation range of the gain network to be improved from -32% to 20% without the second capacitor C2 to 20% with the second capacitor C2 within the working range, even under different working conditions (such as voltage, temperature, and process deviation). Therefore, a smaller gain variation range is achieved through the gain structure, and the design complexity of the gain structure can be simplified, thereby ensuring the stability and reliability of the circuit.

[0042] In one embodiment, by simulating the clock signal circuit, the working amplitude range of the clock signal, that is, the working amplitude range input to the clock buffer, and the working frequency of the clock generation can be obtained. According to the working amplitude range and the working frequency, the values ​​of the first capacitor C1, the second capacitor C2, the resistor R1 and the size of the first transistor MN0 are set. These parameters can determine the transconductance The value of Fig. 9 The high-pass inflection point (i.e., the first inflection point) shown in FIG. 1 is a high-pass inflection point (i.e., the first inflection point). The smaller the size of the first transistor MN0, the faster its speed and the smaller its parasitic capacitance, so that Fig. 9 In practical applications, the values ​​of the first capacitor C1, the second capacitor C2, the resistor R1 and the size of the first transistor MN0 can be optimized by simulator parameter transformation, and each parameter is finally determined.

[0043] In one embodiment, in addition to implementing the gain bias part based on the N-type MOS tube bias and the resistor and capacitor network, the following can also be used: Fig.13 The P-type MOS tube + N-type MOS tube bias stage shown. The clock buffer is improved by adding the seventh and eighth transistors. The current mirror is composed of a single P-type MOS tube, the drain of the seventh transistor is connected to the output end of the first branch of the current mirror, the gate is connected to the gate of the first transistor MN0, and the source is connected to the drain of the first transistor MN0. The drain of the eighth transistor is connected to the output end of the second branch of the current mirror, the gate is connected to the gate of the second transistor MN1, and the source is connected to the drain of the second transistor MN1.

[0044] The key to gain is the transconductance ( ), which is the ratio of the change in output current to the change in input voltage. The larger the transconductance, the higher the gain. In the gain network, the role of the seventh and eighth transistors is to increase the transconductance, thereby increasing the gain.

[0045] The gate of the seventh transistor is connected to the gate of the first transistor MN0, which means that the gate-source voltage of the seventh transistor is determined by the working state of the first transistor MN0. When the first transistor MN0 receives a clock signal, the gate-source voltage of the seventh transistor will also change accordingly, thereby adjusting the conduction state of the seventh transistor. Since the source of the seventh transistor is connected to the drain of the first transistor MN0, the drain current of the seventh transistor will be equal to the drain current of the first transistor MN0. By adjusting the working state of the seventh transistor, the output current can be controlled, thereby improving the gain.

[0046] The gate of the eighth transistor is connected to the gate of the second transistor MN1, and the working principle is similar to that of the seventh transistor. When the second transistor MN1 receives a clock signal, the gate-source voltage of the eighth transistor will also change accordingly, adjusting the conduction state of the eighth transistor. The source of the eighth transistor is connected to the drain of the second transistor MN1, and the drain current of the eighth transistor will be equal to the drain current of the second transistor MN1. By adjusting the working state of the eighth transistor, the output current can be controlled, thereby further improving the gain. This design improves the gain, so that it can provide a higher output current under different working conditions.

[0047] It should be noted that the two different gain networks provided in the above two embodiments enable the clock buffer to amplify the clock signal according to the gain factor. In conjunction with the hysteresis comparator CMP of the next stage, the hysteresis comparator CMP can convert only the amplitude required for work into a square wave clock, thereby filtering out noise signals below a certain amplitude, and preventing the clock buffer from outputting noises of various frequencies and clock signals of various amplitudes, resulting in abnormal glitches or erroneous frequencies in the output square wave signal.

[0048] In one embodiment, in order to make the hysteresis comparator CMP pass only the signal within the working frequency and suppress the conversion of the out-of-band signal into a square wave signal, the amplitude range of the output of the hysteresis comparator CMP is determined by the gain coefficient. The threshold (upper and lower switching voltages) of the hysteresis comparator CMP is usually related to the amplitude of the clock signal and the gain coefficient. A larger gain makes the hysteresis window wider. In the process of processing the clock signal, the clock signal may contain high-frequency glitches or small-amplitude interference signals. A gain network is set in the clock buffer to amplify the clock signal. When the clock signal is interfered by a small amplitude of noise, if the gain is high enough, the input change caused by the noise is still not enough to break through the hysteresis window, so as not to trigger the flip of the comparator. This setting enables the hysteresis comparator CMP to effectively transmit low-amplitude noise signals, which can avoid unnecessary jumps in the output caused by these noises, and only respond to the real clock signal edge, so that the square wave signal output by the hysteresis comparator CMP does not contain these small-amplitude noise signals, thereby improving the stability of the clock signal.

[0049] In one embodiment, by setting the hysteresis voltage of the hysteresis comparator CMP, the hysteresis comparator CMP can invert the output for the required amplitude signal, while the signal with a smaller amplitude (such as noise) will not pass through, thereby ensuring the stability of the clock signal. Among them, the gain level of the gain network is determined, so that the peak-to-peak value of the signal after amplification by the gain network can be determined. On this basis, the noise amplitude to be filtered is determined, and the amplitude of the amplified noise signal is calculated by the gain level. The hysteresis voltage of the hysteresis comparator CMP is set to be greater than the amplitude of the amplified noise signal. Then, the hysteresis comparator CMP does not output the clock for the signal less than the hysteresis voltage, thereby filtering the low-amplitude noise in the clock signal, and realizing the amplitude filtering function.

[0050] Assuming that the clock signal (sine wave) is 60mV peak-to-peak ("mV peak-to-peak" is abbreviated as Vpp below), and the gain of the gain stage is 7dB, then after the gain stage, the waveform of the clock signal is amplified to about 134mVpp. If you need to filter noise below 60mVPP, such as Fig.14 As shown, Fig.14 The waveform processing diagram of the hysteresis comparator CMP is shown. The hysteresis voltage of the hysteresis comparator CMP needs to be designed to be greater than 134mV. For example, the hysteresis voltage is set to 150mV. In this way, the hysteresis comparator CMP will switch states only when the amplitude of the amplified clock signal exceeds 150mVpp. The 60mVpp noise signal does not reach 150mV after amplification and will not trigger the flipping of the hysteresis comparator CMP, ensuring that small signals (including noise) are shielded.

[0051] In this embodiment, the hysteresis voltage is set to be higher than the noise amplitude to ensure that only the valid signal is flipped and output as a square wave, and the noise does not cause false triggering, thereby ensuring the stability of the clock signal.

[0052] The present application also provides an application embodiment for implementing the above clock buffer design. The specific process includes: Step 1: Determine design specifications According to the actual simulation results of the clock generation circuit, the operating amplitude range of the input to the clock buffer is obtained (such as > 400mVpp). According to the working scenario of the circuit, the noise amplitude that needs to be filtered is obtained (such as < 60mVpp). The operating frequency range of the clock generation circuit is determined by the known design requirements, assuming a 4~24Mhz operating range.

[0053] Step 2: Set the values ​​of resistors and capacitors and the size of the MOS tube according to the design specifications.

[0054] (1) Since the operating frequency is determined, the transconductance is determined by setting the sizes of the first capacitor C1, the second capacitor C2, the resistor R1 and the first transistor MN0. According to the set specifications, the high-pass inflection point is designed to be less than 4Mhz, such as 400Khz. This design process can be tuned by simulator parameter transformation to determine various parameters.

[0055] (2) Setting the first transistor MN0 to a shorter length can make it faster and have a smaller parasitic capacitance. At the same time, the simulator scans the current flowing through the drain of the first transistor MN0 and extends the right inflection point in the spectrum to greater than 24 MHz.

[0056] (3) The gain of the waveform is mainly determined by the ratio of the first capacitor C1 to the second capacitor C2, and the typical gain is set to 5 dB.

[0057] After the above step 2, the gain stage design is completed, and PVT simulation is performed to verify the stability of the design, and finally the corresponding simulation results are obtained. PVT simulation refers to the comprehensive simulation of the process, voltage and temperature of the circuit to evaluate the performance and stability of the circuit under different conditions.

[0058] Step 3, reference voltage circuit design After the gain stage design is completed, the current mirror of the gain stage (the third transistor MP0 and the fifth transistor MP2) is connected to the first transistor MN0 and scaled down to save power consumption and ensure sufficient quantity to meet the matching requirements. The ratio is set to 4:1 to complete the matching design.

[0059] Step 4, hysteresis comparator CMP design After the gain stage design is completed, PVT simulation with clock signals of 80mVpp and 400mVpp is performed to output a composite signal (bufout) at the drain of the first transistor MN0 to obtain the actual working amplitude range. According to the simulation results, the hysteresis voltage range of the hysteresis comparator CMP is preliminarily determined as follows: the hysteresis voltage should be greater than the bufout amplitude range at 80mVpp and less than the bufout amplitude range at 400mVpp. In practical applications, the hysteresis comparator CMP can adopt a conventional cross-coupled pair structure, and adjust the size ratio of the MOS tube to meet the above hysteresis requirements, and perform PVT transient simulation (80mVpp and 400mVpp, frequency range of 4MHz to 24MHz combination). Fine-tune the ratio during the simulation to ensure that the functional requirements are met under all conditions.

[0060] Through the above steps, the design of the clock buffer is completed, including the design of the gain stage, reference voltage circuit and hysteresis comparator CMP, ensuring that the circuit operates stably under the specified working conditions and meets the design specifications.

[0061] In one embodiment, a clock module is provided, comprising a clock signal generating circuit and the above-mentioned clock buffer circuit.

[0062] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0063] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0064] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A clock buffer, characterized in that: It includes a first capacitor, a first transistor, a second transistor, a current mirror and a hysteresis comparator; One end of the first capacitor is connected to the clock signal, and the other end of the first capacitor inputs the alternating current of the clock signal into the gate of the first transistor (MN0); The current mirror comprises a first branch and a second branch composed of transistors, the input end of the first branch and the input end of the second branch are respectively connected to a working power supply; the output end of the first branch of the current mirror is connected to the drain of the first transistor and connected to the negative input end of the hysteresis comparator; the output end of the second branch of the current mirror is connected to the drain of the second transistor and connected to the positive input end of the hysteresis comparator; The gate and drain of the second transistor are short-circuited; the source of the first transistor and the source of the second transistor are grounded respectively; The output terminal of the hysteresis comparator outputs a clock signal; Among them, the negative input end of the hysteresis comparator is a composite signal; the positive input end of the hysteresis comparator is a reference voltage; the composite signal is generated by superimposing the DC bias voltage output by the first branch and the AC quantity output by the first transistor; the reference voltage is the same as the DC bias voltage.

2. The clock buffer according to claim 1, wherein: The clock buffer further includes a second capacitor and a resistor, wherein the second capacitor and the resistor are connected in parallel and connected across the gate and drain of the first transistor; wherein the gain coefficient is associated with the ratio of the first capacitor to the second capacitor.

3. The clock buffer according to claim 2, characterized in that: The amplitude range of the hysteresis comparator output is determined by the gain factor.

4. The clock buffer according to claim 3, characterized in that: The hysteresis voltage of the clock buffer is set to be greater than the amplitude of the noise amplified signal; the amplitude of the noise amplified signal is calculated by the noise signal and the gain coefficient.

5. The clock buffer according to claim 2, wherein: The values ​​of the first capacitor, the second capacitor, the resistor and the size of the first transistor are set according to the operating amplitude range of the clock signal and the operating frequency of the clock generating circuit.

6. The clock buffer according to claim 1, wherein: The first branch of the current mirror includes a third transistor, and the second branch of the current mirror includes a fourth transistor; wherein, The drain of the third transistor is the input end of the first branch, and the source of the third transistor is the output end of the first branch; the drain of the fourth transistor is the input end of the second branch, and the source of the fourth transistor is the output end of the second branch; the gates of the third transistor and the fourth transistor are connected to a first bias voltage.

7. The clock buffer according to claim 1, wherein: The first branch of the current mirror includes a third transistor and a fifth transistor, and the second branch of the current mirror includes a fourth transistor and a sixth transistor; wherein, The drain of the third transistor is the input end of the first branch, the gate of the third transistor is connected to the first bias voltage, the source of the third transistor is connected to the drain of the fifth transistor, the gate of the fifth transistor is connected to the second bias voltage, and the source of the fifth transistor is the output end of the first branch; The drain of the fourth transistor is the input end of the second branch, the gate of the fourth transistor is connected to the first bias voltage, the source of the fourth transistor is connected to the drain of the sixth transistor, the gate of the sixth transistor is connected to the second bias voltage, and the source of the sixth transistor is the output end of the second branch.

8. The clock buffer according to claim 2, wherein: The clock buffer further includes a seventh transistor and an eighth transistor; wherein, The drain of the seventh transistor is connected to the output end of the first branch of the current mirror, the gate of the seventh transistor is connected to the gate of the first transistor, and the source of the seventh transistor is connected to the drain of the first transistor; The drain of the eighth transistor is connected to the output end of the second branch of the current mirror, the gate of the eighth transistor is connected to the gate of the second transistor, and the source of the eighth transistor is connected to the drain of the second transistor.

9. The clock buffer according to claim 1, wherein: A width ratio of the first transistor to the second transistor satisfies N:1; a width ratio of the transistor in the first branch to the transistor in the second branch of the current mirror satisfies N:

1.

10. A clock module, characterized in that: The invention comprises a clock generating circuit and the clock buffer according to any one of claims 1 to 9.

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