Power-on reset circuit

Abstract

A power-on reset (POR) circuit includes a first jump detector circuit and a second jump detector circuit. The first jump detector circuit generates a reset signal indicative of a state of a supply voltage based on a jump node voltage ramped up when the supply voltage ramps up. When the jump node voltage exceeds a threshold, the reset signal is asserted. The second jump detector circuit generates a control signal based on the supply voltage and a reference voltage. The reference voltage is smaller than the power supply voltage until the power supply voltage drops obliquely. During a ramp-down of the supply voltage, the supply voltage drops below the reference voltage, and when the supply voltage is less than the reference voltage by a different threshold, the control signal is asserted. The asserted control signal causes the hopping node voltage to be changed such that the reset signal is de-asserted.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Indian Application No. 202341067186 filed on October 6, 2023, the contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic circuits, and more particularly, to a power-on reset circuit. Background Art

[0004] Integrated circuits (ICs) include various functional circuits that are critical to their operation. Such functional circuits require a power supply voltage above a predefined value to ensure accurate execution of the associated operations. Such predefined values ​​of the power supply voltage are called trip values. When the IC is powered on, the power supply voltage ramps up at different ramp rates before settling to a specific value. During the ramp-up period, if the functional circuit operates at a power supply voltage less than the trip value, an erroneous output may be generated, which may cause the IC to malfunction. Summary of the invention

[0005] According to one embodiment, a circuit includes:

[0006] A power-on reset (POR) circuit configured to generate a reset signal indicating a state of a power supply voltage, the POR circuit comprising:

[0007] A first trip detector circuit, comprising: (i) an input terminal configured to receive a trip node voltage of a trip node, wherein the trip node voltage ramps up based on a ramp up of the power supply voltage; and (ii) an output terminal configured to generate the reset signal based on the trip node voltage, such that during the ramp up of the power supply voltage, when the trip node voltage is less than a first threshold, the reset signal is de-asserted, and when the trip node voltage exceeds the first threshold, the reset signal transitions from a de-asserted state to an asserted state;

[0008] a reference generation circuit comprising an input configured to receive the supply voltage and an output configured to generate a reference voltage, wherein the reference voltage is a reduced version of the supply voltage during the ramp-up period and during a steady-state period of the supply voltage, and

[0009] wherein during at least a portion of the ramp-down of the supply voltage, the supply voltage drops below the reference voltage;

[0010] a second transition detector circuit coupled to the output terminal of the reference generating circuit and comprising an output terminal configured to generate a control signal based on the reference voltage and the power supply voltage so that during the ramp-down of the power supply voltage, when the power supply voltage is less than the reference voltage by a second threshold, the control signal transitions from the de-asserted state to the asserted state; and

[0011] A control circuit is coupled to the trip node and the second trip detector circuit and is configured to change the trip node voltage based on a transition of the control signal to cause the reset signal to transition from the asserted state to the deasserted state.

[0012] Illustratively, the POR circuit further includes a first diode circuit including a first end configured to receive the power supply voltage and a second end coupled to the trip node, and wherein the first diode circuit is configured to generate the trip node voltage at the second end, causing the trip node voltage to ramp up based on the ramp up of the power supply voltage and to be a reduced version of the power supply voltage until the trip node voltage exceeds the first threshold.

[0013] Illustratively, during the ramp-up of the supply voltage, the trip node voltage is equal to a difference between the supply voltage and a threshold voltage associated with the first diode circuit until the trip node voltage exceeds the first threshold.

[0014] Illustratively, during the ramp-up of the power supply voltage, the transition node voltage is less than the power supply voltage until the transition node voltage exceeds the first threshold, and wherein when the transition node voltage exceeds the first threshold, the transition node voltage is adjusted to be equal to the power supply voltage.

[0015] Example:

[0016] The POR circuit further includes a first control transistor, the first control transistor including (i) a first current terminal configured to receive the power supply voltage, (ii) a control terminal configured to receive an enable signal; and (iii) a second current terminal coupled to the trip node, the first control transistor being configured to control the trip node voltage so that when the first control transistor is activated, the trip node voltage is equal to the power supply voltage, the first control transistor is activated when the enable signal is asserted, and the enable signal is de-asserted when the trip node voltage is less than the first threshold and transitions from the de-asserted state to the asserted state when the trip node voltage exceeds the first threshold.

[0017] By way of example, the control circuit includes a second control transistor, the second control transistor including: (i) a first current terminal coupled to a low power supply voltage terminal; (ii) a control terminal coupled to the second jump detector circuit and configured to receive the control signal; and (iii) a second current terminal coupled to the jump node, wherein the second control transistor is configured to control the jump node voltage so that when the second control transistor is activated, the jump node voltage is pulled down to the voltage of the low power supply voltage terminal, and wherein the second control transistor is activated based on the assertion of the control signal.

[0018] Example:

[0019] The first trip detector circuit includes a first inverter configured to generate a first trigger signal based on the trip node voltage,

[0020] during the ramp-up of the power supply voltage, when the trip node voltage is less than the first threshold, the first trigger signal is de-asserted, and when the trip node voltage exceeds the first threshold, the first trigger signal transitions from the de-asserted state to the asserted state,

[0021] Based on the transition of the first trigger signal, the voltage of the transition node is adjusted to be equal to the power supply voltage,

[0022] During the steady state of the power supply voltage, the first trigger signal remains asserted and the trip node voltage remains equal to the power supply voltage, and

[0023] During the ramp-down of the power supply voltage, when the trip node voltage is pulled down to a voltage of a low power supply voltage terminal, the first trigger signal transitions from the asserted state to the deasserted state.

[0024] Illustratively, the first transition detector circuit further comprises:

[0025] a second inverter comprising: (i) an input terminal coupled to the output terminal of the first inverter and configured to receive the first trigger signal; and (ii) an output terminal configured to generate a first intermediate signal, the first intermediate signal being an inverted version of the first trigger signal; and

[0026] a third inverter comprising: (i) an input terminal coupled to the output terminal of the second inverter and configured to receive the first intermediate signal; and (ii) an output terminal configured to generate an enable signal, the enable signal being an inverted version of the first intermediate signal, wherein the enable signal is logically equivalent to the first trigger signal, and wherein based on the logic state of the enable signal, the trip node voltage is adjusted to be equal to the power supply voltage.

[0027] Illustratively, the first transition detector circuit further comprises a fourth inverter configured to generate the reset signal, the reset signal being an inverted version of the first trigger signal.

[0028] By way of example, the first inverter generates the first trigger signal at its output terminal, and the first inverter comprises:

[0029] a first high sense transistor comprising: (i) a first current terminal configured to receive the supply voltage; (ii) a control terminal configured to receive the trip node voltage; and (iii) a second current terminal; and

[0030] a second high detection transistor comprising: (i) a first current terminal coupled to the low power supply voltage terminal; (ii) a control terminal configured to receive the trip node voltage; and (iii) a second current terminal coupled to the second current terminal of the first high detection transistor at a first output node, wherein the first output node corresponds to the output terminal of the first inverter, and wherein the first threshold is a function of the power supply voltage, the threshold voltage of the first high detection transistor, and the threshold voltage of the second high detection transistor.

[0031] Example:

[0032] The POR circuit additionally includes a first control transistor including a first current terminal configured to receive the supply voltage and a second current terminal coupled to the trip node,

[0033] The control circuit includes a second control transistor, the second control transistor includes a first current terminal coupled to the low power supply voltage terminal and a second current terminal coupled to the trip node,

[0034] During the ramp-up of the power supply voltage, when the trip node voltage is less than the first threshold, the first control transistor and the second control transistor are deactivated, and when the trip node voltage exceeds the first threshold, the first control transistor is activated and configured to control the trip node voltage so that the trip node voltage is equal to the power supply voltage,

[0035] During the ramp-down of the power supply voltage, when the power supply voltage is less than the reference voltage by the second threshold, the second control transistor is activated, and

[0036] The driving strength of the second control transistor is greater than the driving strength of the first control transistor, and therefore, when the second control transistor is activated, the second control transistor is configured to control the trip node voltage so that the trip node voltage is pulled down to the voltage of the low power supply voltage terminal.

[0037] Example:

[0038] The reference generating circuit corresponds to a second diode circuit, the second diode circuit including (i) a first terminal configured to receive the power supply voltage and (ii) a second terminal coupled to the second trip detector circuit,

[0039] The POR circuit additionally includes a capacitor including a first electrode coupled to the second end of the second diode circuit at a reference node, and

[0040] The reference voltage is generated at the reference node.

[0041] By way of example, the second transition detector circuit comprises:

[0042] a first low detection transistor comprising: (i) a first current terminal coupled to the reference generating circuit and configured to receive the reference voltage; (ii) a control terminal configured to receive the power supply voltage; and (iii) a second current terminal; and

[0043] a second low sense transistor comprising: (i) a first current terminal coupled to a low supply voltage terminal; (ii) a control terminal configured to receive the supply voltage; and (iii) a second current terminal coupled to the second current terminal of the second low sense transistor at a second output node,

[0044] The first low detection transistor and the second low detection transistor are configured to generate a second trigger signal at the second output node,

[0045] During the ramp-up and the steady-state of the power supply voltage, (i) the power supply voltage is greater than the reference voltage, (ii) the first low detection transistor is deactivated and the second low detection transistor is activated, and (iii) the second trigger signal is deasserted,

[0046] During the ramp-down of the power supply voltage, the power supply voltage drops below the reference voltage, and when the power supply voltage is less than the reference voltage by the second threshold, the first low detection transistor is activated and the second low detection transistor is deactivated, and the second trigger signal transitions from the deasserted state to the asserted state, and

[0047] The control signal is logically equivalent to the second trigger signal.

[0048] Illustratively, the second threshold is a function of the power supply voltage, a threshold voltage of the first low detection transistor, and a threshold voltage of the second low detection transistor.

[0049] Illustratively, the second transition detector circuit further comprises:

[0050] a fifth inverter comprising: (i) an input terminal coupled to the second current terminal of the first low detection transistor and the second current terminal of the second low detection transistor and configured to receive the second trigger signal; and (ii) an output terminal configured to generate a second intermediate signal, the second intermediate signal being an inverted version of the second trigger signal; and

[0051] a sixth inverter comprising: (i) an input terminal coupled to the output terminal of the fifth inverter and configured to receive the second intermediate signal; and (ii) an output terminal configured to generate the control signal, which is an inverted version of the second intermediate signal.

[0052] Example:

[0053] The reset signal indicates the state of the power supply voltage so that

[0054] (i) during the ramp-up of the power supply voltage, when the power supply voltage is less than a transition high value, the reset signal is de-asserted, and when the power supply voltage exceeds the transition high value, the reset signal transitions from the de-asserted state to the asserted state,

[0055] (ii) during said steady state of said power supply voltage, said reset signal remains asserted, and

[0056] (iii) during the ramp-down of the power supply voltage, when the power supply voltage is greater than a transition low value, the reset signal remains asserted, and when the power supply voltage drops below the transition low value, the reset signal transitions from the asserted state to the de-asserted state, and

[0057] The trip high value corresponds to a value of the power supply voltage when the trip node voltage exceeds the first threshold, and the trip low value corresponds to a value of the power supply voltage when the power supply voltage is less than the reference voltage by the second threshold.

[0058] Illustratively, the transition high value is greater than the transition low value.

[0059] Illustratively, the circuit further includes a functional circuit coupled to the POR circuit and configured to receive the reset signal and perform one or more operations associated with the functional circuit based on the asserted state of the reset signal.

[0060] Illustratively, during the steady state of the power supply voltage, the current consumption of the POR circuit is zero.

[0061] According to an embodiment, a circuit includes:

[0062] A power-on reset (POR) circuit configured to generate a reset signal indicating a state of a power supply voltage, the POR circuit comprising:

[0063] a first diode circuit comprising: (i) a first terminal configured to receive the supply voltage; and (ii) a second terminal;

[0064] A first inverter comprising: (i) a power supply terminal configured to receive the power supply voltage; (ii) an input terminal coupled to the second terminal of the first diode circuit; and (iii) an output terminal configured to generate a first trigger signal;

[0065] a second diode circuit comprising: (i) a first terminal configured to receive the supply voltage; and (ii) a second terminal;

[0066] a first low sense transistor comprising: (i) a first current terminal coupled to the second terminal of the second diode circuit; (ii) a control terminal configured to receive the supply voltage; and (iii) a second current terminal;

[0067] a second low detection transistor comprising: (i) a first current terminal coupled to a low power supply voltage terminal; (ii) a control terminal configured to receive the power supply voltage; and (iii) a second current terminal coupled to the second current terminal of the first low detection transistor; and

[0068] A control transistor comprising: (i) a first current terminal, the first current terminal being coupled to the low power supply voltage terminal; (ii) a second current terminal, the second current terminal being coupled to the second terminal of the first diode circuit and the input terminal of the first inverter; and (ii) a control terminal, the control terminal being coupled to the second current terminal of the first low detection transistor, wherein the reset signal is an inverted version of the first trigger signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The following detailed description of embodiments of the present disclosure will be better understood when read in conjunction with the accompanying drawings. The present disclosure is illustrated by way of example and not limitation in the accompanying drawings, in which like numerals indicate similar elements.

[0070] Figure 1 A schematic block diagram showing an integrated circuit (IC) according to an embodiment of the present disclosure;

[0071] Figure 2 The embodiment according to the present disclosure is shown Figure 1 A schematic circuit diagram of a power-on reset (POR) circuit of an IC; and

[0072] Figure 3 2 is a timing diagram illustrating the operation of a POR circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0073] The detailed description of the accompanying drawings is intended to describe the embodiments of the present disclosure, and is not intended to represent the only form in which the present disclosure can be practiced. It should be understood that the same or equivalent functions can be implemented by different embodiments intended to be included in the spirit and scope of the present disclosure.

[0074] Overview:

[0075] Conventionally, the reset signal generated by the power-on reset (POR) circuit is used to indicate that the power supply voltage is higher than the jump value. For example, during the ramp-up of the power supply voltage, when the power supply voltage is less than the jump value, the reset signal is de-asserted (e.g., in a logic low state), and when the power supply voltage exceeds the jump value, the reset signal is changed from the de-asserted state to the asserted state (e.g., a logic high state). Similarly, during the ramp-down of the power supply voltage, when the power supply voltage drops below the jump value, the reset signal is changed to the de-asserted state. The jump values ​​during the ramp-up and ramp-down may be different. Therefore, the various components of the integrated circuit (IC) may be inoperable (e.g., may be in a standby mode) when the reset signal is de-asserted, and may be operable only when the reset signal is asserted. The POR circuit may include various transistors and inverters to enable the generation of a reset signal. Typically, in such a POR circuit, during the steady state of the power supply voltage, a low impedance path is formed between the power supply voltage and the ground terminal. In other words, such a POR circuit consumes a non-zero steady-state current, which results in an increase in static power consumption. Other POR circuits that aim to achieve zero power may have difficulty implementing trigger scenarios during both ramping up and ramping down of the supply voltage.

[0076] Various embodiments of the present disclosure disclose an IC including a POR circuit. The POR circuit may generate a reset signal indicating the state of a power supply voltage. The POR circuit may include a first diode circuit and a second diode circuit, a first jump detector circuit and a second jump detector circuit, and a control circuit. The first diode circuit and the second diode circuit generate a jump node voltage and a reference voltage based on the power supply voltage, respectively. The jump node voltage and the reference voltage are ramped up based on the ramp up of the power supply voltage and are reduced versions of the power supply voltage. The first jump detector circuit generates a reset signal based on the jump node voltage, and the second jump detector circuit generates a control signal based on the reference voltage and the power supply voltage. The control circuit changes the jump node voltage based on the control signal, thereby controlling the logic state of the reset signal.

[0077] When the IC is powered on, the transition node voltage and the reference voltage follow the power supply voltage and are less than the power supply voltage. In such cases, the first and second transition detector circuits are deactivated (e.g., not triggered). In other words, the reset signal and the control signal are deasserted. When the control signal is deasserted, the control circuit is deactivated (e.g., not triggered). The reset signal remains deasserted when the transition node voltage is less than the first threshold, and transitions from the deasserted state to the asserted state when the transition node voltage exceeds the first threshold (e.g., when the power supply voltage exceeds the transition high value). Therefore, the asserted state of the reset signal indicates that the power supply voltage is higher than a predefined level. In addition, when the transition node voltage exceeds the first threshold, the transition node voltage is adjusted to be equal to the power supply voltage. For the rest of the ramp-up and during the steady state of the power supply voltage, the transition node voltage remains equal to the power supply voltage, and the reset signal remains asserted. In addition, during the ramp-up and steady state of the power supply voltage, the reference voltage remains less than the power supply voltage, which causes the second transition detector circuit and then the control circuit to remain deactivated. During the ramp-down of the power supply voltage, the power supply voltage drops below the reference voltage. When the power supply voltage is less than the reference voltage by a second threshold value (e.g., when the power supply voltage drops below the transition low value), the second transition detector circuit is activated and generates a control signal in an asserted state. The asserted state of the control signal activates the control circuit, and the activated control circuit controls the transition node voltage so that the transition node voltage is pulled down to the ground voltage. Therefore, the reset signal transitions from the asserted state to the deasserted state.

[0078] Therefore, during the ramp-up of the power supply voltage, when the power supply voltage is less than the jump high value, the reset signal is de-asserted, and when the power supply voltage exceeds the jump high value, the reset signal transitions from the de-asserted state to the asserted state. For the rest of the ramp-up and during the steady state of the power supply voltage, the reset signal remains asserted. In addition, during the ramp-down of the power supply voltage, when the power supply voltage is greater than the jump low value, the reset signal remains asserted, and when the power supply voltage drops below the jump low value, the reset signal transitions from the asserted state to the de-asserted state. Therefore, the reset signal indicates the state of the power supply voltage. Therefore, the reset signal can be used by various functional circuits of the IC to perform associated operations.

[0079] Therefore, the POR circuit of some embodiments of the present disclosure utilizes two separate jump detector circuits to realize the detection of ramp-up and ramp-down triggering scenarios. The detection of the trigger point (especially the jump low value) in the present disclosure is different from the detection of the trigger point in some conventional POR circuits. In addition, during the steady state, all voltages and signals of the POR circuit are equal to the power supply voltage or the ground voltage. In other words, the low impedance path between the power supply voltage and the ground terminal is prevented during the steady state in the POR circuit of some embodiments of the present disclosure. Therefore, the POR circuit is prevented from consuming non-zero steady-state current. Therefore, the power consumption of the IC of some embodiments of the present disclosure is significantly less than the power consumption of the IC including some conventional POR circuits. Since the POR circuit of some embodiments of the present disclosure can detect both ramp-up and ramp-down triggering scenarios while avoiding consuming non-zero steady-state current, the POR circuit of some embodiments of the present disclosure is significantly more efficient and accurate than some conventional POR circuits.

[0080] Figure 1 1 is a schematic block diagram of an integrated circuit (IC) 100 according to an embodiment of the present disclosure. The IC 100 may include a power supply 102, a power-on reset (POR) circuit 104, and a functional circuit 106.

[0081] The power supply 102 may be configured to generate a power supply voltage VDD. In an example, the power supply voltage VDD is equal to 1.8 volts (V). However, in other embodiments, the power supply voltage VDD may have other values.

[0082] The POR circuit 104 may be coupled to the power supply 102 (e.g., a high power supply voltage terminal) and a ground terminal (e.g., a low power supply voltage terminal). The POR circuit 104 may be configured to receive a power supply voltage VDD from the power supply 102 and generate a reset signal RST that may indicate a state of the power supply voltage VDD. For example, during the ramp-up of the power supply voltage VDD, when the power supply voltage VDD is less than the transition high value, the reset signal RST is de-asserted (e.g., in a logic low state), and when the power supply voltage VDD exceeds the transition high value, the reset signal RST transitions from a de-asserted state to an asserted state (e.g., a logic high state). In addition, for the remainder of the ramp-up and during the steady state of the power supply voltage VDD, the reset signal RST remains asserted. In addition, during the ramp-down of the power supply voltage VDD, when the power supply voltage VDD is greater than the transition low value, the reset signal RST remains asserted, and when the power supply voltage VDD drops below the transition low value, the reset signal RST transitions from an asserted state to a de-asserted state.

[0083] The term "assertion" is used to mean placing a signal in an active state. Some signals may be asserted high signals, while some signals may be asserted low signals. In the case of an asserted high signal, the assertion of the signal corresponds to the signal being in a logical high state. Conversely, in the case of an asserted low signal, the assertion of the signal corresponds to the signal being in a logical low state. In the above example, the reset signal RST is an asserted high signal (e.g., the active state corresponds to a logical high state).

[0084] The jump high value and the jump low value do not change significantly at different ramp rates of the power supply voltage VDD. In an embodiment, the jump high value is greater than the jump low value. For example, the jump high value may be equal to 0.9V, and the jump low value may be equal to 0.7V. However, in other embodiments, the jump high value and the jump low value may be different.

[0085] Therefore, in the POR circuit 104, the trigger point (e.g., the transition high value and the transition low value) is detected during both the ramp-up and ramp-down of the power supply voltage VDD. In addition, during the steady state of the power supply voltage VDD, all voltages and signals of the POR circuit 104 are equal to the power supply voltage VDD or the ground voltage. Therefore, the POR circuit 104 is prevented from consuming a non-zero steady-state (e.g., static) current. In other words, during the steady state of the power supply voltage VDD, the current consumption of the POR circuit 104 is zero. Therefore, the POR circuit 104 is able to detect both the ramp-up and ramp-down trigger scenarios while avoiding consuming a non-zero steady-state current, which makes the POR circuit 104 efficient and accurate compared to some conventional POR circuits. Combined with Figure 2 and Figure 3 The POR circuit 104 is explained in detail.

[0086] The functional circuit 106 may be coupled to the power supply 102, the POR circuit 104, and the ground terminal. The functional circuit 106 may include a suitable circuit system that may be configured to perform one or more operations. For example, the functional circuit 106 may be configured to receive a power supply voltage VDD and a reset signal RST from the power supply 102 and the POR circuit 104, respectively. Based on the assertion state of the reset signal RST, the functional circuit 106 is further configured to perform one or more operations associated with the functional circuit 106. In addition, based on the de-assertion state of the reset signal RST, the functional circuit 106 may be configured to operate in a standby mode. Therefore, the reset signal RST ensures that the functional circuit 106 is operable only when the power supply voltage VDD is within a desired range (e.g., a range that does not hinder the operation of the functional circuit 106). Examples of the functional circuit 106 may include analog circuits, digital circuits, memory circuits, sensors, input / output circuits, processor circuits, communication circuits, or any combination thereof.

[0087] Functional circuit 106 is an exemplary functional circuit that can utilize reset signal RST for its operation. However, the scope of the present disclosure is not limited in this regard. In various other embodiments, reset signal RST can be utilized by various other functional circuits of IC 100 without departing from the scope of the present disclosure.

[0088] although Figure 1 All circuits are shown implemented on IC 100, but the scope of the present disclosure is not limited in this regard. In various other embodiments, some circuits may be external to IC 100. For example, in some embodiments, power supply 102 may be external to IC 100.

[0089] The scope of the present disclosure is not limited to the ground terminal being the low power supply voltage terminal. In other embodiments, the voltage of the low power supply voltage terminal may correspond to a non-zero value (eg, -1V, 1V, etc.).

[0090] Figure 2 A schematic circuit diagram of a POR circuit 104 according to an embodiment of the present disclosure is shown. The POR circuit 104 may include a first diode circuit 202, a first trip detector circuit 204, a first control transistor 206, a second control transistor 208, a second diode circuit 210, and a second trip detector circuit 212.

[0091] The first diode circuit 202 may be coupled to the power supply 102 and the first jump detector circuit 204. Examples of the first diode circuit 202 may include a diode, a diode-connected transistor, etc. In the embodiments described below, the first diode circuit 202 is a diode-connected transistor. Hereinafter, the first diode circuit 202 is referred to as "the first diode-connected transistor 202". However, in other embodiments, the first diode circuit 202 may be implemented with a diode or other types of diode circuits (not shown). In an embodiment, the first diode-connected transistor 202 corresponds to a p-channel metal oxide semiconductor (PMOS) transistor. The first diode-connected transistor 202 may include a first current terminal and a second current terminal and a control terminal. In the present disclosure, the first current terminal and the second current terminal of the transistor correspond to the source terminal and the drain terminal of the transistor, respectively, and the control terminal corresponds to the gate terminal of the transistor.

[0092] The source terminal of the first diode-connected transistor 202 may be coupled to the power supply 102 and may be configured to receive a power supply voltage VDD from the power supply 102. The drain terminal of the first diode-connected transistor 202 may be coupled to the gate terminal of the first diode-connected transistor 202, thereby generating a diode-connected transistor configuration. Thus, the source terminal of the first diode-connected transistor 202 may correspond to a first end of the first diode circuit 202, while the drain terminal and the gate terminal of the first diode-connected transistor 202 may correspond to a second end of the first diode circuit 202. The drain terminal of the first diode-connected transistor 202 may be additionally coupled to the first trip detector circuit 204, the first control transistor 206, and the second control transistor 208 at a trip node 213. Furthermore, the first diode-connected transistor 202 may be configured to generate a trip node voltage VTN at its drain terminal (e.g., at the trip node 213).

[0093] The transition node voltage VTN is ramped up based on the ramp up of the power supply voltage VDD and is a reduced version of the power supply voltage VDD (e.g., less than the power supply voltage VDD) until the power supply voltage VDD exceeds the transition high value. In an embodiment, the transition node voltage VTN is equal to the difference between the power supply voltage VDD and the threshold voltage of the first diode-connected transistor 202 until the power supply voltage VDD exceeds the transition high value. When the power supply voltage VDD exceeds the transition high value, the transition node voltage VTN is adjusted to be equal to the power supply voltage VDD. Such control of the transition node voltage VTN is performed by the first control transistor 206. The transition node voltage VTN remains equal to the power supply voltage VDD until the power supply voltage VDD drops below the transition low value. In such cases, the transition node voltage VTN can be pulled down to the ground terminal. Such control of the transition node voltage VTN is performed by the second control transistor 208.

[0094] The first jump detector circuit 204 may be coupled to the first diode-connected transistor 202 (e.g., the drain terminal of the first diode-connected transistor 202), the first control transistor 206 and the second control transistor 208 at the trip node 213, coupled to the power supply 102, the functional circuit 106 and the ground terminal. The first jump detector circuit 204 may be configured to receive the power supply voltage VDD and the trip node voltage VTN from the power supply 102 and the drain terminal of the first diode-connected transistor 202, respectively. Based on the power supply voltage VDD and the trip node voltage VTN, the first jump detector circuit 204 may be further configured to generate a reset signal RST. Therefore, the first jump detector circuit 204 may include an input terminal configured to receive the trip node voltage VTN and an output terminal configured to generate the reset signal RST. In addition, the first jump detector circuit 204 may be configured to provide the reset signal RST to the functional circuit 106. In order to achieve the generation of the reset signal RST, the first jump detector circuit 204 includes a first inverter 214 to a fourth inverter 220.

[0095] The first inverter 214 may be coupled to the first diode-connected transistor 202 (e.g., the drain terminal of the first diode-connected transistor 202), the power supply 102, and the ground terminal. The first inverter 214 may be configured to receive the power supply voltage VDD and the trip node voltage VTN from the power supply 102 and the drain terminal of the first diode-connected transistor 202, respectively, and generate the first trigger signal TRG1 based on the trip node voltage VTN and the power supply voltage VDD. The first trigger signal TRG1 is an asserted low signal. In the example, the first inverter 214 includes a high power supply terminal configured to receive the power supply voltage VDD, a low power supply terminal coupled to the ground terminal, an input terminal configured to receive the trip node voltage VTN, and an output terminal configured to generate the first trigger signal TRG1.

[0096] The first inverter 214 may include a first high detection transistor 222 and a second high detection transistor 224. In an embodiment, the first high detection transistor 222 corresponds to a PMOS transistor, and the second high detection transistor 224 corresponds to an n-channel metal oxide semiconductor (NMOS) transistor. Each of the first high detection transistor 222 and the second high detection transistor 224 includes a source terminal, a gate terminal, and a drain terminal. The source terminal and the gate terminal of the first high detection transistor 222 may be coupled to the power supply 102 and the drain terminal of the first diode-connected transistor 202, and may be configured to receive a power supply voltage VDD and a trip node voltage VTN from the power supply 102 and the drain terminal of the first diode-connected transistor 202, respectively. The source terminal and the gate terminal of the second high detection transistor 224 may be coupled to a ground terminal and a gate terminal of the first high detection transistor 222, respectively. Therefore, the gate terminal of the second high detection transistor 224 may be configured to receive the trip node voltage VTN. In addition, the drain terminal of the first high detection transistor 222 may be coupled to the drain terminal of the second high detection transistor 224 at the first output node 225. The first output node 225 corresponds to an output terminal of the first inverter 214. The first inverter 214 generates a first trigger signal TRG1 at an output terminal thereof.

[0097] During the ramp-up of the power supply voltage VDD, when the trip node voltage VTN is less than the first threshold, the first trigger signal TRG1 is de-asserted (e.g., in a logic high state). In other words, the trip node voltage VTN is equivalent to a logic '0', and therefore the output of the first inverter 214 (e.g., the first trigger signal TRG1) is a logic '1'. In addition, when the trip node voltage VTN exceeds the first threshold (e.g., equivalent to a logic '1'), the first trigger signal TRG1 transitions from a de-asserted state (e.g., a logic high state) to an asserted state (e.g., a logic low state). In this scenario, the first threshold corresponds to the trip voltage of the first inverter 214. Therefore, the first threshold is a function of the power supply voltage VDD, the threshold voltage of the first high detection transistor 222, and the threshold voltage of the second high detection transistor 224, as shown in the following equation (1):

[0098]

[0099] in,

[0100] Vtrip is the trip voltage of the first inverter 214,

[0101] Vthp is the threshold voltage of the first high detection transistor 222,

[0102] Vthn is the threshold voltage of the second high detection transistor 224,

[0103]

[0104] μ p is the mobility of the first high detection transistor 222,

[0105] C oxp is the oxide capacitance of the first high sense transistor 222,

[0106] is the aspect ratio of the first high detection transistor 222,

[0107] μ n is the mobility of the second highest detection transistor 224,

[0108] C oxn is the oxide capacitance of the second high sense transistor 224,

[0109] is the aspect ratio of the second high detection transistor 224 .

[0110] Therefore, the first threshold is also a function of the mobility, oxide capacitance, and aspect ratio of each of the first high detection transistor 222 and the second high detection transistor 224 .

[0111] Based on the transition of the first trigger signal TRG1 (e.g., based on the jump node voltage VTN exceeding the first threshold), the jump node voltage VTN is adjusted to be equal to the power supply voltage VDD. The following explains in detail the adjustment of the jump node voltage VTN based on the transition of the first trigger signal TRG1. For the rest of the ramp-up and during the steady state of the power supply voltage VDD, the first trigger signal TRG1 remains asserted, and the jump node voltage VTN remains equal to the power supply voltage VDD. In addition, during the ramp-down of the power supply voltage VDD, when the jump node voltage VTN is pulled down to the ground terminal, the first trigger signal TRG1 transitions from the asserted state to the deasserted state.

[0112] The second inverter 216 may be coupled to the first inverter 214 (e.g., the drain terminal of the first high detection transistor 222 and the second high detection transistor 224). The second inverter 216 may be configured to receive the first trigger signal TRG1 from the first inverter 214 and generate a first intermediate signal IM1, which is an inverted version of the first trigger signal TRG1. Therefore, the first intermediate signal IM1 is an asserted high signal. Therefore, the second inverter 216 may include an input terminal coupled to the output terminal of the first inverter 214 and an output terminal configured to generate the first intermediate signal IM1. Similarly, the third inverter 218 may be coupled to the second inverter 216 and may be configured to receive the first intermediate signal IM1 from the second inverter 216. The third inverter 218 may be further configured to generate an enable signal EN, which is an inverted version of the first intermediate signal IM1. Therefore, the third inverter 218 may include an input coupled to the output of the second inverter 216 and an output configured to generate an enable signal EN. Therefore, the enable signal EN is logically equivalent to the first trigger signal TRG1. In addition, the enable signal EN is an assertion low signal. Based on the logic state of the enable signal EN, the jump node voltage VTN is adjusted to be equal to the power supply voltage VDD, as explained in detail below. The fourth inverter 220 may be coupled to the third inverter 218, and may be configured to receive the enable signal EN from the third inverter 218. The fourth inverter 220 may be additionally configured to generate a reset signal RST, which is an inverted version of the enable signal EN. In other words, the reset signal RST is an inverted version of the first trigger signal TRG1. Therefore, the reset signal RST is an assertion high signal. Therefore, the fourth inverter 220 may include an input coupled to the output of the third inverter 218 and an output configured to generate the reset signal RST.

[0113] The second inverter 216 to the fourth inverter 220 may be similar in structure to Figure 2 The first inverter 214 shown, and the components of each of the second inverter 216 to the fourth inverter 220 are not shown in FIG. Figure 2 In order to avoid confusing the illustration. Figure 2 Although not shown in FIG. 1 , the second to fourth inverters 216 to 220 may be configured to receive a power supply voltage VDD and a ground voltage at a power supply terminal of each inverter to perform a corresponding inversion operation.

[0114] Therefore, during the ramp-up of the power supply voltage VDD, the transition node voltage VTN follows the power supply voltage VDD and is less than the power supply voltage VDD. When the transition node voltage VTN is less than the first threshold, the first trigger signal TRG1 is de-asserted (e.g., in a logic high state) and the reset signal RST is de-asserted (e.g., in a logic low state). In addition, when the transition node voltage VTN exceeds the first threshold during the ramp-up, the first trigger signal TRG1 transitions from a de-asserted state to an asserted state (e.g., a logic low state), and therefore, the reset signal RST transitions from a de-asserted state to an asserted state (e.g., a logic high state). Therefore, the transition high value corresponds to the value of the power supply voltage VDD when the transition node voltage VTN exceeds the first threshold. In other words, during the ramp-up of the power supply voltage VDD, the transition node voltage VTN is a reduced version of the power supply voltage VDD (e.g., equal to the difference between the power supply voltage VDD and the threshold voltage of the first diode-connected transistor 202) until the transition node voltage VTN exceeds the first threshold. Furthermore, when the trip node voltage VTN exceeds the first threshold, the trip node voltage VTN is adjusted to be equal to the power supply voltage VDD. Such adjustment of the trip node voltage VTN prevents a low impedance path from being generated between the power supply voltage VDD (eg, the power supply 102 ) and the ground terminal in the first trip detector circuit 204 .

[0115] To control the adjustment of the transition node voltage VTN, the first transition detector circuit 204 (e.g., the third inverter 218) generates an enable signal EN. During the ramp-up of the power supply voltage VDD, the enable signal EN is de-asserted (e.g., in a logic high state) when the transition node voltage VTN is less than the first threshold, and transitions from a de-asserted state to an asserted state (e.g., a logic low state) when the transition node voltage VTN exceeds the first threshold. For the rest of the ramp-up and during the steady state of the power supply voltage VDD, the enable signal EN remains asserted. In addition, during the ramp-down of the power supply voltage VDD, when the transition node voltage VTN is pulled down to the ground terminal, the enable signal EN transitions from an asserted state to a de-asserted state.

[0116] The first trip detector circuit 204 may be further configured to provide an enable signal EN to the first control transistor 206. In an embodiment, the first control transistor 206 corresponds to a PMOS transistor. The first control transistor 206 may include a source terminal, a gate terminal, and a drain terminal. The source terminal and the gate terminal of the first control transistor 206 may be coupled to the power supply 102 and the first trip detector circuit 204 (e.g., the third inverter 218), and may be configured to receive the power supply voltage VDD and the enable signal EN from the power supply 102 and the first trip detector circuit 204, respectively. In addition, the drain terminal of the first control transistor 206 may be coupled to the first trip detector circuit 204 (e.g., the gate terminals of the first high detection transistor 222 and the second high detection transistor 224) and the drain terminal of the first diode-connected transistor 202 at the trip node 213.

[0117] The enable signal EN controls the first control transistor 206 such that the first control transistor 206 is activated and deactivated when the enable signal EN is asserted and deasserted, respectively. Thus, during the ramp-up of the power supply voltage VDD, when the trip node voltage VTN is less than the first threshold (e.g., when the enable signal EN is deasserted), the first control transistor 206 is deactivated. When the trip node voltage VTN exceeds the first threshold (e.g., when the enable signal EN transitions to an asserted state), the first control transistor 206 is activated and may be configured to control the trip node voltage VTN such that the trip node voltage VTN is equal to the power supply voltage VDD. For the remainder of the ramp-up and during the steady state of the power supply voltage VDD, the trip node voltage VTN remains equal to the power supply voltage VDD, the first trigger signal TRG1 remains asserted (e.g., in a logic low state), the enable signal EN remains asserted (e.g., in a logic low state), and the reset signal RST remains asserted (e.g., in a logic high state). In addition, during the ramp-down of the power supply voltage VDD, when the power supply voltage VDD drops below the trip low value, the trip node voltage VTN is pulled down to the ground terminal. In such a case, the first trigger signal TRG1 is de-asserted (e.g., in a logic high state), the enable signal EN is de-asserted (e.g., in a logic high state), and the reset signal RST is de-asserted (e.g., in a logic low state).

[0118] The second control transistor 208 (also corresponding to and referred to as "control circuit 208") may be configured to control the trip node voltage VTN during the ramp-down of the power supply voltage VDD. In an embodiment, the second control transistor 208 corresponds to an NMOS transistor. The second control transistor 208 may include a source terminal, a gate terminal, and a drain terminal. The source terminal of the second control transistor 208 may be coupled to the ground terminal, and the drain terminal of the second control transistor 208 may be coupled to the drain terminals of the first diode-connected transistor 202 and the first control transistor 206 and the gate terminals of the first high detection transistor 222 and the second high detection transistor 224 at the trip node 213. The gate terminal of the second control transistor 208 may be configured to receive a control signal CS that controls the operation of the second control transistor 208. The control signal CS is an asserted high signal. The control signal CS controls the second control transistor 208 so that the second control transistor 208 is activated and deactivated when the control signal CS is asserted and deasserted, respectively.

[0119] During the ramp-up and steady-state of the power supply voltage VDD, the control signal CS remains deasserted, and therefore, the second control transistor 208 remains deactivated. During the ramp-down of the power supply voltage, when the power supply voltage VDD drops below the transition low value, the control signal CS transitions from the deasserted state to the asserted state. Therefore, the second control transistor 208 is activated and can be configured to control the transition node voltage VTN so that the transition node voltage VTN is pulled down to the ground terminal. In an embodiment, the driving strength of the second control transistor 208 is greater than the driving strength of the first control transistor 206, and therefore, although the first control transistor 206 is activated, the transition node voltage VTN is pulled down to the ground terminal.

[0120] When the trip node voltage VTN is pulled down to the ground terminal, each of the first trigger signal TRG1 and the enable signal EN changes from the asserted state to the deasserted state. Therefore, the first control transistor 206 is deactivated. In addition, the reset signal RST changes from the asserted state to the deasserted state. Therefore, the reset signal RST provides an accurate indication of the state of the power supply voltage VDD.

[0121] In the POR circuit 104 , generation of the control signal CS is enabled by the second diode circuit 210 and the second trip detector circuit 212 .

[0122] The second diode circuit 210 can be coupled to the power supply 102 and the second jump detector circuit 212. Examples of the second diode circuit 210 may include a diode, a diode-connected transistor, etc. In the embodiments described below, the second diode circuit 210 is a diode-connected transistor. Hereinafter, the second diode circuit 210 is referred to as "the second diode-connected transistor 210". However, in other embodiments, the second diode circuit 210 can be implemented with a diode or other types of diode circuits (not shown). In an embodiment, the second diode-connected transistor 210 corresponds to a PMOS transistor. The second diode-connected transistor 210 may include a source terminal, a gate terminal, and a drain terminal.

[0123] The source terminal of the second diode-connected transistor 210 may be coupled to the power supply 102 and may be configured to receive the power supply voltage VDD from the power supply 102. The drain terminal of the second diode-connected transistor 210 may be coupled to the gate terminal of the second diode-connected transistor 210, thereby generating a diode-connected transistor configuration. Therefore, the source terminal of the second diode-connected transistor 210 may correspond to the first terminal of the second diode circuit 210, and the drain terminal and the gate terminal of the second diode-connected transistor 210 may correspond to the second terminal of the second diode circuit 210. The drain terminal of the second diode-connected transistor 210 may be additionally coupled to the second trip detector circuit 212 at the reference node 226. In addition, the second diode-connected transistor 210 may be configured to generate a reference voltage VREF at the drain terminal of the second diode-connected transistor 210 (e.g., at the reference node 226). In the present disclosure, the second diode-connected transistor 210 may correspond to and may also be referred to as a "reference generating circuit 210". Therefore, the reference generation circuit 210 may include an input terminal configured to receive the power supply voltage VDD and an output terminal configured to generate the reference voltage VREF.

[0124] During the ramp-up and steady-state of the power supply voltage VDD, the reference voltage VREF ramps up based on the ramp-up of the power supply voltage VDD and is a reduced version of the power supply voltage VDD (e.g., less than the power supply voltage VDD). In an embodiment, during the ramp-up and steady-state of the power supply voltage VDD, the reference voltage VREF is equal to the difference between the power supply voltage VDD and the threshold voltage of the second diode-connected transistor 210. Therefore, before the power supply voltage VDD ramps down, the reference voltage VREF stabilizes at a value less than the power supply voltage VDD. In an embodiment, the POR circuit 104 may include a capacitor 227 coupled between the drain terminal of the second diode-connected transistor 210 and the ground terminal. For example, the capacitor 227 may include a first electrode coupled to the drain terminal of the second diode-connected transistor 210 at the reference node 226 and a second electrode coupled to the ground terminal. The capacitor 227 may store a stable value of the reference voltage VREF at the end of the steady-state of the power supply voltage VDD.

[0125] During the ramp-down of the power supply voltage VDD, the power supply voltage VDD decreases while the reference voltage VREF (e.g., the voltage at the drain terminal of the second diode-connected transistor 210) is maintained by the capacitor 227. In other words, at least within a portion of the ramp-down of the power supply voltage VDD, the power supply voltage VDD drops below the reference voltage VREF. The reduction of the power supply voltage VDD and the maintenance of the reference voltage VREF cause the second diode-connected transistor 210 to be deactivated. In this scenario, when the power supply voltage VDD is less than the reference voltage VREF by a second threshold, the second transition detector circuit 212 is activated (e.g., triggered). Therefore, the transition low value corresponds to the value of the power supply voltage VDD when the power supply voltage VDD drops below the reference voltage VREF second threshold. In such a case, the maintained reference voltage VREF is used to transition the state of the control signal CS.

[0126] The second jump detector circuit 212 may be coupled to the second diode-connected transistor 210 (e.g., the drain terminal of the second diode-connected transistor 210) at a reference node 226, coupled to the power supply 102, the second control transistor 208 (e.g., the gate terminal of the second control transistor 208), and the ground terminal. The second jump detector circuit 212 may be configured to receive the power supply voltage VDD and the reference voltage VREF from the power supply 102 and the drain terminal of the second diode-connected transistor 210, respectively. Based on the power supply voltage VDD and the reference voltage VREF, the second jump detector circuit 212 may be further configured to generate a control signal CS. Therefore, the second jump detector circuit 212 may include an input terminal configured to receive the power supply voltage VDD and an output terminal configured to generate the control signal CS. In addition, the second jump detector circuit 212 may be configured to provide the control signal CS to the gate terminal of the second control transistor 208. To be able to generate the control signal CS, the second transition detector circuit 212 may include a first low detection transistor 228 and a second low detection transistor 230 , a fifth inverter 232 and a sixth inverter 234 .

[0127] The first low detection transistor 228 and the second low detection transistor 230 enable detection of a trip low trigger point of the power supply voltage VDD. In an embodiment, the first low detection transistor 228 corresponds to a PMOS transistor, and the second low detection transistor 230 corresponds to an NMOS transistor. Each of the first low detection transistor 228 and the second low detection transistor 230 may include a source terminal, a gate terminal, and a drain terminal. The source terminal and the gate terminal of the first low detection transistor 228 may be coupled to the drain terminal of the second diode-connected transistor 210 and the power supply 102, and may be configured to receive a reference voltage VREF and a power supply voltage VDD from the drain terminal of the second diode-connected transistor 210 and the power supply 102, respectively. The source terminal and the gate terminal of the second low detection transistor 230 may be coupled to the ground terminal and the gate terminal of the first low detection transistor 228, respectively. Therefore, the gate terminal of the second low detection transistor 230 may be configured to receive the power supply voltage VDD. In addition, the drain terminal of the first low detection transistor 228 may be coupled to the drain terminal of the second low detection transistor 230 at the second output node 235. The first low detection transistor 228 and the second low detection transistor 230 may be configured to generate a second trigger signal TRG2 at a second output node 235. The second trigger signal TRG2 is an asserted high signal. The first low detection transistor 228 and the second low detection transistor 230 thus constitute a seventh inverter having a high power supply terminal configured to receive a reference voltage VREF, a low power supply terminal coupled to a ground terminal, an input terminal configured to receive a power supply voltage VDD, and an output terminal configured to generate the second trigger signal TRG2.

[0128] During the ramp-up and steady-state of the power supply voltage VDD, the power supply voltage VDD is greater than the reference voltage VREF. Therefore, the first low detection transistor 228 is deactivated and the second low detection transistor 230 is activated (for example, when the power supply voltage VDD is greater than the threshold voltage of the second low detection transistor 230). Therefore, the second trigger signal TRG2 is de-asserted (for example, in a logic low state). In addition, during the ramp-down of the power supply voltage VDD, the power supply voltage VDD drops below the reference voltage VREF (for example, the voltage stored in the capacitor 227). When the power supply voltage VDD is less than the reference voltage VREF by a second threshold, the first low detection transistor 228 is activated and the second low detection transistor 230 is deactivated. Therefore, the second trigger signal TRG2 transitions from a de-asserted state to an asserted state (for example, a logic high state). In this scenario, the second threshold corresponds to the trip voltage of the seventh inverter. Therefore, in a similar manner as described above in equation (1), the second threshold is a function of the power supply voltage VDD, the threshold voltage of the first low detection transistor 228, and the threshold voltage of the second low detection transistor 230. In other words, the second threshold corresponds to a voltage difference between the reference voltage VREF and the power supply voltage VDD, which is sufficient to make the driving strength of the first low detection transistor 228 greater than the driving strength of the second low detection transistor 230, thereby enabling the second trigger signal TRG2 to be pulled up to the asserted state.

[0129] The fifth inverter 232 may be coupled to the drain terminal of the first low detection transistor 228 and the second low detection transistor 230 at the second output node 235. The fifth inverter 232 may be configured to receive the second trigger signal TRG2 from the drain terminal of the first low detection transistor 228 and the second low detection transistor 230, and generate a second intermediate signal IM2, which is an inverted version of the second trigger signal TRG2. Therefore, the second intermediate signal IM2 is an asserted low signal. Therefore, the fifth inverter 232 may include an input terminal coupled to the output terminal of the seventh inverter and an output terminal configured to generate the second intermediate signal IM2. The sixth inverter 234 may be coupled to the fifth inverter 232, and may be configured to receive the second intermediate signal IM2 from the fifth inverter 232. In addition, the sixth inverter 234 may be configured to generate a control signal CS, which is an inverted version of the second intermediate signal IM2. The control signal CS is therefore logically equivalent to the second trigger signal TRG2. Therefore, the sixth inverter 234 may include an input terminal coupled to the output terminal of the fifth inverter 232 and an output terminal configured to generate the control signal CS.

[0130] The fifth inverter 232 and the sixth inverter 234 may be similar in structure to Figure 2The first inverter 214 shown, and the components of each of the fifth inverter 232 and the sixth inverter 234 are not shown in FIG. Figure 2 In order to avoid confusing the illustration. Figure 2 Although not shown in FIG. 1 , the fifth inverter 232 and the sixth inverter 234 may be configured to receive the power supply voltage VDD and the ground voltage at the power supply terminal of each inverter to perform corresponding inversion operations.

[0131] Therefore, during the ramp-up and steady-state of the power supply voltage VDD, the reference voltage VREF follows the power supply voltage VDD and is less than the power supply voltage VDD. Therefore, the control signal CS remains deasserted. During the ramp-down of the power supply voltage VDD, the power supply voltage VDD drops below the reference voltage VREF. When the power supply voltage VDD is less than the reference voltage VREF by a second threshold, the second trigger signal TRG2 then controls the signal CS to transition from a deasserted state to an asserted state. Based on the assertion of the control signal CS, the second control transistor 208 (e.g., the control circuit 208) can be configured to change the jump node voltage VTN (e.g., pull the jump node voltage VTN down to the ground terminal) so that the reset signal RST transitions from the asserted state to the deasserted state.

[0132] Combination Figure 3 The operation of the POR circuit 104 is explained in detail.

[0133] The scope of the present disclosure is not limited to the first and second transition detector circuits 204 and 212 implemented in the manner described above. In various other embodiments, the first and second transition detector circuits 204 and 212 may be implemented using different or additional components without departing from the scope of the present disclosure.

[0134] although Figure 2 Described using transistors as control circuits and diode-connected transistors as reference generation circuits, but the scope of the present disclosure is not limited thereto. In various other embodiments, different or additional components may be used to implement the control circuit and the reference generation circuit without departing from the scope of the present disclosure.

[0135] Figure 3 A timing diagram 300 is shown illustrating the operation of the POR circuit 104 according to an embodiment of the present disclosure.

[0136] At time point T0, IC 100 is powered on. During time period T0-T1, power supply voltage VDD ramps up. Since the transition node voltage VTN and reference voltage VREF follow power supply voltage VDD and are reduced versions of power supply voltage VDD, the transition node voltage VTN and reference voltage VREF ramp up during time period T0-T1 and are less than power supply voltage VDD. The transition node voltage VTN is less than the first threshold, and therefore the first trigger signal TRG1 and then the enable signal EN are in a logic high state. Therefore, the first control transistor 206 is deactivated. In addition, when the reference voltage VREF is less than the power supply voltage VDD, the second trigger signal TRG2 and then the control signal CS are in a logic low state. Therefore, the second control transistor 208 is deactivated. In addition, the reset signal RST is deasserted.

[0137] At time point T1, the transition node voltage VTN exceeds the first threshold. In other words, the power supply voltage VDD exceeds the transition high value at time point T1. In addition, at time point T1, the enable signal EN transitions from a logic high state to a logic low state, and therefore, the reset signal RST transitions from a logic low state to a logic high state. The reference voltage VREF remains less than the power supply voltage VDD, and therefore the control signal CS remains in a logic low state. In addition, when the enable signal EN transitions to a logic low state, the first control transistor 206 is activated, and the transition node voltage VTN is adjusted to be equal to the power supply voltage VDD.

[0138] During the time period T1-T2, the transition node voltage VTN remains equal to the power supply voltage VDD, while the reference voltage VREF follows and is less than the power supply voltage VDD. Therefore, the pulse signal EN and the control signal CS remain in a logic low state, and the reset signal RST remains in a logic high state. In the timing diagram 300, the reset signal RST in a logic high state is indicated as following the power supply voltage VDD. However, the scope of the present disclosure is not limited to this.

[0139] At time point T2, the power supply voltage VDD starts to ramp down. During the time period T2-T3, when the power supply voltage VDD decreases, the reference voltage VREF is maintained by the capacitor 227. In other words, the power supply voltage VDD drops below the reference voltage VREF. During the time period T2-T3, the difference between the power supply voltage VDD and the reference voltage VREF is not enough to activate the first low detection transistor 228. Therefore, the control signal CS remains in a logic low state. In addition, the enable signal EN remains in a logic low state, and the reset signal RST remains in a logic high state.

[0140] At time point T3, the power supply voltage VDD is less than the reference voltage VREF by a second threshold. In other words, the power supply voltage VDD drops below the transition low value at time point T3. In addition, at time point T3, the first low detection transistor 228 is activated and the second low detection transistor 230 is deactivated. Therefore, the control signal CS transitions to a logic high state, thereby activating the second control transistor 208. Therefore, the transition node voltage VTN is pulled down to the ground terminal. In response, the enable signal EN transitions to a logic high state, and therefore, the reset signal RST transitions to a logic low state.

[0141] During time period T3 - T4 , the supply voltage VDD ramps down to ground, and IC 100 shuts down.

[0142] As shown in timing diagram 300, the trip high value is greater than the trip low value, thereby providing hysteresis in POR circuit 104. Different trip high and trip low values ​​may be achieved by controlling the size of the various transistors of POR circuit 104.

[0143] Therefore, in some embodiments of the present disclosure, the POR circuit 104 utilizes two separate trip detector circuits (e.g., the first trip detector circuit 204 and the second trip detector circuit 212) to implement detection of ramp-up and ramp-down trigger scenarios. Detecting a low trigger point (e.g., a trip low value) using a combination of the second diode-connected transistor 210 and the second trip detector circuit 212 distinguishes the POR circuit 104 from some conventional POR circuits that utilize different techniques to implement the detection of a trip low trigger point. In addition, during the steady state of the power supply voltage VDD, all voltages and signals of the POR circuit 104 are equal to the power supply voltage VDD or the ground voltage. In other words, a low impedance path between the power supply voltage VDD (e.g., the power supply 102) and the ground terminal is prevented in the POR circuit 104 during the steady state. Therefore, the POR circuit 104 is prevented from consuming a non-zero steady-state current. Therefore, the power consumption of the IC 100 is significantly less than the power consumption of ICs that include some conventional POR circuits. In addition, the POR circuit 104 includes several inverters and transistors to enable the generation of the reset signal RST, and is therefore not area intensive. Since the POR circuit 104 can detect both ramp-up and ramp-down triggering scenarios while avoiding consuming non-zero steady-state current, the POR circuit 104 is significantly more efficient and accurate than some conventional POR circuits.

[0144] In an embodiment of the present disclosure, an IC 100 is disclosed. The IC 100 may include a POR circuit 104 that may be configured to generate a reset signal RST. The reset signal RST indicates the state of the power supply voltage VDD. The POR circuit 104 may include a first jump detector circuit 204, a reference generation circuit 210, a second jump detector circuit 212, and a control circuit 208. The first jump detector circuit 204 may include an input terminal configured to receive a jump node voltage VTN of a jump node 213. The jump node voltage VTN ramps up based on the ramping of the power supply voltage VDD. In addition, the first jump detector circuit 204 may include an output terminal configured to generate a reset signal RST based on the jump node voltage VTN. During the ramping of the power supply voltage VDD, the reset signal RST is de-asserted when the jump node voltage VTN is less than a first threshold, and the reset signal RST transitions from a de-asserted state to an asserted state when the jump node voltage VTN exceeds the first threshold. The reference generation circuit 210 may include an input terminal configured to receive a power supply voltage VDD and an output terminal configured to generate a reference voltage VREF. During the ramp-up and steady-state period of the power supply voltage VDD, the reference voltage VREF is a reduced version of the power supply voltage VDD. In addition, during at least a portion of the ramp-down period of the power supply voltage VDD, the power supply voltage VDD drops below the reference voltage VREF. The second jump detector circuit 212 may be coupled to the output terminal of the reference generation circuit 210. The second jump detector circuit 212 may include an output terminal configured to generate a control signal CS based on the reference voltage VREF and the power supply voltage VDD. During the ramp-down period of the power supply voltage VDD, when the power supply voltage VDD is less than the reference voltage VREF by a second threshold, the control signal CS transitions from a deasserted state to an asserted state. The control circuit may be coupled to a jump node 213 and the second jump detector circuit 212. Based on the transition of the control signal CS, the control circuit 208 may be configured to change the jump node voltage VTN so that the reset signal RST transitions from an asserted state to a deasserted state.

[0145] In another embodiment of the present disclosure, an IC 100 is disclosed. The IC 100 may include a POR circuit 104 that may be configured to generate a reset signal RST. The reset signal RST indicates the state of a power supply voltage VDD. The POR circuit 104 may include a first diode circuit 202, a first inverter 214, a second diode circuit 210, a first low detection transistor 228, a second low detection transistor 230, and a second control transistor 208. Each of the first diode circuit 202 and the second diode circuit 210 may include a first terminal and a second terminal. Each of the first low detection transistor 228, the second low detection transistor 230, and the second control transistor 208 may include a first current terminal (e.g., a source terminal), a control terminal (e.g., a gate terminal), and a second current terminal (e.g., a drain terminal). The first terminal of each of the first diode circuit 202 and the second diode circuit 210 may be configured to receive the power supply voltage VDD. The first inverter 214 may include a first power supply terminal (e.g., a high power supply terminal) configured to receive a power supply voltage VDD, an input terminal coupled to the second terminal of the first diode circuit 202, and an output terminal configured to generate a first trigger signal TRG1. The first current terminals of the first low detection transistor 228 and the second low detection transistor 230 may be coupled to the second current terminal and the low power supply voltage terminal of the second diode circuit 210, respectively. The control terminals of the first low detection transistor 228 and the second low detection transistor 230 may be configured to receive the power supply voltage VDD. In addition, the second current terminal of the first low detection transistor 228 may be coupled to the second current terminal of the second low detection transistor 230. The second current terminal of the second control transistor 208 may be coupled to the second current terminal of the first diode circuit 202. In addition, the control terminal of the second control transistor 208 may be coupled to the second current terminal of the first low detection transistor 228 through the fifth inverter 232 and the sixth inverter 234. The reset signal RST is an inverted version of the first trigger signal TRG1.

[0146] In some embodiments, the POR circuit 104 may further include a first diode circuit 202, which may include a first end and a second end. The first end of the first diode circuit 202 may be configured to receive the power supply voltage VDD. In addition, the second end of the first diode circuit 202 may be coupled to the trip node 213. The first diode circuit 202 may be configured to generate a trip node voltage VTN at its second end. The trip node voltage VTN ramps up based on the ramp up of the power supply voltage VDD and is a reduced version of the power supply voltage VDD until the trip node voltage VTN exceeds the first threshold.

[0147] In some embodiments, during the ramp-up of the power supply voltage VDD, the trip node voltage VTN is equal to the difference between the power supply voltage VDD and a threshold voltage associated with the first diode circuit 202 (e.g., the threshold voltage of the first diode-connected transistor 202) until the trip node voltage VTN exceeds the first threshold.

[0148] In some embodiments, during the ramp-up of the power supply voltage VDD, the trip node voltage VTN is less than the power supply voltage VDD until the trip node voltage VTN exceeds a first threshold. When the trip node voltage VTN exceeds the first threshold, the trip node voltage VTN is adjusted to be equal to the power supply voltage VDD.

[0149] In some embodiments, the POR circuit 104 may further include a first control transistor 206, which includes a first current terminal and a second current terminal and a control terminal. The first current terminal and the control terminal of the first control transistor 206 may be configured to receive a power supply voltage VDD and an enable signal EN, respectively. In addition, the second current terminal of the first control transistor 206 may be coupled to a transition node 213. The first control transistor 206 may be configured to control a transition node voltage VTN so that when the first control transistor 206 is activated, the transition node voltage VTN is equal to the power supply voltage VDD. When the enable signal EN is asserted, the first control transistor 206 may be activated. The enable signal EN may be de-asserted when the transition node voltage VTN is less than a first threshold, and may be changed from a de-asserted state to an asserted state when the transition node voltage VTN exceeds the first threshold.

[0150] In some embodiments, the control circuit 208 may include a second control transistor 208, which includes a first current terminal and a second current terminal and a control terminal. The first current terminal and the second current terminal of the second control transistor 208 may be coupled to the low power supply voltage terminal and the trip node 213, respectively. In addition, the control terminal of the second control transistor 208 may be coupled to the second trip detector circuit 212 and may be configured to receive a control signal CS from the second trip detector circuit 212. The second control transistor 208 may be configured to control the trip node voltage VTN so that when the second control transistor 208 is activated, the trip node voltage VTN is pulled down to the voltage of the low power supply voltage terminal. The second control transistor 208 is activated based on the assertion of the control signal CS.

[0151] In some embodiments, the first jump detector circuit 204 may include a first inverter 214 that can be configured to generate a first trigger signal TRG1 based on a jump node voltage VTN. During the ramp-up period of the power supply voltage VDD, when the jump node voltage VTN is less than the first threshold, the first trigger signal TRG1 is de-asserted, and when the jump node voltage VTN exceeds the first threshold, the first trigger signal TRG1 transitions from a de-asserted state to an asserted state. Based on the transition of the first trigger signal TRG1, the jump node voltage VTN is adjusted to be equal to the power supply voltage VDD. During the steady state period of the power supply voltage VDD, the first trigger signal TRG1 remains asserted, and the jump node voltage VTN remains equal to the power supply voltage VDD. During the ramp-down period of the power supply voltage VDD, when the jump node voltage VTN is pulled down to the ground terminal, the first trigger signal TRG1 transitions from an asserted state to a de-asserted state.

[0152] In some embodiments, the first transition detector circuit 204 may further include a second inverter 216 and a third inverter 218. The second inverter 216 may include: (i) an input terminal coupled to the output terminal of the first inverter 214 and configured to receive the first trigger signal TRG1; and (ii) an output terminal configured to generate a first intermediate signal IM1, which is an inverted version of the first trigger signal TRG1. The third inverter 218 may include: (i) an input terminal coupled to the output terminal of the second inverter 216 and configured to receive the first intermediate signal IM1; and (ii) an output terminal configured to generate an enable signal EN, which is an inverted version of the first intermediate signal IM1. Therefore, the enable signal EN is logically equivalent to the first trigger signal TRG1. Based on the logic state of the enable signal EN, the transition node voltage VTN is adjusted to be equal to the power supply voltage VDD.

[0153] In some embodiments, the first transition detector circuit 204 may further include a fourth inverter 220 , which may be configured to generate a reset signal RST that is an inverted version of the first trigger signal TRG1 .

[0154] In some embodiments, the first inverter 214 generates a first trigger signal TRG1 at its output terminal. The first inverter 214 may include a first high detection transistor 222 and a second high detection transistor 224, each including a first current terminal and a second current terminal and a control terminal. The first current terminal of the first high detection transistor 222 may be configured to receive a power supply voltage VDD, and the first current terminal of the second high detection transistor 224 may be coupled to a low power supply voltage terminal. The control terminals of the first high detection transistor 222 and the second high detection transistor 224 may be configured to receive a trip node voltage VTN. In addition, the second current terminal of the first high detection transistor 222 may be coupled to the second current terminal of the second high detection transistor 224 at a first output node 225. The first output node 225 corresponds to the output terminal of the first inverter 214. The first threshold may be a function of the power supply voltage VDD, the threshold voltage of the first high detection transistor 222, and the threshold voltage of the second high detection transistor 224.

[0155] In some embodiments, during the ramp-up of the power supply voltage VDD, when the trip node voltage VTN is less than the first threshold, the first control transistor 206 and the second control transistor 208 are deactivated. In addition, when the trip node voltage VTN exceeds the first threshold, the first control transistor 206 is activated and can be configured to control the trip node voltage VTN so that the trip node voltage VTN is equal to the power supply voltage VDD. During the ramp-down of the power supply voltage VDD, when the power supply voltage VDD is less than the reference voltage VREF by a second threshold, the second control transistor 208 is activated. The driving strength of the second control transistor 208 is greater than the driving strength of the first control transistor 206, and therefore, when the second control transistor 208 is activated, the second control transistor 208 can be configured to control the trip node voltage VTN so that the trip node voltage VTN is pulled down to the voltage of the low power supply voltage terminal.

[0156] In some embodiments, reference generation circuit 210 includes second diode circuit 210. Second diode circuit 210 includes a first terminal configured to receive power supply voltage VDD and a second terminal coupled to a second trip detector circuit. POR circuit 104 additionally includes capacitor 227. Capacitor 227 includes a first electrode coupled to the second terminal of second diode circuit 210 at reference node 226. Reference voltage VREF is generated at reference node 226.

[0157] In some embodiments, the second transition detector circuit 212 may include a first low detection transistor 228 and a second low detection transistor 230 each including a first current terminal and a second current terminal and a control terminal. The first current terminal of the first low detection transistor 228 may be configured to receive a reference voltage VREF, and the first current terminal of the second low detection transistor 230 may be coupled to a low power supply voltage terminal. The control terminals of the first low detection transistor 228 and the second low detection transistor 230 may be configured to receive a power supply voltage VDD. The second current terminal of the first low detection transistor 228 may be coupled to the second current terminal of the second low detection transistor 230 at a second output node 235. The first low detection transistor 228 and the second low detection transistor 230 are configured to generate a second trigger signal TRG2 at the second output node 235. During the ramp-up and steady-state of the power supply voltage VDD, the power supply voltage VDD is greater than the reference voltage VREF, the first low detection transistor 228 is deactivated and the second low detection transistor 230 is activated, and the second trigger signal TRG2 is deasserted. In addition, during the ramp-down of the power supply voltage VDD, the power supply voltage VDD drops below the reference voltage VREF. When the power supply voltage VDD is less than the reference voltage VREF by a second threshold, the first low detection transistor 228 is activated and the second low detection transistor 230 is deactivated, and the second trigger signal TRG2 transitions from the deasserted state to the asserted state. The control signal CS is logically equivalent to the second trigger signal TRG2.

[0158] In some embodiments, the second threshold is a function of the power supply voltage VDD, the threshold voltage of the first low detection transistor 228 , and the threshold voltage of the second low detection transistor 230 .

[0159] In some embodiments, the second transition detector circuit 212 may further include a fifth inverter 232 and a sixth inverter 234. The fifth inverter 232 may include an input terminal coupled to the second terminals of the first low detection transistor 228 and the second low detection transistor 230 and configured to receive the second trigger signal TRG2; and an output terminal configured to generate a second intermediate signal IM2, which is an inverted version of the second trigger signal TRG2. The sixth inverter 234 may include an input terminal coupled to the output terminal of the fifth inverter 232 and configured to receive the second intermediate signal IM2; and an output terminal configured to generate a control signal CS, which is an inverted version of the second intermediate signal IM2.

[0160] In some embodiments, during the ramp-up of the power supply voltage VDD, when the power supply voltage VDD is less than the jump high value, the reset signal RST is de-asserted, and when the power supply voltage VDD exceeds the jump high value, the reset signal RST changes from the de-asserted state to the asserted state. During the steady state of the power supply voltage VDD, the reset signal RST remains asserted. In addition, during the ramp-down of the power supply voltage VDD, when the power supply voltage VDD is greater than the jump low value, the reset signal RST remains asserted, and when the power supply voltage VDD drops below the jump low value, the reset signal RST changes from the asserted state to the de-asserted state. Therefore, the reset signal RST indicates the state of the power supply voltage VDD. The jump high value corresponds to the value of the power supply voltage VDD when the jump node voltage VTN exceeds the first threshold, and the jump low value corresponds to the value of the power supply voltage VDD when the power supply voltage VDD is less than the reference voltage VREF by a second threshold.

[0161] In some embodiments, the transition high value is greater than the transition low value.

[0162] In some embodiments, IC 100 may additionally include functional circuit 106 that may be coupled to POR circuit 104. Functional circuit 106 may be configured to receive reset signal RST from POR circuit 104 and perform one or more operations associated therewith based on the assertion state of reset signal RST.

[0163] In some embodiments, during the steady state of the power supply voltage VDD, the current consumption of the POR circuit 104 is zero.

[0164] Although various embodiments of the present disclosure have been shown and described, it should be clear that the present disclosure is not limited to these embodiments. Without departing from the spirit and scope of the present disclosure described in the claims, many modifications, changes, variations, substitutions and equivalents will be apparent to those skilled in the art. In addition, unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the time or other priority ordering of such elements.

Claims

1. A circuit, characterized in that: include: A power-on reset (POR) circuit configured to generate a reset signal indicating a state of a power supply voltage, the POR circuit comprising: A first trip detector circuit, comprising: (i) an input terminal configured to receive a trip node voltage of a trip node, wherein the trip node voltage ramps up based on a ramp up of the power supply voltage; and (ii) an output terminal configured to generate the reset signal based on the trip node voltage, such that during the ramp up of the power supply voltage, when the trip node voltage is less than a first threshold, the reset signal is de-asserted, and when the trip node voltage exceeds the first threshold, the reset signal transitions from a de-asserted state to an asserted state; a reference generation circuit comprising an input configured to receive the supply voltage and an output configured to generate a reference voltage, wherein the reference voltage is a reduced version of the supply voltage during the ramp-up and steady-state period of the supply voltage, and wherein the supply voltage drops below the reference voltage during at least a portion of the ramp-down of the supply voltage; a second transition detector circuit coupled to the output terminal of the reference generating circuit and comprising an output terminal configured to generate a control signal based on the reference voltage and the power supply voltage so that during the ramp-down of the power supply voltage, when the power supply voltage is less than the reference voltage by a second threshold, the control signal transitions from the de-asserted state to the asserted state; and A control circuit is coupled to the trip node and the second trip detector circuit and is configured to change the trip node voltage based on a transition of the control signal to cause the reset signal to transition from the asserted state to the deasserted state.

2. The circuit according to claim 1, characterized in that The POR circuit additionally includes a first diode circuit including a first end configured to receive the power supply voltage and a second end coupled to the trip node, and wherein the first diode circuit is configured to generate the trip node voltage at the second end, causing the trip node voltage to ramp up based on the ramping of the power supply voltage and to be a reduced version of the power supply voltage until the trip node voltage exceeds the first threshold.

3. The circuit according to claim 1, characterized in that The POR circuit further includes a first control transistor including (i) a first current terminal configured to receive the power supply voltage, (ii) a control terminal configured to receive an enable signal; and (iii) a second current terminal coupled to the trip node, The first control transistor is configured to control the trip node voltage so that when the first control transistor is activated, the trip node voltage is equal to the power supply voltage, When the enable signal is asserted, the first control transistor is activated, and The enable signal is de-asserted when the trip node voltage is less than the first threshold, and transitions from the de-asserted state to the asserted state when the trip node voltage exceeds the first threshold.

4. The circuit according to claim 1, characterized in that The control circuit includes a second control transistor, the second control transistor including: (i) a first current terminal, which is coupled to the low power supply voltage terminal; (ii) a control terminal, which is coupled to the second trip detector circuit and is configured to receive the control signal; and (iii) a second current terminal, which is coupled to the trip node, wherein the second control transistor is configured to control the trip node voltage so that when the second control transistor is activated, the trip node voltage is pulled down to the voltage of the low power supply voltage terminal, and wherein the second control transistor is activated based on the assertion of the control signal.

5. The circuit according to claim 1, characterized in that The first trip detector circuit includes a first inverter configured to generate a first trigger signal based on the trip node voltage, during the ramp-up of the power supply voltage, when the trip node voltage is less than the first threshold, the first trigger signal is de-asserted, and when the trip node voltage exceeds the first threshold, the first trigger signal transitions from the de-asserted state to the asserted state, Based on the transition of the first trigger signal, the voltage of the transition node is adjusted to be equal to the power supply voltage, During the steady state of the power supply voltage, the first trigger signal remains asserted and the trip node voltage remains equal to the power supply voltage, and During the ramp-down of the power supply voltage, when the trip node voltage is pulled down to a voltage of a low power supply voltage terminal, the first trigger signal transitions from the asserted state to the deasserted state.

6. The circuit according to claim 5, characterized in that The first transition detector circuit additionally comprises: a second inverter comprising: (i) an input terminal coupled to the output terminal of the first inverter and configured to receive the first trigger signal; and (ii) an output terminal configured to generate a first intermediate signal, the first intermediate signal being an inverted version of the first trigger signal; and a third inverter comprising: (i) an input terminal coupled to the output terminal of the second inverter and configured to receive the first intermediate signal; and (ii) an output terminal configured to generate an enable signal, the enable signal being an inverted version of the first intermediate signal, wherein the enable signal is logically equivalent to the first trigger signal, and wherein based on the logic state of the enable signal, the trip node voltage is adjusted to be equal to the power supply voltage.

7. The circuit according to claim 1, characterized in that The POR circuit additionally includes a first control transistor including a first current terminal configured to receive the supply voltage and a second current terminal coupled to the trip node, The control circuit includes a second control transistor, the second control transistor includes a first current terminal coupled to the low power supply voltage terminal and a second current terminal coupled to the trip node, During the ramp-up of the power supply voltage, when the trip node voltage is less than the first threshold, the first control transistor and the second control transistor are deactivated, and when the trip node voltage exceeds the first threshold, the first control transistor is activated and configured to control the trip node voltage so that the trip node voltage is equal to the power supply voltage, During the ramp-down of the power supply voltage, when the power supply voltage is less than the reference voltage by the second threshold, the second control transistor is activated, and The driving strength of the second control transistor is greater than the driving strength of the first control transistor, and therefore, when the second control transistor is activated, the second control transistor is configured to control the trip node voltage so that the trip node voltage is pulled down to the voltage of the low power supply voltage terminal.

8. The circuit according to claim 1, characterized in that The second transition detector circuit comprises: a first low detection transistor comprising: (i) a first current terminal coupled to the reference generating circuit and configured to receive the reference voltage; (ii) a control terminal configured to receive the power supply voltage; and (iii) a second current terminal; and a second low sense transistor comprising: (i) a first current terminal coupled to a low supply voltage terminal; (ii) a control terminal configured to receive the supply voltage; and (iii) a second current terminal coupled to the second current terminal of the second low sense transistor at a second output node, The first low detection transistor and the second low detection transistor are configured to generate a second trigger signal at the second output node, During the ramp-up and the steady-state of the power supply voltage, (i) the power supply voltage is greater than the reference voltage, (ii) the first low detection transistor is deactivated and the second low detection transistor is activated, and (iii) the second trigger signal is deasserted, During the ramp-down of the power supply voltage, the power supply voltage drops below the reference voltage, and when the power supply voltage is less than the reference voltage by the second threshold, the first low detection transistor is activated and the second low detection transistor is deactivated, and the second trigger signal transitions from the deasserted state to the asserted state, and The control signal is logically equivalent to the second trigger signal.

9. The circuit according to claim 1, characterized in that The reset signal indicates the state of the power supply voltage so that (i) during the ramp-up of the power supply voltage, when the power supply voltage is less than a transition high value, the reset signal is de-asserted, and when the power supply voltage exceeds the transition high value, the reset signal transitions from the de-asserted state to the asserted state, (ii) during said steady state of said power supply voltage, said reset signal remains asserted, and (iii) during the ramp-down of the power supply voltage, when the power supply voltage is greater than a transition low value, the reset signal remains asserted, and when the power supply voltage drops below the transition low value, the reset signal transitions from the asserted state to the de-asserted state, and The trip high value corresponds to a value of the power supply voltage when the trip node voltage exceeds the first threshold, and the trip low value corresponds to a value of the power supply voltage when the power supply voltage is less than the reference voltage by the second threshold.

10. A circuit, characterized in that: include: A power-on reset (POR) circuit configured to generate a reset signal indicating a state of a power supply voltage, the POR circuit comprising: a first diode circuit comprising: (i) a first terminal configured to receive the supply voltage; and (ii) a second terminal; A first inverter comprising: (i) a power supply terminal configured to receive the power supply voltage; (ii) an input terminal coupled to the second terminal of the first diode circuit; and (iii) an output terminal configured to generate a first trigger signal; a second diode circuit comprising: (i) a first terminal configured to receive the supply voltage; and (ii) a second terminal; a first low sense transistor comprising: (i) a first current terminal coupled to the second terminal of the second diode circuit; (ii) a control terminal configured to receive the supply voltage; and (iii) a second current terminal; a second low detection transistor comprising: (i) a first current terminal coupled to a low power supply voltage terminal; (ii) a control terminal configured to receive the power supply voltage; and (iii) a second current terminal coupled to the second current terminal of the first low detection transistor; and a control transistor comprising: (i) a first current terminal coupled to the low power supply voltage terminal; (ii) a second current terminal coupled to the second terminal of the first diode circuit and the input terminal of the first inverter; and (ii) a control terminal coupled to the second current terminal of the first low sense transistor, wherein the reset signal is an inverted version of the first trigger signal.

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