Instrument forced shutdown circuit and instrument

Abstract

The invention discloses an instrument forced shutdown circuit and an instrument, and relates to the field of circuit protection. Wherein a first input pin and a second input pin of the OR gate chip U1 are respectively connected with a first key KEY1 and a second key KEY2; a first input pin and a second input pin of the NOR gate chip U2 are respectively connected with an output pin of the OR gate chip U1 and a third key KEY3; the KEY1, the KEY2 and the KEY3 are three different keys on the instrument and meter; an output pin of the NOR gate chip U2 is connected with a base electrode of a triode Q1 through a resistor R1; the collector of the triode Q1 is connected with the base of the triode Q2; the collector electrode of the triode Q2 is connected with the grid electrode of the PMOS tube U3 through a resistor R5; the source electrode of the PMOS transistor U3 is connected with the positive electrode of the battery, and the drain electrode of the PMOS transistor U3 is connected with the power supply circuit of the microcontroller. On the basis that the appearance structure of the instrument is not changed, the function of immediately cutting off power when the key is pressed down can be achieved, and the risk of mistaken touch does not exist.

Description

Technical Field

[0001] The present application relates to the technical field of circuit protection, and in particular to an instrument forced shutdown circuit and the instrument. Background Art

[0002] Existing battery-powered instruments and meters contain microcontroller units (MCU) working devices. If there is a problem with the working program, there is a risk of freezing. At this time, the battery power can only be disconnected to restore to normal. However, the batteries in such instruments and meters are often not easy to remove. When the MCU freezes, the software shutdown will not respond. At this time, the shutdown operation cannot be achieved. You can only wait for the battery to run out of power and shut down automatically or disassemble the machine to cut off the power. This method is extremely unfriendly to users. The existing solution is to add an additional hardware switch to force power off. This method will change the appearance and structure of the instrument, and it is easy to touch it by mistake if you are not careful. Another solution is to use the integral delay method of the hardware circuit. This method requires pressing the button for a long time, generally up to tens of seconds, which is not friendly to the user's patience. Summary of the invention

[0003] In view of the problems existing in the above prior art, the purpose of this application is to provide an instrument forced shutdown circuit and an instrument, which can realize the power-off function of pressing a button immediately without changing the appearance and structure of the instrument, and there is no risk of accidental touch.

[0004] To achieve the above objectives, this application provides the following solutions.

[0005] On the one hand, the present application provides an instrument forced shutdown circuit, including: an OR gate chip U1, a NOR gate chip U2, a resistor R1, a resistor R2, a transistor Q1, a transistor Q2, a PMOS tube U3, a resistor R3, a resistor R4, a resistor R5, a resistor R6 and a capacitor C1; The first input pin of the OR gate chip U1 is connected to the first key KEY1; the second input pin of the OR gate chip U1 is connected to the second key KEY2; the output pin of the OR gate chip U1 is connected to the first input pin of the NOR gate chip U2; the second input pin of the NOR gate chip U2 is connected to the third key KEY3; the output pin of the NOR gate chip U2 is connected to one end of the resistor R1; the other end of the resistor R1 is respectively connected to the base of the transistor Q1 and one end of the resistor R2; the other end of the resistor R2 and the emitter of the transistor Q1 are grounded; the collector of the transistor Q1 is respectively connected to one end of the resistor R3, one end of the resistor R4 and the base of the transistor Q2 The other end of the resistor R3 and the emitter of the transistor Q2 are grounded; the collector of the transistor Q2 is connected to one end of the resistor R5; the other end of the resistor R5 is respectively connected to one end of the resistor R6, one end of the capacitor C1 and the gate of the PMOS tube U3; the other end of the resistor R4, the other end of the resistor R6, the other end of the capacitor C1 and the source of the PMOS tube U3 are all connected to the positive electrode of the battery in the instrument; the negative electrode of the battery is grounded; the drain of the PMOS tube U3 is connected to the power supply circuit of the microcontroller in the instrument; the first button KEY1, the second button KEY2 and the third button KEY3 are three different buttons on the instrument.

[0006] Optionally, the first key KEY1, the second key KEY2 or the third key KEY3 is at a low level when pressed.

[0007] Optionally, when the first key KEY1 and the second key KEY2 are pressed simultaneously, the output pin of the OR gate chip U1 outputs a low level; otherwise, the output pin of the OR gate chip U1 outputs a high level.

[0008] Optionally, when the first key KEY1, the second key KEY2 and the third key KEY3 are pressed simultaneously, the output pin of the NOR gate chip U2 outputs a high level; otherwise, the output pin of the NOR gate chip U2 outputs a low level.

[0009] Optionally, when the output pin of the NOR gate chip U2 outputs a high level, the transistor Q1 is turned on, the transistor Q2 is turned off, and the PMOS tube U3 is turned off; otherwise, the PMOS tube U3 is turned on.

[0010] Optionally, the instrument forced shutdown circuit also includes: a fuse F1; the other end of the resistor R4, the other end of the resistor R6, the other end of the capacitor C1 and the source of the PMOS tube U3 are all connected to the positive electrode of the battery through the fuse F1.

[0011] Optionally, the OR gate chip U1 and the NOR gate chip U2 are both powered by a 3.3V voltage.

[0012] Optionally, the instrument forced shutdown circuit further includes: a capacitor C3; a power pin of the OR gate chip U1 is grounded through the capacitor C3.

[0013] Optionally, the instrument forced shutdown circuit further includes: a capacitor C2; and a power pin of the NOR gate chip U2 is grounded through the capacitor C2.

[0014] On the other hand, the present application also provides an instrument, which is powered by a battery and includes the instrument forced shutdown circuit.

[0015] According to the specific embodiments provided in this application, this application discloses the following technical effects: In the instrumentation forced shutdown circuit provided in the present application, the first button KEY1, the second button KEY2 and the third button KEY3 are three different buttons built into the instrumentation, so there is no need to add additional buttons to the instrumentation, and it is a hidden design of button combination, which does not affect the weight and appearance of the original instrumentation. The combination design of three buttons requires that the three buttons be pressed at the same time to complete the shutdown function, so there is no problem of accidental touch, which improves the safety of use. Pressing the three buttons at the same time can achieve an immediate forced shutdown, which is neither inconvenient to operate due to too many combination buttons, nor does it require the user to wait for dozens of seconds to shut down, greatly shortening the shutdown waiting time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 This is the circuit connection diagram of the instrument forced shutdown circuit. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] The purpose of this application is to propose an instrument forced shutdown circuit and an instrument, which can realize the power-off function of pressing a button without changing the appearance and structure of the instrument, and there is no risk of accidental touch.

[0020] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0021] In an exemplary embodiment, the present application provides a forced shutdown circuit for an instrument. Figure 1 As shown, the instrument forced shutdown circuit includes: an OR gate chip U1, a NOR gate chip U2, a resistor R1, a resistor R2, a transistor Q1, a transistor Q2, a PMOS tube U3, a resistor R3, a resistor R4, a resistor R5, a resistor R6 and a capacitor C1.

[0022] Among them, the first input pin of the OR gate chip U1 is connected to the first key KEY1. The second input pin of the OR gate chip U1 is connected to the second key KEY2. The output pin of the OR gate chip U1 is connected to the first input pin of the NOR gate chip U2. The second input pin of the NOR gate chip U2 is connected to the third key KEY3. The output pin of the NOR gate chip U2 is connected to one end of the resistor R1. The other end of the resistor R1 is respectively connected to the base of the transistor Q1 and one end of the resistor R2. The other end of the resistor R2 and the emitter of the transistor Q1 are grounded. The collector of the transistor Q1 is respectively connected to one end of the resistor R3, one end of the resistor R4 and the base of the transistor Q2. The other end of the resistor R3 and the emitter of the transistor Q2 are grounded. The collector of the transistor Q2 is connected to one end of the resistor R5. The other end of the resistor R5 is respectively connected to one end of the resistor R6, one end of the capacitor C1 and the gate of the PMOS tube U3. The other end of the resistor R4, the other end of the resistor R6, the other end of the capacitor C1 and the source of the PMOS tube U3 are all connected to the positive electrode of the battery in the instrument. The negative electrode of the battery is grounded. The drain of the PMOS tube U3 is connected to the power supply circuit of the microcontroller in the instrument. The first key KEY1, the second key KEY2 and the third key KEY3 are three different keys on the instrument.

[0023] When the first key KEY1 , the second key KEY2 or the third key KEY3 is pressed, it is at a low level.

[0024] When the first key KEY1 and the second key KEY2 are pressed simultaneously, the output pin of the OR gate chip U1 outputs a low level; otherwise, the output pin of the OR gate chip U1 outputs a high level.

[0025] When the first key KEY1 , the second key KEY2 and the third key KEY3 are pressed simultaneously, the output pin of the NOR gate chip U2 outputs a high level; otherwise, the output pin of the NOR gate chip U2 outputs a low level.

[0026] When the output pin of the NOR gate chip U2 outputs a high level, the transistor Q1 is turned on, the transistor Q2 is turned off, and the PMOS tube U3 is turned off; otherwise, the PMOS tube U3 is turned on.

[0027] In an exemplary embodiment, the instrument forced shutdown circuit further includes: a fuse F1. In this exemplary embodiment, the other end of the resistor R4, the other end of the resistor R6, the other end of the capacitor C1, and the source of the PMOS tube U3 are all connected to the positive electrode of the battery through the fuse F1. The fuse F1 is used for short-circuit protection of subsequent circuits.

[0028] In an exemplary embodiment, the instrument forced shutdown circuit further includes: a battery connection terminal J1. The battery connection terminal J1 includes three ports, wherein port 1 is connected to one end of the fuse F1 for introducing a positive power supply signal VBAT of the battery. Port 2 of the battery connection terminal J1 is connected to an NTC port of the battery for introducing a temperature signal NTC of the battery. Port 3 of the battery connection terminal J1 is grounded.

[0029] In an exemplary embodiment, the battery may be two lithium batteries, and the voltage of the positive power supply signal VBAT is 8.4V.

[0030] The PMOS tube U3 can use the HSBB2627 chip, which includes three electrodes and 8 pins, of which pins 1, 2, and 3 are source pins S, and the source pin S is connected to the other end of the fuse F1. Pin 4 of the HSBB2627 chip is the gate pin G, and the gate pin G is respectively connected to the other end of the resistor R5, one end of the resistor R6, and one end of the capacitor C1. Pins 5, 6, 7, and 8 of the HSBB2627 chip are all drain pins D, and the drain pin D is connected to the power supply circuit of the MCU. VBAT_PWR is the power supply signal of the MCU.

[0031] The OR gate chip U1 can use the SN74AHC1G32DBVR chip. Pin 1 of the SN74AHC1G32DBVR chip serves as the first input pin of the OR gate chip U1, which is used to connect the first key KEY1, and its input signal is recorded as A. Pin 2 of the SN74AHC1G32DBVR chip serves as the second input pin of the OR gate chip U1, which is used to connect the second key KEY2, and its input signal is recorded as B. Pin 3 of the SN74AHC1G32DBVR chip is a ground pin (recorded as GND) for grounding. Pin 4 of the SN74AHC1G32DBVR chip serves as the output pin of the OR gate chip U1, and its output signal is recorded as Y. Pin 5 of the OR gate chip U1 is a power pin (recorded as VCC), which is used to connect a 3.3V voltage for power supply.

[0032] In an exemplary embodiment, the instrument forced shutdown circuit further includes: a capacitor C3; and a power pin of the OR gate chip U1 is grounded through the capacitor C3.

[0033] The OR gate chip U1 is used to perform a logical OR operation on the input signals A and B of the first key KEY1 and the second key KEY2, and output the result through the output signal Y. The OR gate logic used by the OR gate chip U1 is shown in Table 1 below.

[0034] Table 1 OR gate logic of OR gate chip U1

[0035] The NOR gate chip U2 can use the SN74AHC1G02DBVR chip. Pin 1 of the SN74AHC1G02DBVR chip serves as the first input pin of the NOR gate chip U2, and its input signal is recorded as A, which is used to connect the output pin of the OR gate chip U1. Pin 2 of the SN74AHC1G02DBVR chip serves as the second input pin of the NOR gate chip U2, and is used to connect the third key KEY3, and its input signal is recorded as B. Pin 3 of the SN74AHC1G02DBVR chip is a ground pin (recorded as GND) for grounding. Pin 4 of the SN74AHC1G02DBVR chip serves as the output pin of the NOR gate chip U2, and its output signal is recorded as Y. Pin 5 of the NOR gate chip U2 is a power pin (recorded as VCC), which is used to connect a 3.3V voltage for power supply.

[0036] In an exemplary embodiment, the instrument forced shutdown circuit further includes: a capacitor C2; the power pin of the NOR gate chip U2 is grounded through the capacitor C2. The capacitor C2 and the capacitor C3 are filter capacitors of the device.

[0037] The NOR gate chip U2 is used to perform logical NOR on the output signal of the OR gate chip U1 and the input signals A and B of the second key KEY2, and output the result through the output signal Y. The NOR gate logic used by the NOR gate chip U2 is shown in Table 2 below.

[0038] Table 2 NOR gate logic of NOR gate chip U2

[0039] In an exemplary embodiment, the transistor Q1 and the transistor Q2 may be of the type 2N5551. The transistor Q1 comprises three pins, the base of which is respectively connected to the other end of the resistor R1 and one end of the resistor R2, the emitter of which is connected to the power ground, and the collector of which is connected to one end of the resistor R3, one end of the resistor R4 and the base of the transistor Q2. The transistor Q1 is used to isolate the battery input and drive the subsequent transistor Q2.

[0040] The transistor Q2 also includes three pins, the base of which is connected to one end of the resistor R3, one end of the resistor R4 and the collector of the transistor Q1, the emitter of which is connected to the power ground, and the collector of which is connected to one end of the resistor R5. The transistor Q2 is used to drive the PMOS tube U3.

[0041] The resistors R3, R4, R5, R6, transistors Q1 and Q2 are used together to ensure the gate-source (GS) voltage of the PMOS tube U3 so that it is normally in the on state. At this time, the positive power supply signal VBAT of the battery normally supplies power to the MCU via the fuse F1 and the PMOS tube U3.

[0042] The input signals of the first key KEY1 , the second key KEY2 and the third key KEY3 are high level 1 when the corresponding keys are not pressed; and are low level 0 when the corresponding keys are pressed.

[0043] The resistor R2 is used to ensure that the transistor Q1 is in the cut-off state by default when powered on.

[0044] In the instrumentation forced shutdown circuit of the present application, three appropriate keys are selected from the original keys of the instrumentation as the first key KEY1, the second key KEY2 and the third key KEY3, according to Figure 1The instrumentation forced shutdown circuit shown is connected between the battery and the MCU power supply circuit. Pressing any of the keys KEY1, KEY2, and KEY3 will not trigger the shutdown function of the circuit. Only when the three keys KEY1, KEY2, and KEY3 connected to the instrumentation forced shutdown circuit are pressed at the same time will the shutdown function be triggered. When the user presses the three keys at the same time, KEY1, KEY2, and KEY3 are low level, and the input signals A and B of the OR gate chip U1 are low level 0, so the output signal Y of the OR gate chip U1 is low level 0. Further, at this time, the input signals A and B of the NOR gate chip U2 are both low level 0, and the output signal Y of the NOR gate chip U2 is high level 1, then the transistor Q1 is turned on. The transistor Q1 is turned on, causing the transistor Q2 to be turned off. The transistor Q2 is turned off, which causes the GS voltage of the PMOS tube U3 to be less than the turn-on voltage, and then the PMOS tube U3 is turned off. After the PMOS tube U3 is turned off, the subsequent MCU power supply circuit is disconnected from the battery and becomes unpowered. At this time, the MCU power supply signal VBAT_PWR is less than the MCU's operating voltage, that is, the MCU is disconnected from the power supply and can be shut down.

[0045] In an exemplary embodiment, the present application also provides an instrument, which is powered by a battery and is provided with Figure 1 The instrumentation forced shutdown circuit shown can realize the forced power-off shutdown function when the MCU crashes. This method uses the buttons of the original instrumentation to add the function of forced shutdown without adding additional buttons. It is a combined hidden design and does not affect the weight and appearance of the original instrumentation. The present application adopts a combination design of three buttons, which requires the three buttons to be pressed at the same time to complete the shutdown function, so there is no problem of false touch, which improves the safety of use. Pressing the three buttons at the same time can achieve an immediate forced shutdown, which will not be inconvenient to operate due to too many combination buttons, and there is no problem of users having to wait for dozens of seconds to shut down. In addition, the instrumentation forced shutdown circuit of the present application adopts low-power gate circuit devices, and its power consumption is at the uA level, which hardly affects the original battery life of the instrumentation, so it has broad application prospects.

[0046] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0047] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A forced shutdown circuit for an instrument, characterized in that: include: OR gate chip U1, NOR gate chip U2, resistor R1, resistor R2, transistor Q1, transistor Q2, PMOS tube U3, resistor R3, resistor R4, resistor R5, resistor R6 and capacitor C1; The first input pin of the OR gate chip U1 is connected to the first key KEY1; the second input pin of the OR gate chip U1 is connected to the second key KEY2; the output pin of the OR gate chip U1 is connected to the first input pin of the NOR gate chip U2; the second input pin of the NOR gate chip U2 is connected to the third key KEY3; the output pin of the NOR gate chip U2 is connected to one end of the resistor R1; the other end of the resistor R1 is respectively connected to the base of the transistor Q1 and one end of the resistor R2; the other end of the resistor R2 and the emitter of the transistor Q1 are grounded; the collector of the transistor Q1 is respectively connected to one end of the resistor R3, one end of the resistor R4 and the base of the transistor Q2 The other end of the resistor R3 and the emitter of the transistor Q2 are grounded; the collector of the transistor Q2 is connected to one end of the resistor R5; the other end of the resistor R5 is respectively connected to one end of the resistor R6, one end of the capacitor C1 and the gate of the PMOS tube U3; the other end of the resistor R4, the other end of the resistor R6, the other end of the capacitor C1 and the source of the PMOS tube U3 are all connected to the positive electrode of the battery in the instrument; the negative electrode of the battery is grounded; the drain of the PMOS tube U3 is connected to the power supply circuit of the microcontroller in the instrument; the first button KEY1, the second button KEY2 and the third button KEY3 are three different buttons on the instrument.

2. The instrument forced shutdown circuit according to claim 1, characterized in that: When the first key KEY1 , the second key KEY2 or the third key KEY3 is pressed, it is at a low level.

3. The instrument forced shutdown circuit according to claim 2, characterized in that: When the first key KEY1 and the second key KEY2 are pressed simultaneously, the output pin of the OR gate chip U1 outputs a low level; otherwise, the output pin of the OR gate chip U1 outputs a high level.

4. The instrument forced shutdown circuit according to claim 3, characterized in that: When the first key KEY1 , the second key KEY2 , and the third key KEY3 are pressed simultaneously, the output pin of the NOR gate chip U2 outputs a high level; otherwise, the output pin of the NOR gate chip U2 outputs a low level.

5. The instrument forced shutdown circuit according to claim 4, characterized in that: When the output pin of the NOR gate chip U2 outputs a high level, the transistor Q1 is turned on, the transistor Q2 is turned off, and the PMOS tube U3 is turned off; otherwise, the PMOS tube U3 is turned on.

6. The instrument forced shutdown circuit according to claim 1, characterized in that: Also includes: Fuse F1; the other end of the resistor R4, the other end of the resistor R6, the other end of the capacitor C1 and the source of the PMOS tube U3 are all connected to the positive electrode of the battery through the fuse F1.

7. The instrument forced shutdown circuit according to claim 1, characterized in that: The OR gate chip U1 and the NOR gate chip U2 are both powered by 3.3V voltage.

8. The instrument forced shutdown circuit according to claim 1, characterized in that: Also includes: Capacitor C3; the power pin of the OR gate chip U1 is grounded through the capacitor C3.

9. The instrument forced shutdown circuit according to claim 1, characterized in that: Also includes: Capacitor C2; the power pin of the NOR gate chip U2 is grounded through the capacitor C2.

10. An instrument powered by a battery, characterized in that: An instrument forced shutdown circuit comprising any one of claims 1 to 9.

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