A pulse protection circuit

Abstract

The pulse protection circuit provided by the present invention only needs to add simple electronic components between each IO signal receiving pin that needs pulse protection and the power module in the integrated circuit of the chip, and implements signal isolation of the IO signal structure pin based on the power module, ensuring that the MOS tube cannot be turned on before the power module is initialized. Since the MOS tube cannot be turned on, the IO interference signal cannot directly enter the chip, thereby achieving the function of isolating the interference signal. The present application uses a simple circuit and realizes the protection of the internal logic circuit of the chip at a relatively low cost.

Description

Technical Field

[0001] The invention relates to the technical field of protection circuits, in particular to a pulse protection circuit. Background Art

[0002] In wired communications, interference wave processing is an issue that must be considered during circuit design. Figure 1 The figure shows the logical structure of our existing products such as the Lexmark series encryption chips. The signals from external chips such as the main control chip are connected to the signal receiving pin rPin in the logic circuit inside the encryption chip based on the IO interface. The power module in the figure represents the power circuit inside the encryption chip, which supplies power to other logic circuits in the encryption chip. In the specific implementation, the power module is a common level conversion circuit to achieve logic level conversion, such as converting 3.3V to Vcore voltage. In actual use, some system-level interference signals often occur, such as interference introduced when the mains is powered on, interference from the digital circuit on the board, etc., which will cause greater interference to this type of printer port. These interference signals will cause the encryption chip to misjudge when receiving the signal and cause communication failure, and even burn the circuit in severe cases.

[0003] In the prior art, most of the methods are to add RC filters to the circuit to filter the interference signal, or use complex circuits such as comparator circuits or signal adjustment circuits to adjust the signal. However, due to its structural characteristics, each RC filter has its own filtering range, and its filtering frequency range is limited, and it is impossible to completely limit the high-energy signal. As for the complex signal adjustment circuit, it requires customized design, and the structure is also relatively complex, which will increase the design cost. Summary of the invention

[0004] In order to solve the problem of filtering large-energy interference signals in the filtering method in the prior art, or the high cost of signal adjustment circuit design, the present invention provides a pulse protection circuit, which can protect the internal logic circuit of the chip at a relatively low cost.

[0005] The technical solution of the present invention is as follows: a pulse protection circuit, characterized in that it comprises: resistors R0 and R1, a diode D1 and a MOS tube; One end of the resistor R0 is connected to an external IO pin, the other end of the resistor R0 is connected to the source of the MOS tube, and the drain of the MOS tube is connected to the IO signal receiving pin in the protected logic circuit; the power supply V core The end is used to power the logic circuit; one end of the resistor R1 is connected to the drain of the MOS tube, and the other end of the resistor R1 is connected to the power supply or ground, and when the MOS tube is turned off, a missing signal is provided to the logic circuit.

[0006] It is further characterized by: When the MOS tube is a PMOS tube, the other end of the resistor R1 is grounded to GND; When the MOS tube is an NMOS tube, the other end of the resistor R1 is connected to the power supply V of the power module. core end; It also includes: a diode D1; The gate of the MOS tube is connected to the cathode of the diode D1, and the anode of the diode D1 is connected to the reset control signal pin of the power module; The turn-on time of the MOS tube is adjusted based on the conduction power of the diode D1.

[0007] The pulse protection circuit provided by the present invention only needs to add simple electronic components between each IO signal receiving pin that needs pulse protection and the power module in the integrated circuit of the chip, and implements signal isolation of the IO signal structure pin based on the power module, ensuring that the MOS tube cannot be turned on before the power module is initialized. Since the MOS tube cannot be turned on, the IO interference signal cannot directly enter the chip, thereby achieving the function of isolating the interference signal. The present application uses a simple circuit and realizes the protection of the internal logic circuit of the chip at a relatively low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of the structure of an integrated circuit inside a chip in the prior art; Figure 2 This is a pulse protection circuit diagram based on NMOS tube; Figure 3 This is a pulse protection circuit diagram based on PMOS tube; Figure 4 To add a comparison diagram of signal changes before and after the protection circuit of this application. DETAILED DESCRIPTION

[0009] The present application includes a pulse protection circuit, which includes: resistors R0 and R1, diode D1, diode D1 and MOS tube, the specific connection relationship is as follows Figure 2 and Figure 3 As shown. Among them, Figure 2 and Figure 3The power module in the figure is based on the power circuit in the existing chip logic circuit, such as: level conversion circuit implementation. When the power module supplies power to other logic modules in its chip integrated circuit, it will provide Vcore voltage; when the power module is initialized and can supply power normally, it will notify each logic circuit with a high-level signal "1" through the reset control signal por. During the power supply process of the power module, the por signal continues to be output at a high level. The logic circuit in the figure is an existing logic circuit of the chip, and the specific structure is different based on the different IO signal receiving pins rPin. The technical solution of the present application can perform interference signal protection on the logic circuit associated with any IO signal receiving pin in the chip logic circuit.

[0010] like Figure 2 As shown in the figure, when the MOS tube is an NMOS tube, one end of the resistor R0 is connected to the external IO pin, and the other end is connected to the source of the MOS tube Source, the drain of the MOS tube Drain is connected to the IO signal receiving pin rPin in the protected logic circuit; the gate of the MOS tube is connected to the cathode of the diode D1, and the anode of the diode D1 is connected to the reset control signal pin por of the power module; the power supply V of the power module core The end is used to power the logic circuit; one end of the resistor R1 is connected to the drain of the MOS tube, and the other end of the resistor R1 is connected to the power supply V of the power module. core , when the MOS tube is turned off, it provides the missing signal to the logic circuit.

[0011] After the whole system is powered on, each working module is first initialized and enters the initialization state. At this time, the working state of all modules is not stable. This application uses the power module to isolate the signal of the port. Before the power module completes the initialization, V core The MOS tube without power supply is in an unstable state, and the Por reset signal is also in a low level state; the MOS tube without power supply is in a closed state at this time, that is, the MOS tube cannot be turned on. Since the MOS tube cannot be turned on, the IO interference signal cannot directly enter the chip through the IO signal receiving pin rPin, thereby achieving the function of isolating the power-on interference signal. This method can effectively disconnect the path of the interference signal entering the IO signal receiving pin rPin before the power module is initialized, thereby effectively isolating the interference signal from damaging the logic circuit.

[0012] When the chip power supply and other analog modules are initialized, the power supply module sends a control signal to notify other logic circuits that the power supply is available, and the MOS tube is turned on, thereby connecting the IO port and the logic circuit. Figure 2 In the circuit shown, resistor R1 is connected to the logic circuit supply voltage V COREThis is because if the NMOS tube wants to be turned on, its gate voltage should be greater than the source voltage. If IO is a high-level signal, the NMOS tube will be turned off, so the R1 resistor plays a role in giving the high-level signal (that is, the green line is connected to the V core ). When the IO port is at a low level, the NMOS tube is turned on, and the low-level signal pulls the logic level down through the NMOS tube, ensuring that the signal entering the IO port can be accurately transmitted to the IO signal receiving pin in the logic circuit.

[0013] like Figure 3 As shown in the figure, when the MOS tube is a PMOS tube, one end of the resistor R0 is connected to the external IO pin, and the other end is connected to the source of the MOS tube Source, the drain of the MOS tube Drain is connected to the IO signal receiving pin rPin in the protected logic circuit; the gate of the MOS tube is connected to the cathode of the diode D1, and the anode of the diode D1 is connected to the reset control signal pin por of the power module; the power supply V of the power module core One end of the resistor R1 is connected to the drain of the MOS tube, and the other end of the resistor R1 is grounded GND. When the MOS tube is turned off, a missing signal is provided to the logic circuit.

[0014] When the MOS tube is a PMOS tube, when the gate Gate is a low-level signal (to ensure that the voltage at this end is less than the source Source), when the IO port voltage is high, the PMOS tube is turned on, the IO port signal is connected to the logic circuit, and the logic circuit is at a high level. When the IO port voltage is low, the PMOS tube is turned off, the IO port signal is disconnected from the logic circuit, and the logic circuit is controlled by the R1 resistor at this time, and the voltage is low. This ensures the normal transmission of the IO signal.

[0015] In actual applications, the IO port of the logic chip is interfered with before the analog circuit is initialized, which can easily lead to chip initialization failure or chip damage. If during normal communication, since the power supply of the slave chip is provided by the host, the IO port is interfered with by a large signal during the initialization process, the working state of the receiving chip will be unstable, and the signal cannot be received and processed normally. For example, in a printer, the main control chip will send a print command to the slave chip, such as the ink cartridge control chip. If the ink cartridge control chip is interfered with by the signal during the power-on stage of the printer, resulting in the failure of chip initialization, the ink cartridge control chip will lose the command because it has not completed the initialization operation, which will cause the whole machine to fail to start.

[0016] In this application, a diode D1 is provided, and the conduction voltage of the D1 tube can be used to control the turn-on delay time of the MOS tube, and the signal sent from the IO port is delayed according to the preset time, reducing the probability of signal loss due to the logic circuit not being ready. Assuming that D1 is turned on at 0.7V, the threshold voltage of the MOS tube is VGS, and the IO port is at a low level (generally 0), the MOS tube can be turned on when and only when the voltage V≥VGS+0.7 given by the power module, thereby achieving signal delay and ensuring that the IO signal can be transmitted to the logic circuit after the logic circuit is ready, reducing the probability of IO signal loss. In specific implementation, the turn-on time of the MOS tube is adjusted based on the conduction power supply of the diode D1, ensuring that the delay time can be adjusted according to actual conditions, ensuring that this application is more practical.

[0017] In specific applications, the por signal is the internal reset control signal of the power supply. If an NMOS tube is used, por can give a normal high-level signal. If a PMOS tube is used, the por signal needs to be inverted, that is, an inverter is connected when por is output ( Figure 3 marked as ~por in the text).

[0018] like Figure 4 As shown, the signal transmitted from the IO port carries an interference wave, and the arrival time is earlier than the ready time of the power module. After the circuit processing of the present application, the interference wave before the power is ready is cut off to prevent the interference wave from damaging the logic circuit. At the same time, the IO signal can be adjusted to be consistent with the ready time of the power supply, reducing the probability of signal loss.

[0019] After using the technical solution of the present invention, the characteristics of the MOS tube as a switch tube are used to shield the interference signal of the IO signal receiving port based on the signal of the power module. The circuit implementation structure of the present application is simple, with high fault tolerance, and is suitable for most IO port application scenarios. The use of MOS tubes as control pins can effectively isolate large current scenarios and further protect the chip logic port. At the same time, a diode D1 is set in the circuit, and the opening time is further accurately controlled by adding a control circuit at the D1 end, ensuring that the IO port signal can specify the delay time and ensure the controllability of the IO port signal delivery time.

Claims

1. A pulse protection circuit, characterized in that: It includes: resistors R0 and R1, diode D1 and MOS tube; One end of the resistor R0 is connected to an external IO pin, the other end of the resistor R0 is connected to the source of the MOS tube, and the drain of the MOS tube is connected to the IO signal receiving pin in the protected logic circuit; the power supply V core The end is used to power the logic circuit; one end of the resistor R1 is connected to the drain of the MOS tube, and the other end of the resistor R1 is connected to the power supply or ground, and when the MOS tube is turned off, a missing signal is provided to the logic circuit.

2. A pulse protection circuit according to claim 1, characterized in that: When the MOS tube is a PMOS tube, the other end of the resistor R1 is grounded GND.

3. A pulse protection circuit according to claim 1, characterized in that: When the MOS tube is an NMOS tube, the other end of the resistor R1 is connected to the power supply V of the power module. core end.

4. A pulse protection circuit according to claim 1, characterized in that: It also includes: a diode D1; The gate of the MOS tube is connected to the cathode of the diode D1 , and the anode of the diode D1 is connected to the reset control signal pin of the power module.

5. A pulse protection circuit according to claim 4, characterized in that: The turn-on time of the MOS tube is adjusted based on the conduction power of the diode D1.

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