Frequency divider circuit

Abstract

The present specification relates to a frequency divider circuit. The frequency divider circuit includes: a first latch; a first output amplifier having at least one input coupled to the at least one output of the first latch; a second latch having at least one input coupled to the at least one output of the first output amplifier; and a second output amplifier having at least one input coupled to the at least one output of the second latch, and having at least one output coupled to the input of the first latch.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to French patent application No. 2310585, filed on October 4, 2023, entitled “Procédé de fabrication d'uncondensateur”, which is incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic circuits and devices, and more particularly to circuits and devices suitable for processing radio frequency signals.The present disclosure more precisely relates to frequency divider circuits. Background Art

[0004] Radio frequency signals currently have a very large number of uses, such as radio communications, systems for detecting the presence and / or speed of objects, certain medical devices, household appliances, etc.

[0005] For this purpose, it may be useful to apply manipulations to these radio frequency signals, such as, for example, manipulations with respect to the frequencies of the radio frequency signals.

[0006] It would be desirable to be able to improve, at least in part, certain aspects of known electronic systems adapted to apply operations to one or more radio frequency signals. Summary of the invention

[0007] There is a need for electronic systems and devices adapted to more efficiently apply operations to radio frequency signals.

[0008] There is a need for a more efficient frequency divider circuit for receiving radio frequency signals.

[0009] A need exists for a frequency divider circuit that receives a radio frequency signal with improved output amplitude.

[0010] A need exists for a frequency divider circuit that receives a radio frequency signal with attenuated phase noise.

[0011] Embodiments overcome all or part of the disadvantages of known electronic devices adapted to operate upon radio frequency signals.

[0012] Embodiments overcome all or some of the disadvantages of known frequency divider circuits for receiving radio frequency signals.

[0013] An embodiment provides a divider circuit comprising: a first latch; a first output amplifier having at least one input coupled to at least one output of the first latch; a second latch having at least one input coupled to at least one output of the first output amplifier; and a second output amplifier having at least one input coupled to at least one output of the second latch and having at least one output coupled to an input of the first latch.

[0014] According to an embodiment, the circuit further comprises a first capacitor having a terminal coupled to at least one output of the first output amplifier.

[0015] According to an embodiment, the circuit further comprises a second capacitor having a terminal coupled to at least one output of the second output amplifier.

[0016] According to an embodiment, the circuit is adapted to receive a first signal.

[0017] According to an embodiment, the first latch comprises at least one clock terminal adapted to receive the first signal.

[0018] According to an embodiment, the second latch comprises at least one clock terminal adapted to receive the first signal.

[0019] According to an embodiment, the first signal is a radio frequency signal.

[0020] According to an embodiment, the circuit is adapted to divide the frequency of the first signal by two.

[0021] According to an embodiment, the first latch, the second latch, the first output amplifier and the second output amplifier are powered by the same power supply voltage.

[0022] According to an embodiment, the first latch, the second latch, the first output amplifier, and the second output amplifier receive the same reference voltage.

[0023] According to an embodiment, the reference voltage is ground. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The foregoing features and advantages, and others, will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0025] Figure 1 An embodiment of a frequency divider circuit is shown entirely schematically in block form;

[0026] Figure 2 Partially shown in box form Figure 1 An electrical diagram of an embodiment of a frequency divider circuit;

[0027] Figure 3 Shows Figure 2 An electrical diagram of a latch of an embodiment of the present invention;

[0028] Figure 4 Shows Figure 2 An electrical diagram of an output amplifier of an embodiment;

[0029] Figure 5 Partially shown in box form Figure 2 An electrical diagram of a variation of an embodiment of a frequency divider circuit; and

[0030] Figure 6 Shows Figure 5 An electrical diagram of an embodiment of a latch. DETAILED DESCRIPTION

[0031] In the various drawings, similar features have been designated by similar reference numerals. In particular, common structural and / or functional features between the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0032] For clarity, only the steps and elements useful for understanding the described embodiments have been illustrated and described in detail.

[0033] Unless otherwise indicated, when reference is made to two elements being connected together, this means a direct connection without any intervening elements other than conductors, and when reference is made to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0034] In the following description, when reference is made to terms that qualify absolute positions such as terms "front", "back", "top", "bottom", "left", "right", etc., or relative positions such as terms "above", "below", "upper", "lower", etc., or terms that qualify directions such as terms "horizontal", "vertical", etc., unless otherwise specified, it refers to the orientation in the drawings.

[0035] Unless otherwise specified, the expressions "about", "approximately", "substantially" and "approximately" mean plus or minus 10%, preferably plus or minus 5%.

[0036] In the remainder of this disclosure, periodic electromagnetic signals in the frequency range of 3 kHz to 300 GHz are referred to as radio frequency signals or RF signals.

[0037] The embodiments described hereinafter relate to circuits suitable for processing radio frequency signals and in particular to frequency divider circuits suitable for receiving a radio frequency signal as input so as to deliver as output two radio frequency signals having frequencies equal to fractions of the frequency of the input signal. The case studied herein is more precisely a frequency divider circuit suitable for dividing the frequency of the input signal by two.

[0038] Frequency divider circuits are usually associated with output amplifiers that enable the output signal to be amplified. However, these associations often have too low an output amplitude and have an impact on the phase noise of circuits downstream of the frequency divider circuit. The embodiments described hereinafter improve the output amplitude and reduce the phase noise of the output signal.

[0039] For this purpose, the embodiments described hereinafter relate to a frequency divider circuit having an output amplifier which is directly integrated into the frequency divider circuit. Figure 1 , Figure 2 and Figure 5 Two embodiments of such a circuit are described.

[0040] Figure 1 An embodiment of a frequency divider circuit 100 (f / 2) is shown entirely schematically in block form.

[0041] As previously described, the frequency divider circuit 100 is formed by components of a frequency divider circuit and two output amplifiers. Figure 2 and Figure 5 Two detailed examples of circuit 100 are described.

[0042] The circuit 100 includes two input terminals IN+ and IN-, between which an input signal is applied. More specifically, the two input terminals IN+ and IN- are coupled to input nodes IN100+ and IN100-, which are adapted to receive a radio frequency input signal having a frequency f.

[0043] The circuit 100 also includes four output terminals I+, I-, Q+, and Q- for transmitting in-phase and quadrature output signals (I, Q) of the circuit 100. More specifically, the two output terminals I+ and I- are coupled to output nodes OUT100-I+ and OUT100-I-, and the output nodes OUT100-I+ and OUT100-I- are suitable for transmitting output radio frequency signals having a frequency f / 2. The two output terminals Q+ and Q- are coupled to output nodes OUT100-Q+ and OUT100-Q-, and the output nodes OUT100-Q+ and OUT100-Q- are suitable for transmitting output radio frequency signals having a frequency f / 2 corresponding to the input signal in quadrature.

[0044] Output load at Figure 1, i.e., a circuit including a resistor assembled in parallel with a capacitor. More specifically, the output load at the output nodes OUT100-I+ and OUT100-I- includes a resistor RI coupled between the nodes OUT100-I+ and OUT100-I- and a capacitor CI coupled between the nodes OUT100-I+ and OUT100-I-. Similarly, the output load at the output nodes OUT100-Q+ and OUT100-Q- includes a resistor RQ coupled between the nodes OUT100-Q+ and OUT100-Q- and a capacitor CQ coupled between the nodes OUT100-Q+ and OUT100-Q-.

[0045] The circuit 100 further comprises two power supply terminals VDD and GND. The power supply terminal VDD is adapted to receive a power supply voltage VDD. The power supply terminal GND is adapted to receive a reference voltage GND, such as ground.

[0046] Circuit 100 also includes terminals for receiving a bias current and a voltage Bias100. Figure 2 These bias currents and voltages are described in further detail.

[0047] Figure 2 The diagram partially shows the Figure 1 An embodiment of a frequency divider circuit 200 of the type of circuit 100 is described.

[0048] As previously described, the frequency divider circuit 200 includes two input terminals IN200+ and IN200- adapted to receive the radio frequency input signal SigRF200. The circuit 200 also includes two first output terminals OUT200-I+ and OUT200-I-, the first output terminals OUT200-I+ and OUT200-I- adapted to deliver a first output signal SigRF200-I having a frequency equal to half the frequency of the input signal SigRF200. The circuit 200 also includes two second output terminals OUT200-Q+ and OUT200-Q-, the second output terminals OUT200-Q+ and OUT200-Q- adapted to deliver a second output signal SigRF200-Q in phase and quadrature with the first output signal SigRF200-I. The circuit 200 also receives a power supply voltage VDD and a reference voltage GND.

[0049] The frequency divider circuit 200 includes a latch 201 (CML LATCH), an output amplifier 202 (BUFFER I), a latch 203 (CML LATCH), and an output amplifier 204 (BUFFER Q).

[0050] Latches 201 and 203 are CML (Current Mode Logic) type latches or current mode logic latches. Figure 3 A detailed example of the latches 201 and 203 is described. The latches 201 and 203 each have the following terminals: two input terminals D+ and D-, two output terminals Q+ and Q-, two clock terminals Clk+ and Clk-, one bias terminal Bias; and two power supply terminals VDD and GND.

[0051] Clock terminals Clk+ and Clk− of latches 201 and 203 receive the radio frequency input signal SigRF200 .

[0052] The bias terminal Bias of latch 201 receives bias voltage Vbias201. The bias terminal Bias of latch 203 receives bias voltage Vbias203. According to an example, bias voltages Vbias201 and Vbias203 are the same and are coupled to each other through a current mirror ( Figure 2 not shown) transmission.

[0053] The power supply terminals VDD of both latches 201 and 203 receive the power supply voltage VDD. Similarly, the power supply terminals GND of both latches 201 and 203 receive the reference voltage GND.

[0054] The output amplifiers 202 and 204 each have the following terminals: two input terminals + and −, two output terminals OUT+ and OUT−, one bias terminal Bias, and two power supply terminals VDD and GND.

[0055] against Figure 4 Detailed examples of amplifiers 202 and 204 are described.

[0056] The bias terminal Bias of the amplifier 202 receives a bias current Ibias 202. The bias terminal Bias of the amplifier 204 receives a bias current Ibias 204. According to an example, the bias currents Ibias 202 and Ibias 204 are the same.

[0057] The power supply terminals VDD of both amplifiers 202 and 204 receive the power supply voltage VDD. Similarly, the power supply terminals GND of both amplifiers 202 and 204 receive the reference voltage GND.

[0058] According to an embodiment, output terminals Q+ and Q- of latch 201 are coupled to, preferably connected to, + and - input terminals of output amplifier 202. In other words, output terminal Q+ of latch 201 is coupled to, preferably connected to, the + input terminal of output amplifier 202, and output terminal Q- of latch 201 is coupled to, preferably connected to, the - input terminal of output amplifier 202.

[0059] According to an embodiment, the output terminals OUT+ and OUT- of the output amplifier 202 deliver the first output signal SigRF200-I, but are also coupled to, preferably connected to, the input terminals D+ and D- of the latch 203. In other words, the output terminal OUT+ of the amplifier 202 is coupled to, preferably connected to, the input terminal D+ of the latch 203, and the output terminal OUT- of the amplifier 202 is coupled to, preferably connected to, the input terminal D- of the latch 203.

[0060] According to an embodiment, output terminals Q+ and Q- of latch 203 are coupled to, preferably connected to, + and - input terminals of output amplifier 204. In other words, output terminal Q+ of latch 203 is coupled to, preferably connected to, the + input terminal of output amplifier 204, and output terminal Q- of latch 203 is coupled to, preferably connected to, the - input terminal of output amplifier 204.

[0061] According to an embodiment, the output terminals OUT+ and OUT- of the output amplifier 204 deliver the second output signal SigRF200-Q, but are also coupled to, and preferably connected to, the input terminals D+ and D- of the latch 201. In other words, the output terminal OUT+ of the amplifier 204 is coupled to, and preferably connected to, the input terminal D+ of the latch 201, and the output terminal OUT- of the amplifier 204 is coupled to, and preferably connected to, the input terminal D- of the latch 201.

[0062] The advantage of this embodiment is that the circuit 200 has a lower output impedance by integrating the output amplifiers 202 and 204 into the loop formed by the latches 201 and 203. In other words, the output signals SigRF200-I and SigRF200-Q have a higher amplitude, which reduces the phase noise of the downstream circuits of the circuit 200.

[0063] Figure 3 Shown for Figure 2 A practical example of a latch 300 of the type of latches 201 and 203 described.

[0064] According to an example, latch 300 is formed by a metal oxide semiconductor field effect transistor, or a MOSFET transistor, or a MOS transistor. In addition, latch 300 is formed by an N-channel MOS transistor, or an N-type MOS transistor, or an NMOS transistor. Those skilled in the art will be able to easily adapt the circuit forming latch 300 using a P-channel MOS transistor, or a P-type MOS transistor, or a PMOS transistor.

[0065] Like latches 201 and 203 , latch 300 includes the following terminals: two input terminals D+ and D−, two output terminals Q+ and Q−, two clock terminals Clk+ and Clk−, and two power supply terminals VDD and GND.

[0066] The latch 300 includes two transistors NMOS T301 and T302, the gates of which are coupled to the input terminals D+ and D- of the latch 300. More specifically, the gate of the transistor T301 is coupled to, preferably connected to, the input terminal D+, and the gate of the transistor T302 is coupled to, preferably connected to, the input terminal D-. The sources of the transistors T301 and T302 are coupled to, preferably connected together and coupled to, preferably connected to, a node A301. The drain of the transistor T301 is coupled to, preferably connected to, the output terminal Q+ of the latch 300. The drain of the transistor T302 is coupled to, preferably connected to, the output terminal Q- of the latch 300.

[0067] The latch 300 also includes two resistors R301 and R302, which couple the output terminals Q+ and Q- to the power supply terminal VDD. More specifically, the first terminal of the resistor R301 is coupled to, preferably connected to, the output terminal Q+, and the second terminal of the resistor R301 is coupled to, preferably connected to, the power supply terminal VDD. Similarly, the first terminal of the resistor R302 is coupled to, preferably connected to, the output terminal Q-, and the second terminal of the resistor R302 is coupled to, preferably connected to, the power supply terminal VDD.

[0068] The latch 300 also includes two NMOS transistors T303 and T304, whose drains and their gates are coupled to the output terminals Q+ and Q-. More specifically, the drain of the transistor T303 and the gate of the transistor T304 are coupled, preferably connected together, and coupled to, preferably connected to the output terminal Q+. The drain of the transistor T304 and the gate of the transistor T303 are coupled, preferably connected together, and coupled to, preferably connected to the output terminal Q-. In addition, the sources of the transistors T303 and T304 are coupled, preferably connected together, and coupled to, preferably connected to the node B301.

[0069] The latch 300 also includes an NMOS transistor T305 and a capacitor C301 coupled to the clock terminal Clk+. More specifically, a first terminal of the capacitor C301 is coupled to, preferably connected to, the clock terminal Clk+, and a second terminal of the capacitor C301 is coupled to, preferably connected to, the gate of the transistor T305. The drain of the transistor T305 is coupled to, preferably connected to, the node A301, and the source of the transistor T305 is coupled to, preferably connected to, the power supply terminal GND.

[0070] The latch 300 also includes a resistor R303 that couples the gate of the transistor T305 to a node that delivers the bias voltage Vbias300. More specifically, a first terminal of the resistor R303 is coupled to, preferably connected to, the gate terminal of the transistor T305, and a second terminal of the resistor R303 is coupled to, preferably connected to, the node that delivers the bias voltage Vbias300.

[0071] The latch 300 also includes an NMOS transistor T306 and a capacitor C302 coupled to the clock terminal Clk-. More specifically, a first terminal of the capacitor C302 is coupled to, preferably connected to, the clock terminal Clk-, and a second terminal of the capacitor C302 is coupled to, preferably connected to, the gate of the transistor T306. The drain of the transistor T306 is coupled to, preferably connected to, the node B301, and the source of the transistor T306 is coupled to, preferably connected to, the power supply terminal GND.

[0072] The latch 300 also includes a resistor R304 that couples the gate of the transistor T306 to a node that delivers the bias voltage Vbias300. More specifically, a first terminal of the resistor R304 is coupled to, preferably connected to, the gate terminal of the transistor T306, and a second terminal of the resistor R304 is coupled to, preferably connected to, the node that delivers the bias voltage Vbias300.

[0073] Figure 4 Shown for Figure 2 A practical example of an output amplifier 400 of the type described for output amplifiers 202 and 204 .

[0074] According to an example, the amplifier 400 is formed by MOS transistors, and more precisely by NMOS transistors. A person skilled in the art will be able to easily adapt the circuit forming the amplifier 400 using PMOS transistors.

[0075] Like the amplifiers 202 and 204 , the amplifier 400 includes the following terminals: two input terminals + and −, two output terminals OUT+ and OUT−, one bias terminal Bias, and two power supply terminals VDD and GND.

[0076] The output amplifier 400 includes two transistors NMOS T401 and T402, the gates of which are coupled to the + and - input terminals of the amplifier 400. More specifically, the gate of the transistor T401 is coupled to, preferably connected to, the + input terminal, and the gate of the transistor T402 is coupled to, preferably connected to, the - input terminal. The drains of the transistors T401 and T402 are coupled to, preferably connected together and coupled to, preferably connected to, the power supply terminal VDD. The source of the transistor T401 is coupled to, preferably connected to, the output terminal OUT+ of the amplifier 400. The source of the transistor T402 is coupled to, preferably connected to, the output terminal OUT- of the amplifier 400.

[0077] The amplifier 400 also includes a capacitor C401, which couples the gate terminal of the transistor T401 to the node A401. More specifically, a first terminal of the capacitor C401 is coupled to, preferably connected to, the gate terminal of the transistor T401, i.e., coupled to, preferably connected to the +input terminal, and a second terminal of the capacitor C401 is coupled to, preferably connected to, the node A401.

[0078] The amplifier 400 further includes a capacitor C402, which couples the gate terminal of the transistor T401 to the node B401. More specifically, a first terminal of the capacitor C402 is coupled to, preferably connected to, the gate terminal of the transistor T402, i.e., coupled to, preferably connected to the -input terminal, and a second terminal of the capacitor C402 is coupled to, preferably connected to, the node B401.

[0079] The amplifier 400 also includes NMOS transistors T408 and T409 forming a current mirror, which forms a current source of the amplifier 400. The drain of the transistor T408 is coupled to, preferably connected to, the output terminal OUT+, and the source of the transistor T408 is coupled to, preferably connected to the terminal GND. The drain of the transistor T409 is coupled to, preferably connected to, the output terminal OUT-, and the source of the transistor T409 is coupled to, preferably connected to the terminal GND. The gate of the transistor T408 is coupled to, preferably connected to the node B401. The gate of the transistor T409 is coupled to, preferably connected to the node A401.

[0080] The amplifier 400 also includes two resistors R401 and R402 coupled in series between nodes B401 and A401. More specifically, a first terminal of the resistor R401 is coupled to, preferably connected to, the node B401, and a second terminal of the resistor R401 is coupled to, preferably connected to, the node D401. A first terminal of the resistor R402 is coupled to, preferably connected to, the node D401, and a second terminal of the resistor R402 is coupled to, preferably connected to, the node A401.

[0081] The amplifier 400 also includes a capacitor C403 and a transistor T411. The capacitor C403 couples the node D401 to the terminal GND. The first terminal of the capacitor C403 is coupled to, preferably connected to, the node D401, and the second terminal of the capacitor C403 is coupled to, preferably connected to, the terminal GND. The drain and gate of the transistor T411 are coupled to, preferably connected together and coupled to, preferably connected to, the terminal Bias and the node D401, and the source of the transistor T411 is coupled to, preferably connected to, the terminal GND.

[0082] Figure 5 The diagram is partially shown in the form of a box. Figure 1 Another embodiment of a frequency divider circuit 500 of the type described is described.

[0083] The frequency divider circuit 500 is similar to the Figure 2 The frequency divider circuit 200 is described. Elements common to the circuits 200 and 500 are not described in detail here, and only the differences between the circuits 200 and 500 are highlighted.

[0084] Thus, like circuit 200, circuit 500 includes circuits such as those for Figure 2 The latches 501 and 503 and the output amplifiers 202 and 204 are assembled as described in the embodiment of the present invention. The latches 501 and 503 are very similar to those described for Figure 2 The latches 501 and 503 are similar to the latches 201 and 203 described above and specifically include the same connection terminals. The latches 501 and 503 differ from the latches 201 and 203 in that they also include a terminal Bias2 that enables application of a second bias voltage. Figure 6 A detailed example of the latches 501 and 503 is described.

[0085] The circuit 500 also comprises a capacitive output link. For this purpose, the circuit 500 comprises capacitors C501 , C502 , C503 and C504 arranged at the outputs of the output amplifiers 202 and 204 .

[0086] More specifically, circuit 500 also includes capacitors C501 and C502, which couple output terminals OUT+ and OUT- of output amplifier 202 to output nodes OUT500-I+ and OUT500-I- of circuit 500. In other words, a first terminal of capacitor C501 is coupled to, preferably connected to, terminal OUT+ of amplifier 202, and a second terminal of capacitor C501 is coupled to, preferably connected to, node OUT500-I+ and terminal D+ of latch 503. Similarly, a first terminal of capacitor C502 is coupled to, preferably connected to, terminal OUT- of amplifier 202, and a second terminal of capacitor C502 is coupled to, preferably connected to, node OUT500-I- and terminal D+ of latch 503.

[0087] Similarly, circuit 500 also includes capacitors C503 and C504, which couple output terminals OUT+ and OUT- of output amplifier 202 to output nodes OUT500-Q+ and OUT500-Q- of circuit 500. In other words, a first terminal of capacitor C503 is coupled to, preferably connected to, terminal OUT+ of amplifier 202, and a second terminal of capacitor C503 is coupled to, preferably connected to, node OUT500-Q+ and terminal D+ of latch 501. Similarly, a first terminal of capacitor C504 is coupled to, preferably connected to, terminal OUT- of amplifier 202, and a second terminal of capacitor C504 is coupled to, preferably connected to, node OUT500-Q- and terminal D- of latch 501.

[0088] Figure 6 Shown for Figure 2 A practical example of a latch 600 of the type of latches 501 and 503 described.

[0089] Latch 600 is similar to the Figure 3 The latch 300 described herein. Elements common to the circuits 300 and 600 are not described in detail herein, and only the differences between the circuits 300 and 600 are highlighted.

[0090] Thus, like latch 300, latch 600 includes a Figure 3 1 and 2. The transistors T301 to T306, the resistors R301 to R304, and the capacitors C301 and C302 are arranged as described above.

[0091] The latch 600 also includes bias resistors R601 and R602, so that the gates of transistors T301 and T302 can be biased. More specifically, resistor R301 includes a first terminal coupled to, preferably connected to, the gate terminal of transistor T301 and a second terminal coupled to, preferably connected to, a node for delivering bias voltage Vbias600. Resistor R302 includes a first terminal coupled to, preferably connected to, the gate terminal of transistor T302 and a second terminal coupled to, preferably connected to, a node for delivering bias voltage Vbias600. According to an example, bias voltage Vbias600 is different from bias voltage Vbias300. According to an example, bias voltage Vbias600 is determined by a control loop ( Figure 6 (not shown) control.

[0092] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will recognize other variations.

[0093] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A frequency divider circuit, comprising: a first latch; a first output amplifier having: at least one input coupled to at least one output of the first latch; a second latch having: at least one input coupled to at least one output of the first output amplifier; A second output amplifier having at least one input coupled to at least one output of the second latch and having at least one output coupled to at least one input of the first latch.

2. The frequency divider circuit of claim 1, further comprising a first capacitor coupled between at least one output of the first output amplifier and at least one input of the second latch.

3. The frequency divider circuit of claim 1, further comprising a second capacitor coupled between at least one output of the second output amplifier and at least one input of the first latch. The frequency divider circuit of claim 1 , wherein the frequency divider circuit is configured to receive a first signal.

5. The frequency divider circuit of claim 4 , wherein the first latch comprises: At least one clock terminal is configured to receive the first signal.

6. The frequency divider circuit of claim 5, wherein the second latch comprises: At least one clock terminal is configured to receive the first signal. The frequency divider circuit of claim 4 , wherein the first signal is a radio frequency signal. 8 . The frequency divider circuit of claim 4 , wherein the frequency divider circuit is configured to divide the frequency of the first signal by 2. 9 .

9. The frequency divider circuit of claim 1, wherein the first latch, the second latch, the first output amplifier, and the second output amplifier are powered by a same power supply voltage. 10 . The frequency divider circuit of claim 9 , wherein the first latch, the second latch, the first output amplifier, and the second output amplifier receive a same reference voltage.

11. The frequency divider circuit of claim 10, wherein the reference voltage is ground.

12. A frequency divider circuit comprising: a first latch; a first output amplifier having: a first input and a second input, respectively coupled to the first output and the second output of the first latch; a second latch having: a first input and a second input, respectively coupled to the first output and the second output of the first output amplifier; as well as A second output amplifier having a first input and a second input coupled to the first output and the second output of the second latch, respectively; and having a first output and a second output coupled to the first input and the second input of the first latch, respectively.

13. The frequency divider circuit according to claim 12, further comprising: a first capacitor coupled between a first output of the first output amplifier and a first input of the second latch; as well as A second capacitor is coupled between a second output of the first output amplifier and a second input of the second latch.

14. The frequency divider circuit according to claim 12, further comprising: a third capacitor coupled between the first output of the second output amplifier and the first input of the first latch; as well as A fourth capacitor is coupled between the second output of the second output amplifier and the second input of the first latch.

15. The frequency divider circuit of claim 12, wherein the frequency divider circuit is configured to receive a +component and a -component of the first signal.

16. The frequency divider circuit of claim 15, wherein the first latch comprises: The first clock terminal and the second clock terminal are respectively configured to receive a + component and a - component of the first signal.

17. The frequency divider circuit of claim 16, wherein the second latch comprises: The first clock terminal and the second clock terminal are respectively configured to receive a + component and a - component of the first signal.

18. The frequency divider circuit of claim 15, wherein the first signal is a radio frequency signal.

19. The frequency divider circuit of claim 15, wherein the frequency divider circuit is configured to divide the frequencies of the first signal and the second signal by 2.

20. The frequency divider circuit of claim 12, wherein the first latch, the second latch, the first output amplifier, and the second output amplifier are powered by a same supply voltage.

21. The frequency divider circuit of claim 20, wherein the first latch, the second latch, the first output amplifier, and the second output amplifier receive a same reference voltage.

22. The frequency divider circuit of claim 21, wherein the reference voltage is ground.

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