A Phase-Locked Loop Locking and Unlocking Detection Circuit and a Phase-Locked Loop System

Abstract

The present invention relates to the field of integrated circuits, and discloses a phase-locked loop (PLL) locking and unlocking detection circuit and a PLL system. The PLL locking and unlocking detection circuit realizes efficient detection of the locking and unlocking states of the PLL through integrated design. The circuit includes a phase detector, a locking detection circuit, an unlocking detection circuit, and a LOCKDET circuit. The phase detector receives a reference clock signal and a feedback clock signal and outputs corresponding signals. The locking detection circuit performs phase consistency detection for multiple consecutive cycles through a multi-stage cascaded D flip-flop and outputs a locking signal. The unlocking detection circuit outputs an unlocking signal based on the reference clock signal, the feedback clock signal, and the output signal of the phase detector. The LOCKDET circuit generates a comprehensive LOCKDET signal by combining the locking and unlocking signals. The present invention simplifies the circuit design, reduces the hardware cost, improves the response speed and system stability by integrating the locking and unlocking detection functions.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a phase-locked loop locking and unlocking detection circuit and a phase-locked loop system. Background Art

[0002] As an important frequency control system, the phase-locked loop (PLL) is widely used in fields such as frequency synthesis, clock synchronization, and carrier recovery. Its core function is to make the output signal synchronize with the reference signal in terms of frequency and phase through feedback control. However, in practical applications, due to the influence of factors such as power supply noise, temperature change, and interference, the phase-locked loop often switches between the locked and unlocked states. To ensure the normal operation of the phase-locked loop and respond to state changes in a timely manner, it is usually necessary to design a locking detection and an unlocking detection circuit to monitor the working state of the phase-locked loop and ensure the reliability and stability of the system.

[0003] In the prior art, the locking detection and unlocking detection circuits usually adopt an independent design scheme. The locking detection circuit mainly determines whether the phase-locked loop reaches the locked state by monitoring the phase difference between the output signal and the reference signal; while the unlocking detection circuit determines whether unlocking occurs by monitoring the frequency deviation, phase jump, or stability of the output signal. Although this separate design scheme can achieve the detection of the two states respectively, it has the following obvious deficiencies:

[0004] (1) Complex circuit structure: The locking detection and unlocking detection require the separate design of independent detection circuits, which not only increases the complexity and design difficulty of the circuit, but also raises the chip manufacturing cost.

[0005] (2) Slow detection response: The independent detection circuit may lead to an extended signal transmission path. Especially in high-frequency application scenarios, it cannot quickly and accurately feedback the change of the phase-locked loop state, affecting the real-time performance of the system.

[0006] (3) Waste of hardware resources: The separate design scheme requires more hardware resources for the system, such as flip-flops, logic gates, etc., reducing the chip integration and increasing the power consumption.

[0007] (4) Poor detection reliability: Due to the lack of the judgment of the correlation between states, the detection results may be inconsistent, reducing the detection reliability.

[0008] (5) Complex timing control: The independent detection circuit requires additional timing control logic to coordinate the work, increasing the complexity of the timing design. Summary of the Invention

[0009] The object of the present invention is to provide a phase-locked loop (PLL) locking and unlocking detection circuit and a PLL system. The PLL locking and unlocking detection circuit integrates the locking detection and unlocking detection functions, enabling the locking detection and unlocking detection to work collaboratively, simplifying the circuit design while improving the detection efficiency and reliability.

[0010] To solve the above technical problems, the present invention provides a PLL locking and unlocking detection circuit and a PLL system. The PLL locking and unlocking detection circuit includes:

[0011] A phase detector, which receives a reference clock signal and a feedback clock signal generated by a frequency divider in the PLL, and outputs a first output signal and a second output signal;

[0012] A locking detection circuit, connected to the phase detector, includes a plurality of cascaded D flip-flops. The clock input terminal of the plurality of cascaded D flip-flops receives a first clock signal obtained by logical operation of the first output signal and the second output signal. The data input terminal receives a trigger signal obtained by delay processing and logical operation of the first output signal and the second output signal. The reset terminal receives a signal obtained by logical operation of the trigger signal and a reset signal. The locking detection circuit performs locking detection of the PLL based on the output signal of the plurality of cascaded D flip-flops and outputs a locking signal;

[0013] An unlocking detection circuit, connected to the phase detector, is used for unlocking detection of the PLL. When the locking detection circuit determines that the PLL is locked, the unlocking detection circuit receives the reference clock signal, the feedback clock signal, the first output signal, and the second output signal, and outputs an unlocking signal through a D flip-flop and logical operation;

[0014] A LOCKDET circuit, connected to the locking detection circuit and the unlocking detection circuit, receives the locking signal and the unlocking signal, and outputs a LOCKDET signal through a D flip-flop to achieve simultaneous detection of locking detection and unlocking detection.

[0015] Further, the phase detector includes a first D flip-flop and a second D flip-flop. The clock input terminal of the first D flip-flop receives the reference clock signal. The clock input terminal of the second D flip-flop receives the feedback clock signal. The data input terminals of the first D flip-flop and the second D flip-flop are both connected to a high-level signal, and the output terminals respectively output the first output signal and the second output signal.

[0016] Further, the locking detection circuit further includes:

[0017] A first exclusive-NOR gate, with two input terminals respectively connected to the output terminal of the first D flip-flop and the output terminal of the second D flip-flop;

[0018] The first delay unit, the input end of which is connected to the output end of the first exclusive-NOR gate;

[0019] The first NAND gate, the first input end of which is connected to the output end of the delay unit, the second input end of which is connected to the output end of the first exclusive-NOR gate, and the output end of which outputs the trigger signal;

[0020] The first AND gate, the two input ends of which are respectively connected to the output end of the first D flip-flop and the output end of the second D flip-flop, and the output end of which outputs the first clock signal;

[0021] The second AND gate, the first input end of which is connected to the output end of the first NAND gate, and the second input end of which is connected to the reset signal;

[0022] The clock input end of the multi-stage cascaded D flip-flop is connected to the output end of the first AND gate, the data input end of which is connected to the output end of the first NAND gate, and the reset end of which is connected to the output end of the second AND gate;

[0023] The third AND gate, the input end of which is connected to the output end of the multi-stage cascaded D flip-flop;

[0024] The fourth AND gate, the input end of which is connected to the output end of the multi-stage cascaded D flip-flop;

[0025] The fifth AND gate, the two input ends of which are respectively connected to the output ends of the third AND gate and the fourth AND gate, and the output end of which outputs the lock detection signal.

[0026] Further, the multi-stage cascaded D flip-flop includes an eight-stage cascaded D flip-flop. The data input end of the first-stage D flip-flop is connected to the output end of the first NAND gate, the clock input end of which is connected to the output end of the first AND gate for receiving the first clock signal, and the reset end of which is connected to the output end of the second AND gate;

[0027] The data input ends of the subsequent seven-stage D flip-flops are sequentially connected to the output end of the previous-stage D flip-flop, the clock input ends of which are all connected to the output end of the first AND gate to receive the first clock signal, and the reset ends of which are all connected to the output end of the second AND gate.

[0028] Further, the first input end of the third AND gate is connected to the output end of the first-stage D flip-flop, the second input end of the third AND gate is connected to the output end of the second-stage D flip-flop, the third input end of the third AND gate is connected to the output end of the fifth-stage D flip-flop, and the fourth input end of the third AND gate is connected to the output end of the sixth-stage D flip-flop;

[0029] The first input terminal of the fourth AND gate is connected to the output terminal of the third-stage D flip-flop, the second input terminal of the fourth AND gate is connected to the output terminal of the fourth-stage D flip-flop, the third input terminal of the fourth AND gate is connected to the output terminal of the seventh-stage D flip-flop, and the fourth input terminal of the fourth AND gate is connected to the output terminal of the eighth-stage D flip-flop.

[0030] Further, the out-of-lock detection circuit includes:

[0031] A third D flip-flop, with its clock input terminal connected to a reference clock signal, its data input terminal connected to the first output signal, and its reset terminal connected to a reset signal;

[0032] A fourth D flip-flop, with its clock input terminal connected to a feedback clock signal, its data input terminal connected to the second output signal, and its reset terminal connected to the reset signal;

[0033] A second exclusive-NOR gate, with its two input terminals respectively connected to the output terminals of the third D flip-flop and the fourth D flip-flop;

[0034] A fifth D flip-flop, with its clock input terminal connected to the feedback clock signal, its data input terminal connected to the output terminal of the second exclusive-NOR gate, its output terminal outputting an out-of-lock signal, and its reset terminal connected to the reset signal.

[0035] Further, the LOCKDET circuit includes:

[0036] A sixth D flip-flop, with its data input terminal connected to a high-level signal, its clock input terminal connected to the lock signal, its reset terminal connected to the output terminal of the fifth D flip-flop, receiving the out-of-lock signal, and its output terminal outputting a LOCKDET signal.

[0037] Further, it further includes a TIEH circuit, and the TIEH circuit is used to provide a high-level signal to the entire circuit.

[0038] Further, the TIEH circuit includes:

[0039] An N-type MOS transistor, with its source electrode connected to a power supply voltage and its drain electrode connected to a high-level signal;

[0040] A P-type MOS transistor, with its source electrode grounded, its gate electrode and drain electrode connected, and the common connection terminal of the gate electrode and the drain electrode connected to the gate electrode of the N-type MOS transistor.

[0041] A phase-locked loop system includes the above-mentioned phase-locked loop locking and out-of-lock detection circuit and a phase-locked loop.

[0042] Compared with the prior art, the present invention has at least the following beneficial effects:

[0043] The phase-locked loop locking and unlocking detection circuit proposed by the present invention organically integrates the locking detection and unlocking detection functions. The phase detector outputs corresponding signals, and cooperates with the locking signal output by the locking detection circuit through continuous multiple cycles of phase consistency detection by a multi-stage cascaded D flip-flop and the unlocking signal output by the unlocking detection circuit. The LOCKDET circuit realizes the synchronous progress of locking detection and unlocking detection, simplifies the circuit structure, and improves the efficiency and accuracy of phase-locked loop state monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is the basic structural block diagram of the phase-locked loop;

[0045] Figure 2 is the circuit diagram of locking detection and unlocking detection in an embodiment of the present invention;

[0046] Figure 3 is the timing diagram of each signal in an embodiment of the present invention.

[0047] Reference numerals in the drawings: 1, phase detector; 2, unlocking detection circuit; 3, LOCKDET circuit; 4, locking detection circuit; 5, TIEH circuit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] The following will describe in more detail a phase-locked loop locking and unlocking detection circuit and a phase-locked loop system of the present invention in conjunction with the schematic diagrams, in which the preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as a broad guidance for those skilled in the art and not as a limitation to the present invention.

[0049] In the following paragraphs, the present invention will be described more specifically by way of example with reference to the drawings. The advantages and features of the present invention will be clearer according to the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0050] As Figure 1 shown, the basic structure of the phase-locked loop includes a phase detector (PFD), a charge pump (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO), and a frequency divider (DIV). The basic working principle is as follows:

[0051] The reference clock signal CLK_REF and the feedback clock signal CLK_FB from the frequency divider are simultaneously input to the phase detector. The phase detector generates a pair of UP (frequency up) and DOWN (frequency down) control pulses with time difference characteristics by comparing the phase and frequency differences of the two signals. The pulse pair drives the charge pump (CP) module to generate a bidirectional charge and discharge current ICP, where the UP pulse triggers the injection of a forward current and the DN pulse causes the extraction of a reverse current. The output current of the charge pump (CP) is integrated and noise-filtered by the loop filter (LPF) and then converted into a smooth DC control voltage VCONT. The control voltage is applied to the tuning terminal of the voltage-controlled oscillator (VCO), and the output frequency of the oscillator is accurately regulated through the voltage-frequency conversion characteristic to generate a high-quality clock signal CLK_OUT. The output signal is frequency down-sampled by the frequency divider to form the CLK_FB signal, thereby constituting a closed-loop negative feedback system. When the loop reaches lock, the frequency relationship CLK_OUT = N × CLK_REF is satisfied, and at the same time, the phases of the two input signals are kept synchronized, so as to achieve accurate frequency synthesis and phase tracking functions.

[0052] However, as described in the background art, the lock detection and unlock detection of the phase-locked loop usually adopt an independently designed scheme, which has problems such as complex circuit structure, slow detection response, waste of hardware resources, poor detection reliability, and complex timing control.

[0053] Therefore, as Figures 2 to 3 shown, an embodiment of the present invention proposes a phase-locked loop lock and unlock detection circuit, and the phase-locked loop lock and unlock detection circuit includes a phase detector 1, a lock detection circuit 4, an unlock detection circuit 2, and a LOCKDET circuit 3.

[0054] The phase detector 1 is connected to the reference clock signal CLK_REF and the feedback clock signal CLK_FB generated by the frequency divider in the phase-locked loop. By comparing the phases of the reference clock signal CLK_REF and the feedback clock signal CLK_FB and determining whether the two clock signals are synchronized, a first output signal QA and a second output signal QB are output.

[0055] The lock detection circuit 4, which is connected to the phase detector 1, includes a plurality of D flip-flops connected in series. The clock input terminal of the plurality of D flip-flops connected in series receives a first clock signal CK1 obtained by logical operation of the first output signal QA and the second output signal QB. The data input terminal receives a trigger signal obtained by delay processing and logical operation of the first output signal QA and the second output signal QB. The reset terminal receives a signal obtained by logical operation of the trigger signal and the reset signal RSTN. The lock detection circuit performs lock detection of the phase-locked loop based on the output signal of the plurality of D flip-flops connected in series and outputs a lock signal LOCK to ensure the stable operation of the detection circuit and avoid instability caused by misjudgment.

[0056] The lock loss detection circuit 2 is connected to the phase discriminator 1 and is used for detecting the lock loss of the phase-locked loop. After the lock detection circuit determines that the phase-locked loop is locked, the lock loss detection circuit receives the reference clock signal CLK_REF, the feedback clock signal CLK_FB, the first output signal QA, and the second output signal QB, and outputs a lock loss signal FAULT through a D flip-flop and logical operations, providing a lock loss warning signal for the subsequent circuit so as to take measures in a timely manner.

[0057] The LOCKDET circuit 3 is connected to the lock detection circuit and the lock loss detection circuit, receives the lock signal LOCK and the lock loss signal FAULT, and outputs a LOCKDET signal through a D flip-flop to implement lock detection and lock loss detection. The LOCKDET circuit 3 integrates the lock detection and lock loss detection functions into one circuit, starts the lock loss detection function at the rising edge of the lock signal LOCK, and outputs the LOCKDET signal at the falling edge of the lock loss signal FAULT, enabling simultaneous detection of lock detection and lock loss detection, simplifying the circuit design while reducing the circuit complexity and cost.

[0058] Please continue to refer to Figure 2 , in one embodiment, it further includes a TIEH circuit 5, and the TIEH circuit 5 generates a constant high voltage for providing a high-level signal TIEH to the entire circuit to improve the circuit reliability.

[0059] In this embodiment, the phase discriminator 1 includes a first D flip-flop and a second D flip-flop. The clock input terminal of the first D flip-flop receives the reference clock signal CLK_REF, the clock input terminal of the second D flip-flop receives the feedback clock signal CLK_FB. The data input terminals of the first D flip-flop and the second D flip-flop are both connected to the high-level signal TIEH, and the output terminals respectively output the first output signal QA and the second output signal QB.

[0060] In addition, the phase discriminator 1 further includes a second delay unit, a sixth AND gate, a seventh AND gate, and two groups of inverter chains.

[0061] Specifically, the second delay unit includes an inverter, and the output terminal of the inverter is respectively connected to the reset terminals of the first D flip-flop and the second D flip-flop. Through the delay processing of the inverter, it is ensured that the phase difference between the reference clock signal CLK_REF and the feedback clock signal CLK_FB can be accurately reflected.

[0062] The first input terminal of the sixth AND gate is connected to the output terminal of the first D flip-flop, and the second input terminal is connected to the output terminal of the second D flip-flop. The sixth AND gate is used to detect the first output signal QA output by the first D flip-flop and the second output signal QB output by the second D flip-flop. The first output signal QA and the second output signal QB respectively represent the phase information of the reference clock and the feedback clock of the phase-locked loop. When the first output signal QA and the second output signal QB are both at high level, the sixth AND gate outputs a high level, indicating that the phases of the two signals are close to being the same. Through the logical judgment of the AND gate, signals that meet the conditions are screened out, avoiding misjudgment caused by noise or transient phase deviation.

[0063] The first input terminal of the seventh AND gate is connected to the output terminal of the sixth AND gate, and the second input terminal is connected to the reset signal RSTN. The output terminal of the seventh AND gate is connected to the input terminal of the inverter. The seventh AND gate performs a logical AND operation on the output signal of the sixth AND gate and the reset signal RSTN. By combining with the reset signal RSTN, it is ensured that during the reset period, the output of the circuit is cleared or maintained in the initial state, avoiding misoperation.

[0064] Each of the two groups of inverter chains includes two cascaded NOT gates. The input terminal of the first inverter chain is connected to the output terminal of the first D flip-flop, receives the first output signal QA and outputs the UP signal; the input terminal of the second inverter chain is connected to the output terminal of the second D flip-flop, receives the second output signal QB and outputs the DOWN signal. Since there may be certain phase noise or jitter in the feedback signal and the reference clock of the phase-locked loop, the inverter chain reduces signal errors through a certain delay. At the same time, the inverter chain converts the first output signal QA and the second output signal QB into UP and DOWN signals respectively, which are used to drive the subsequent Charge Pump. The UP signal indicates that the output frequency of the phase-locked loop needs to be increased, and the DOWN signal indicates that the output frequency of the phase-locked loop needs to be decreased.

[0065] In this embodiment, the lock detection circuit 4 includes a first XNOR gate, a first delay unit, a first NAND gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, and a multi-stage cascaded D flip-flop.

[0066] The two input terminals of the first XNOR gate are respectively connected to the output terminal of the first D flip-flop and the output terminal of the second D flip-flop. The first XNOR gate detects the phases of the reference clock signal CLK_REF and the feedback clock signal CLK_FB. When the first output signal QA and the second output signal QB are the same (i.e., the phases are the same), the first XNOR gate outputs a high level; when the first output signal QA and the second output signal QB are different (i.e., the phases are different), the first XNOR gate outputs a low level.

[0067] The input terminal of the first delay unit is connected to the output terminal of the first exclusive-NOR gate. The first delay unit introduces a certain delay to accommodate the small phase error existing between the reference clock and the feedback clock, avoiding misjudgment caused by clock jitter or noise.

[0068] The first input terminal of the first NAND gate is connected to the output terminal of the delay unit, the second input terminal is connected to the output terminal of the first exclusive-NOR gate, and the output terminal outputs the trigger signal. The first NAND gate combines the delayed signal and the original exclusive-NOR gate output signal to generate a logically processed signal, avoiding misjudgment caused by short-term phase deviation and improving the reliability of lock detection.

[0069] The two input terminals of the first AND gate are respectively connected to the output terminal of the first D flip-flop and the output terminal of the second D flip-flop, and the output terminal outputs the first clock signal CK1. The first AND gate detects whether the first output signal QA and the second output signal QB exist simultaneously, ensuring the stability and reliability of the clock signal and providing an accurate clock signal for subsequent multi-stage D flip-flops.

[0070] The first input terminal of the second AND gate is connected to the output terminal of the first NAND gate, and the second input terminal is connected to the reset signal RSTN. The second AND gate combines the logically processed signal with the reset signal RSTN to ensure that during the reset period, the output of the circuit is cleared or maintained in the initial state.

[0071] The clock input terminal of the multi-stage cascaded D flip-flop is connected to the output terminal of the first AND gate, the data input terminal is connected to the output terminal of the first NAND gate, and the reset terminal is connected to the output terminal of the second AND gate. The multi-stage cascaded D flip-flop continuously samples the input signal to ensure that the reference clock and the feedback clock are consistent in multiple cycles, thereby determining whether the phase-locked loop is locked and improving the accuracy and stability of lock detection.

[0072] The input terminals of the third AND gate and the fourth AND gate are both connected to the output terminal of the multi-stage cascaded D flip-flop. The third AND gate and the fourth AND gate together process the output signal of the multi-stage D flip-flop, further ensuring the stability and reliability of the signal and providing an accurate logical judgment for the final lock detection signal.

[0073] The two input terminals of the fifth AND gate are respectively connected to the output terminals of the third AND gate and the fourth AND gate, and the output terminal outputs the lock detection signal LOCK. The fifth AND gate combines the output signals of the third AND gate and the fourth AND gate, and through the logical processing of the AND gate, ensures that the final lock detection signal is output only when multiple logical conditions are met, improving the accuracy and reliability of lock detection.

[0074] In one embodiment, the multi-stage cascaded D flip-flop includes an eight-stage cascaded D flip-flop. In the actual circuit design process, even when the phase-locked loop is locked, the pulses of the reference clock signal CLK_REF and the feedback clock signal CLK_FB cannot be exactly the same, and there is a certain error. Therefore, a delay unit is required to accommodate this error. To prevent false locking, the locking detection circuit 4 uses an eight-stage D flip-flop. That is, when the clock signal CLK_REF and the feedback clock signal CLK_FB are the same in eight consecutive cycles, it is determined that the phase-locked loop is locked, and the locking signal LOCK changes from low to high.

[0075] It can be understood that it is not only the consistency in eight consecutive cycles that can be accepted. Those skilled in the art can flexibly set according to the actual application situation, such as less than eight or more than eight; correspondingly, the number of cascaded D flip-flops is also adjusted accordingly.

[0076] Specifically, the data input terminal of the first-stage D flip-flop is connected to the output terminal of the first NAND gate, the clock input terminal is connected to the output terminal of the first AND gate for receiving the first clock signal CK1, and the reset terminal is connected to the output terminal of the second AND gate.

[0077] The data input terminals of the subsequent seven-stage D flip-flops are sequentially connected to the output terminals of the previous-stage D flip-flops, the clock input terminals are all connected to the output terminal of the first AND gate to receive the first clock signal CK1, and the reset terminals are all connected to the output terminal of the second AND gate. The multi-stage cascaded D flip-flop ensures stable phase consistency of the phase-locked loop in multiple cycles through sampling and judgment in eight consecutive cycles, avoiding misjudgment caused by short-term phase deviation or noise.

[0078] In one embodiment, the first input terminal of the third AND gate is connected to the output terminal of the first-stage D flip-flop, the second input terminal of the third AND gate is connected to the output terminal of the second-stage D flip-flop, the third input terminal of the third AND gate is connected to the output terminal of the fifth-stage D flip-flop, and the fourth input terminal of the third AND gate is connected to the output terminal of the sixth-stage D flip-flop. The third AND gate performs a logical AND operation on the output signals of the first-stage, second-stage, fifth-stage, and sixth-stage D flip-flops. Only when these four signals are all high, the output of the third AND gate is high.

[0079] The first input terminal of the fourth AND gate is connected to the output terminal of the third-stage D flip-flop. The second input terminal of the fourth AND gate is connected to the output terminal of the fourth-stage D flip-flop. The third input terminal of the fourth AND gate is connected to the output terminal of the seventh-stage D flip-flop. The fourth input terminal of the fourth AND gate is connected to the output terminal of the eighth-stage D flip-flop. The fourth AND gate performs a logical AND operation on the output signals of the third-stage, fourth-stage, seventh-stage, and eighth-stage D flip-flops. Only when these four signals are all at a high level simultaneously, the output of the fourth AND gate is at a high level.

[0080] Through the continuous sampling and grouped detection of multiple-stage D flip-flops by the third AND gate and the fourth AND gate, the misjudgment caused by noise in a single cycle or short-term phase deviation is effectively reduced, ensuring that the signal remains stable in multiple cycles and improving the stability of lock detection.

[0081] In this embodiment, the unlock detection circuit 2 includes a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, and a second XNOR gate.

[0082] The clock input terminal of the third D flip-flop is connected to the reference clock signal CLK_REF. The data input terminal is connected to the first output signal, that is, connected to the output terminal of the first D flip-flop. The reset terminal is connected to the reset signal RSTN. The third D flip-flop samples the phase information of the reference clock signal CLK_REF and synchronously samples and stores the output signal within the clock cycle of the reference clock signal CLK_REF. In this way, the third D flip-flop can accurately reflect the phase state of the reference clock and provide a reference signal for subsequent unlock detection.

[0083] The clock input terminal of the fourth D flip-flop is connected to the feedback clock signal CLK_FB. The data input terminal is connected to the second output signal, that is, connected to the output terminal of the second D flip-flop. The reset terminal is connected to the reset signal RSTN. The fourth D flip-flop samples the phase information of the feedback clock signal CLK_FB and synchronously samples and stores the output signal within the clock cycle of the feedback clock signal CLK_FB. In this way, the fourth D flip-flop can accurately reflect the phase state of the feedback clock and provide a feedback signal for subsequent unlock detection.

[0084] The second exclusive-NOR gate has two input terminals respectively connected to the output terminals of the third D flip-flop and the fourth D flip-flop. The second exclusive-NOR gate compares the phase states of the reference clock signal CLK_REF and the feedback clock signal CLK_FB. When the two input signals are the same (i.e., the phases are consistent), the second exclusive-NOR gate outputs a high level; when the two input signals are different (i.e., the phases are inconsistent), the second exclusive-NOR gate outputs a low level. In this way, the second exclusive-NOR gate can detect the phase difference between the reference clock and the feedback clock, providing a logical judgment basis for out-of-lock detection.

[0085] The clock input terminal of the fifth D flip-flop is connected to the feedback clock signal CLK_FB, the data input terminal is connected to the output terminal of the second exclusive-NOR gate, the output terminal outputs an out-of-lock signal FAULT, and the reset terminal is connected to the reset signal RSTN. The fifth D flip-flop synchronously samples and stores the output signal of the second exclusive-NOR gate within the clock cycle of the feedback clock signal CLK_FB, and outputs the final out-of-lock signal FAULT. When the second exclusive-NOR gate outputs a low level, it indicates that the phases of the reference clock and the feedback clock are inconsistent, and the fifth D flip-flop sets the out-of-lock signal FAULT to a low level, indicating that the phase-locked loop is out of lock; when the second exclusive-NOR gate outputs a high level, it indicates that the phases are consistent, and the fifth D flip-flop keeps the out-of-lock signal FAULT at a high level, indicating that the phase-locked loop is locked.

[0086] In this embodiment, the LOCKDET circuit 3 includes a sixth D flip-flop. The data input terminal of the sixth D flip-flop is connected to a high-level signal TIEH, the clock input terminal is connected to the lock signal LOCK, the reset terminal is connected to the output terminal of the fifth D flip-flop to receive the out-of-lock signal FAULT, and the output terminal outputs a LOCKDET signal. When the phase-locked loop is locked, the lock signal LOCK becomes a high level. At the rising edge of the lock signal LOCK, the sixth D flip-flop samples the high-level signal TIEH to the output terminal, making the LOCKDET signal become a high level. When the phase-locked loop is out of lock, the out-of-lock signal FAULT becomes a low level. At the falling edge of the out-of-lock signal FAULT, the output of the sixth D flip-flop is cleared, making the LOCKDET signal become a low level.

[0087] In this embodiment, the TIEH circuit 5 includes an N-type MOS transistor and a P-type MOS transistor. The source of the N-type MOS transistor is connected to the power supply voltage VDD, and the drain is connected to the high-level signal TIEH. The source of the P-type MOS transistor is grounded, the gate and the drain are connected, and the common connection terminal of the gate and the drain is connected to the gate of the N-type MOS transistor. The TIEH circuit 5 utilizes the characteristics of the P-type MOS transistor. When the P-type MOS transistor is turned on, the low level of its gate and drain will turn off the N-type MOS transistor, ensuring that the TIEH signal is pulled up to VDD, thereby providing a stable high-level signal.

[0088] The lock detection and unlock detection circuit of the present invention integrates a phase detector 1, a lock detection circuit 4, an unlock detection circuit 2, a LOCKDET circuit 3, and a TIEH circuit 5 to achieve efficient detection of the locked and unlocked states of a phase-locked loop (PLL). Taking Figure 3 as an example, the specific working principle of the present invention is as follows:

[0089] When the circuit starts up, the unlock signal FAULT, the lock signal LOCK, and the LOCKDET signal are all at a low level. The TIEH circuit 5 generates a stable high-level signal TIEH, providing a stable high-level input for the LOCKDET circuit.

[0090] The phase detector 1 outputs a first output signal QA and a second output signal QB through a reference clock signal CLK_REF and a feedback clock signal CLK_FB. The lock detection circuit 4 determines whether the PLL is locked by continuously detecting the phase consistency within eight cycles. When the reference clock signal CLK_REF and the feedback clock signal CLK_FB are consistent within eight consecutive cycles, the lock signal LOCK changes from low to high, indicating that the PLL is locked.

[0091] The unlock detection circuit 2 continuously monitors the phase consistency of the clock signal CLK_REF and the feedback clock signal CLK_FB. When the clock signal CLK_REF and the feedback clock signal CLK_FB are not detected within a certain cycle, the unlock signal FAULT changes from high level to low level, indicating that the PLL is unlocked.

[0092] The LOCKDET circuit 3 starts the unlock detection function at the rising edge of the lock signal LOCK, setting the LOCKDET signal to a high level. When the falling edge of the unlock signal FAULT arrives, the LOCKDET circuit 3 outputs a low level, indicating that the PLL is unlocked. The LOCKDET signal provides a clear indication of the PLL state for the subsequent digital circuit, facilitating the system to monitor and adjust the working state of the PLL in real time.

[0093] Through this integrated design, the present invention simplifies the circuit structure, reduces the hardware cost, and at the same time improves the response speed and stability of the system, and is particularly suitable for high-frequency applications and complex system environments.

[0094] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A phase-locked loop lock and unlock detection circuit, characterized in that: include: A phase detector is connected to a reference clock signal and a feedback clock signal generated by a frequency divider in a phase-locked loop, and outputs a first output signal and a second output signal; A lock detection circuit is connected to the phase detector, and includes a multi-stage series D flip-flop, wherein a clock input terminal of the multi-stage series D flip-flop receives a first clock signal after a logic operation of the first output signal and the second output signal, a data input terminal receives a trigger signal after a delay process and a logic operation of the first output signal and the second output signal, and a reset terminal receives a signal after a logic operation of the trigger signal and the reset signal. The lock detection circuit performs lock detection of the phase-locked loop based on the output signal of the multi-stage series D flip-flop, and outputs a lock signal; an out-of-lock detection circuit, connected to the phase detector, and used for out-of-lock detection of the phase-locked loop. When the lock detection circuit determines that the phase-locked loop is locked, the out-of-lock detection circuit receives the reference clock signal, the feedback clock signal, the first output signal, and the second output signal, and outputs an out-of-lock signal through a D flip-flop and logic operation; A LOCKDET circuit is connected to the lock detection circuit and the unlock detection circuit, receives the lock signal and the unlock signal, and outputs the LOCKDET signal through a D flip-flop to implement lock detection and unlock detection; Wherein, the lock-out detection circuit comprises: A third D flip-flop, wherein the clock input terminal is connected to the reference clock signal, the data input terminal is connected to the first output signal, and the reset terminal is connected to the reset signal; A fourth D flip-flop, wherein a clock input terminal is connected to the feedback clock signal, a data input terminal is connected to the second output signal, and a reset terminal is connected to the reset signal; A second XNOR gate, two input terminals of which are respectively connected to the output terminals of the third D flip-flop and the fourth D flip-flop; A fifth D flip-flop, wherein a clock input terminal is connected to the feedback clock signal, a data input terminal is connected to the output terminal of the second XNOR gate, an output terminal outputs an unlock signal, and a reset terminal is connected to the reset signal.

2. The phase-locked loop lock and unlock detection circuit according to claim 1, characterized in that: The phase detector includes a first D flip-flop and a second D flip-flop, the clock input end of the first D flip-flop receives a reference clock signal, the clock input end of the second D flip-flop receives a feedback clock signal, the data input ends of the first D flip-flop and the second D flip-flop are both connected to high-level signals, and the output ends output the first output signal and the second output signal respectively.

3. The phase-locked loop lock and unlock detection circuit according to claim 1, characterized in that: The lock detection circuit also includes: A first XNOR gate, two input terminals of which are respectively connected to the output terminal of the first D flip-flop and the output terminal of the second D flip-flop; A first delay unit, an input end of which is connected to the output end of the first XNOR gate; A first NAND gate, a first input end connected to the output end of the delay unit, a second input end connected to the output end of the first XNOR gate, and an output end outputting the trigger signal; A first AND gate, wherein two input terminals are respectively connected to the output terminal of the first D flip-flop and the output terminal of the second D flip-flop, and an output terminal outputs the first clock signal; A second AND gate, a first input terminal connected to the output terminal of the first NAND gate, and a second input terminal connected to a reset signal; The clock input terminal of the multi-stage series D flip-flop is connected to the output terminal of the first AND gate, the data input terminal is connected to the output terminal of the first NAND gate, and the reset terminal is connected to the output terminal of the second AND gate; A third AND gate, whose input terminal is connected to the output terminal of the multi-stage series D flip-flop; A fourth AND gate, whose input terminal is connected to the output terminal of the multi-stage series D flip-flop; The fifth AND gate has two input terminals connected to the output terminals of the third AND gate and the fourth AND gate respectively, and an output terminal outputs a locking detection signal.

4. The phase-locked loop lock and unlock detection circuit as claimed in claim 3, characterized in that: The multi-stage serially connected D flip-flops include eight stages of serially connected D flip-flops, wherein a data input terminal of a first stage of the D flip-flops is connected to an output terminal of the first NAND gate, a clock input terminal is connected to an output terminal of the first AND gate for receiving a first clock signal, and a reset terminal is connected to an output terminal of the second AND gate; The data input terminals of the subsequent seven-stage D flip-flops are connected to the output terminals of the previous stage D flip-flops in sequence, the clock input terminals are connected to the output terminals of the first AND gate to receive the first clock signal, and the reset terminals are connected to the output terminals of the second AND gate.

5. The phase-locked loop lock and unlock detection circuit as claimed in claim 4, characterized in that: The first input terminal of the third AND gate is connected to the output terminal of the first-stage D flip-flop, the second input terminal of the third AND gate is connected to the output terminal of the second-stage D flip-flop, the third input terminal of the third AND gate is connected to the output terminal of the fifth-stage D flip-flop, and the fourth input terminal of the third AND gate is connected to the output terminal of the sixth-stage D flip-flop; The first input terminal of the fourth AND gate is connected to the output terminal of the third-stage D flip-flop, the second input terminal of the fourth AND gate is connected to the output terminal of the fourth-stage D flip-flop, the third input terminal of the fourth AND gate is connected to the output terminal of the seventh-stage D flip-flop, and the fourth input terminal of the fourth AND gate is connected to the output terminal of the eighth-stage D flip-flop.

6. The phase-locked loop lock and unlock detection circuit according to claim 1, characterized in that: The LOCKDET circuit comprises: The sixth D flip-flop has a data input terminal connected to the high level signal, a clock input terminal connected to the lock signal, a reset terminal connected to the output terminal of the fifth D flip-flop, receives the unlock signal, and outputs a LOCKDET signal at its output terminal.

7. The phase-locked loop lock and unlock detection circuit according to claim 1, characterized in that: The invention also comprises a TIEH circuit, wherein the TIEH circuit is used for providing a high-level signal to the entire circuit.

8. The phase-locked loop lock and unlock detection circuit as claimed in claim 7, characterized in that: The TIEH circuit comprises: N-type MOS tube, the source is connected to the power supply voltage, and the drain is connected to the high-level signal; The P-type MOS tube has a source connected to the ground, a gate and a drain connected, and a common connection end of the gate and the drain connected to the gate of the N-type MOS tube.

9. A phase-locked loop system, characterized in that: Includes the phase-locked loop locking and unlocking detection circuit and the phase-locked loop as described in any one of 1-8.

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