Low pass filter, phase locked loop, electronic equipment and vehicle

Abstract

The invention discloses a low-pass filter, a phase-locked loop, an electronic device and a vehicle. The low-pass filter comprises a proportional path and an integral path, the input end of the proportional path is connected to the first output end of a phase detector to receive the first output signal of the phase detector; the input end of the integral path is connected to the second output end of the phase detector to receive the second output signal of the phase detector; the output ends of the proportional path and the integral path are connected as the output end of the low-pass filter; the proportional path and the integral path adjust the output end signal of the low-pass filter according to the first output signal and the second output signal respectively.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic appliances, and in particular to a low-pass filter, a phase-locked loop, an electronic device and a vehicle. Background Art

[0002] The phase-locked loop (PLL) mainly includes a phase detector (PFD), a charge pump (CP), a loop filter (LPF), and a voltage-controlled oscillator (VCO). It is a negative feedback control system that uses the voltage generated by phase synchronization to tune the voltage-controlled oscillator to generate the target frequency. Due to its unique frequency synthesis, synchronization and phase detection functions, the phase-locked loop is widely used in many fields. With the continuous development of communication technology, the requirements for the noise index of the phase-locked loop are getting higher and higher.

[0003] In the prior art, there are two main ways to reduce phase-locked loop noise: one is to increase the charge pump current and process two voltage-controlled oscillators in parallel to improve the charge pump linearity, but the disadvantage is that it will increase the chip area and increase the cost; the other is to use a dual-channel filter to reduce the resistance while not increasing the capacitance in the filter, thereby saving chip area, but the disadvantage is that an adder is required, and the adder will generate more obvious noise. Summary of the invention

[0004] To solve the above technical problems, the present invention provides a low-pass filter, a phase-locked loop, an electronic device and a vehicle, which can save chip area and eliminate the resistance noise of the traditional phase-locked loop low-pass filter, thereby reducing the noise of the phase-locked loop.

[0005] To achieve the purpose of the present invention, the present invention adopts the following technical solutions: According to a first aspect of the present invention, there is provided a low-pass filter, comprising: A proportional path, wherein an input end of the proportional path is connected to a first output end of the phase detector to receive a first output signal of the phase detector; An integration path, wherein an input end of the integration path is connected to a second output end of the phase detector to receive a second output signal of the phase detector; The output ends of the proportional path and the integral path are connected as the output end of the low-pass filter; the proportional path and the integral path adjust the output end signal of the low-pass filter according to the first output signal and the second output signal respectively.

[0006] According to some embodiments of the present invention, the proportional path includes two first capacitors C1 connected in parallel, and the first output end of the phase detector includes a first phase output pin up1 and a first signal output pin dn1; one end of the two first capacitors C1 are respectively connected to the first phase output pin up1 and the first signal output pin dn1, and the node after the two first capacitors C1 are connected in parallel serves as the output end of the proportional path.

[0007] According to some embodiments of the present invention, the integral path includes a first switch k1, a second switch k2 and a second capacitor C2, wherein the first switch k1 and the second switch k2 are connected in series to the charge pump current I CP In the path, the middle node of the first switch k1 and the second switch k2 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded; the middle node of the first switch k1 and the second switch k2 serves as the output end of the integration path.

[0008] According to some embodiments of the present invention, the second output end of the phase detector includes a second phase output pin up2 and a second signal output pin dn2, the second phase output pin up2 controls the on and off of the first switch k1; the second signal output pin dn2 controls the on and off of the second switch k2.

[0009] According to some embodiments of the present invention, the phase of the signal output by the first phase output pin up1 is the same as the phase of the signal output by the second phase output pin up2.

[0010] According to some embodiments of the present invention, a phase of a signal outputted from the first signal output pin dn1 is opposite to a phase of a signal outputted from the second signal output pin dn2 .

[0011] According to some embodiments of the present invention, the equivalent resistance R of the proportional path is R=VR / I CP =(Vp / I cp )*C1 / (2*C1+C2); wherein VR represents the output voltage of the proportional path, and Vp represents the output voltage swing of the phase detector.

[0012] A second aspect of the present invention provides a phase-locked loop, comprising the low-pass filter described in any one of the first aspects.

[0013] A third aspect of the present invention provides an electronic device, comprising the low-pass filter described in any one of the first aspect or the phase-locked loop described in the second aspect.

[0014] A fourth aspect of the present invention provides a vehicle, comprising the electronic device described in the third aspect.

[0015] According to the technical solution provided by the present invention, at least the following beneficial effects are achieved: the input end of the proportional path is connected to the first output end of the phase detector to receive the first output signal, the input end of the integral path is connected to the second output end of the phase detector to receive the second output signal, the proportional path adjusts its output end signal according to the first output signal, while the integral path adjusts its output end signal according to the second output signal, and the two output end signals are superimposed as the output end signal of the low-pass filter. By using the low-pass filter in the above technical solution, there is no need to add an additional adder, and while eliminating the resistor noise, the chip area can be reduced to a certain extent.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a circuit schematic diagram of a low-pass filter according to an embodiment of the present invention; Figure 2 is a circuit schematic diagram of a phase detector according to an embodiment of the present invention; Figure 3 It is a state diagram of output signals of each pin of the phase detector according to an embodiment of the present invention and an output voltage diagram of the proportional path.

[0018] Reference numerals: Proportional path 11, integral path 12 DETAILED DESCRIPTION

[0019] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0020] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0021] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", "set", "arrange", etc. should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] Reference below Figures 1 to 3 A low-pass filter according to an embodiment of the first aspect of the present invention is described.

[0023] like Figure 1 As shown, the low-pass filter according to the embodiment of the present invention includes a proportional path 11 and an integral path 12, the proportional path 11 and the integral path 12 are respectively connected to the phase detector PFD to receive the output signal of the phase detector PFD, and the proportional path 11 and the integral path 12 cooperate to adjust the output signal of the low-pass filter. In this way, no additional noise is generated under the premise of ensuring the optimization of the loop bandwidth and noise of the phase-locked loop PLL, so that the phase-locked loop PLL has lower noise and a smaller chip area.

[0024] Specifically, the input end of the proportional path 11 is connected to the first output end of the phase detector to receive the first output signal of the phase detector; the input end of the integral path 12 is connected to the second output end of the phase detector to receive the second output signal of the phase detector; the output ends of the proportional path 11 and the integral path 12 are connected and serve as the output end of the low-pass filter; the proportional path 11 and the integral path 12 adjust the output end signal of the low-pass filter according to the first output signal and the second output signal respectively.

[0025] In some specific embodiments of the present invention, the proportional path 11 includes two first capacitors C1, and the two first capacitors C1 are connected in parallel. The first output end of the phase detector includes a first phase output pin up1 and a first signal output pin dn1, one end of the two first capacitors C1 is connected to the first phase output pin up1 and the first signal output pin dn1 respectively, the node after the two first capacitors C1 are connected in parallel serves as the output end of the proportional path 11, and the voltage at the node after the two first capacitors C1 are connected in parallel serves as the output end voltage VR of the proportional path 11.

[0026] In some specific embodiments of the present invention, the integral path 12 includes a first switch k1, a second switch k2, and a second capacitor C2. The first switch k1 and the second switch k2 are connected in series to the current I of the charge pump CP. CPIn the path, the end of the first switch k1 that is not connected to the second switch k2 is connected to the power supply voltage Vdd_cp of the charge pump CP, and the end of the second switch k2 that is not connected to the first switch k1 is grounded. The middle node of the first switch k1 and the second switch k2 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded. The middle node of the first switch k1 and the second switch k2 serves as the output end of the integral path 12, and the voltage at the middle node of the first switch k1 and the second switch k2 serves as the output end voltage VC of the integral path 12. The output voltage OUT of the low-pass filter is formed by superimposing the output voltage VR of the proportional path 11 and the output voltage VC of the integral path 12.

[0027] Furthermore, the second output end of the phase detector includes a second phase output pin up2 and a second signal output pin dn2. The output signal of the second phase output pin up2 controls the closing or opening of the first switch k1, thereby controlling the connection or disconnection of the charging current of the charge pump CP; the output signal of the second signal output pin dn2 controls the closing or opening of the second switch k2, thereby controlling the connection or disconnection of the discharge current of the charge pump CP.

[0028] like Figure 2 As shown, in some specific embodiments of the present invention, the phase detector includes a first trigger DFF1, a second trigger DFF2, a delay device Delay, an AND gate And, a first buffer Buf1, a second buffer Buf2, a third buffer Buf3 and an inversion gate Inv.

[0029] Specifically, the power pin D1 of the first trigger DFF1 is connected to the voltage vdd, the signal pin of the first trigger DFF1 is connected to the first input signal ref_ck, the output pin Q1 of the first trigger DFF1 is connected to the input pins of the first buffer Buf1 and the second buffer Buf2, the output pin of the first buffer Buf1 corresponds to the first phase output pin up1, the output pin of the second buffer Buf2 corresponds to the second phase output pin up2, and the signal phase output by the first phase output pin up1 is the same as the signal phase output by the second phase output pin up2.

[0030] The power pin D2 of the second flip-flop DFF2 is connected to the voltage vdd, the signal pin of the second flip-flop DFF2 is connected to the second input signal dvi_ck, the output pin Q2 of the second flip-flop DFF2 is connected to the input pin of the third buffer Buf3 and the invertor Inv, the output pin of the third buffer Buf3 corresponds to the second signal output pin dn2, and the output pin of the invertor Inv corresponds to the first signal output pin dn1. The output signal of the output pin Q2 of the second flip-flop DFF2 is inverted by the invertor Inv, so the phase of the signal outputted from the first signal output pin dn1 is opposite to the phase of the signal outputted from the second signal output pin dn2.

[0031] The reset path for removing the dead zone in the phase detector is realized by the delay device Delay and the AND gate And. By introducing a delay, it is ensured that when the phase difference between the output signals of the phase output pin up and the signal output pin dn is very small, there is enough time to trigger the charge pump, thereby avoiding the occurrence of the dead zone.

[0032] Based on the above phase detector structure, such as Figure 3 As shown, when the phase of the first input signal ref_ck leads the second input signal dvi_ck by a time △t, the rising edge of the charging control signal output by the second phase output pin up2 arrives before the discharge signal output by the second signal output pin dn2, and the phase difference time is △t. When the phase of the second input signal dvi_ck leads the first input signal ref_ck by a time △t1, the rising edge of the discharge signal output by the second signal output pin dn2 arrives before the charging control signal output by the second phase output pin up2, and the phase difference time is △t1.

[0033] It should be noted that the output voltage VR of the proportional path 11 and the values ​​of the two first capacitors C1 are related to the output voltage swing Vp of the phase detector PFD. The working principle of the proportional path 11 is: since the output node of the charge pump CP is high impedance, the voltage at the node where the two first capacitors C1 are connected in parallel is the voltage output from the first phase output pin up1 and the first signal output pin dn1 (i.e., the output voltage VR of the proportional path 11) is the voltage divided by the first capacitor C1 and the second capacitor C2, VR=Vp*C1 / (2*C1+C2). The equivalent resistance of the proportional path 11 is R=VR / I CP =(Vp / I cp )*C1 / (2*C1+C2), the formula of the equivalent resistance R does not involve the resistance term, from which it can be seen that the equivalent resistance of the proportional path 11 does not generate thermal noise of the real resistance. The output voltage VC of the integral path 12 = Icp*△t / C2, from which it can be seen that when the same VC is generated, the second capacitor C2 can be reduced by reducing the current Icp of the charge pump CP, so as to achieve the effect of reducing the chip area and saving production costs.

[0034] By adopting the low-pass filter in the above technical solution, there is no need to add an additional adder. While eliminating the resistor noise, the chip area can be reduced to a certain extent without affecting the stability of the phase-locked loop.

[0035] The phase-locked loop according to the second aspect of the present invention comprises the low-pass filter described in the first aspect of the present invention.

[0036] The phase-locked loop in the above technical solution has all the beneficial effects of the above low-pass filter, which will not be described in detail here.

[0037] The electronic device according to the third aspect of the present invention comprises the low-pass filter described in the first aspect of the present invention or the phase-locked loop described in the second aspect of the present invention.

[0038] The electronic device using the above technical solution has all the beneficial effects of the above low-pass filter or phase-locked loop, which will not be described in detail here.

[0039] A vehicle according to an embodiment of the fourth aspect of the present invention comprises the electronic device described in the embodiment of the third aspect of the present invention.

[0040] The vehicle adopting the above technical solution has all the beneficial effects of the above electronic equipment, which will not be described in detail here.

[0041] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0042] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the knowledge scope of ordinary technicians in the technical field without departing from the purpose of the present invention.

Claims

1. A low-pass filter, characterized in that: include: A proportional path (11), wherein an input end of the proportional path (11) is connected to a first output end of the phase detector to receive a first output signal of the phase detector; An integration path (12), wherein an input end of the integration path (12) is connected to a second output end of the phase detector to receive a second output signal of the phase detector; The output ends of the proportional path (11) and the integral path (12) are connected to serve as the output end of the low-pass filter; the proportional path (11) and the integral path (12) adjust the output end signal of the low-pass filter according to the first output signal and the second output signal respectively.

2. The low-pass filter according to claim 1, characterized in that The proportional path (11) comprises two first capacitors C1 connected in parallel, and the first output end of the phase detector comprises a first phase output pin up1 and a first signal output pin dn1; one end of the two first capacitors C1 are respectively connected to the first phase output pin up1 and the first signal output pin dn1, and the node after the two first capacitors C1 are connected in parallel serves as the output end of the proportional path (11).

3. The low-pass filter according to claim 2, characterized in that The integral path (12) comprises a first switch k1, a second switch k2 and a second capacitor C2, wherein the first switch k1 and the second switch k2 are connected in series to a current I CP In the path, the middle node between the first switch k1 and the second switch k2 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded; the middle node between the first switch k1 and the second switch k2 serves as the output end of the integration path (12).

4. The low-pass filter according to claim 3, characterized in that The second output end of the phase detector includes a second phase output pin up2 and a second signal output pin dn2. The second phase output pin up2 controls the on-off of the first switch k1; the second signal output pin dn2 controls the on-off of the second switch k2.

5. The low-pass filter according to claim 4, characterized in that The phase of the signal outputted by the first phase output pin up1 is the same as the phase of the signal outputted by the second phase output pin up2.

6. The low-pass filter according to claim 4, characterized in that The phase of the signal outputted from the first signal output pin dn1 is opposite to the phase of the signal outputted from the second signal output pin dn2.

7. The low-pass filter according to claim 3, characterized in that The equivalent resistance R of the proportional path (11) is VR / I CP =(Vp / I cp )*C1 / (2*C1+C2); wherein VR represents the output voltage of the proportional path, and Vp represents the output voltage swing of the phase detector.

8. A phase-locked loop, characterized in that: Comprising the low pass filter as claimed in any one of claims 1 to 7.

9. An electronic device, characterized in that: It comprises a low pass filter as claimed in any one of claims 1 to 7 or a phase locked loop as claimed in claim 8.

10. A vehicle, characterized in that: Comprising an electronic device as claimed in claim 9.

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