Semiconductor Equipment

Abstract

The present disclosure relates to semiconductor devices. The analog-to-digital converter of the semiconductor device is made high-speed. A voltage quantizer circuit includes: a first comparator, the first comparator includes a first input transistor that inputs a differential input voltage and defines the value of the first bit of a digital signal; and a second comparator, the second comparator includes a second input transistor that is different from the first input transistor and defines the value of the second bit of the digital signal. A correction code determination circuit determines a correction code for correcting a common-mode voltage of a differential input voltage based on a conversion end signal output from the voltage quantizer circuit. A common-mode voltage regulator circuit adjusts the common-mode voltage by adding or subtracting a correction voltage based on a correction code to or from the differential input voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-174228 filed on October 6, 2023, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device, such as a semiconductor device including an analog-to-digital converter.

[0004] The techniques listed below are disclosed.

[0005] [Non-Patent Document 1] “Single-Channel 1.25GS / s 6-Bit Loop-Unrolled Asynchronous SAR-ADC in 40nm-COM”, IEEE CICC 2010, Jiang Tao et al. Background Art

[0006] Non-patent document 1 describes an asynchronous "successive approximation register" - an "analog-to-digital converter" (SAR-ADC) capable of high-speed operation. The SAR-ADC includes as many comparators as the number of digital signal bits. When the comparison operation is completed, the comparator close to the most significant bit outputs an activation signal to the comparator close to the least significant bit. As a result, each comparator continuously performs the comparison (approximation) operation in the order from the most significant bit to the least significant bit. Summary of the invention

[0007] For example, a system that continuously defines each bit of a digital signal while repeatedly using one comparator is known as a typical configuration of a SAR-ADC. However, the system needs to reset the comparator for each repetition, and therefore, it may be difficult to achieve high-speed operation. Therefore, for example, as described in Non-Patent Document 1, the use of an asynchronous SAR-ADC is considerable, especially a SAR-ADC that does not require loop expansion for repeated operation because it includes as many comparators as the bits of a digital signal.

[0008] However, using this type of asynchronous SAR-ADC risks causing the comparison time of the comparator to be long due to the influence of the common-mode differential input voltage. Therefore, there is a risk that the speed of the analog-to-digital converter will not be sufficient.

[0009] The embodiments described below are made under such circumstances, and other objects and novel features will be apparent from the description of the specification and the accompanying drawings.

[0010] A semiconductor device according to an embodiment includes: a voltage quantizer circuit that converts a differential input voltage into a digital signal having a plurality of bits in each sampling period and asserts a conversion end signal when the conversion operation is completed; a correction code determination circuit that receives the conversion end signal from the voltage quantization circuit as its input output; and a common mode voltage regulator circuit that adjusts the common mode voltage of the differential input voltage. The voltage quantizer circuit includes: a first comparator that includes a first input transistor that receives the differential input voltage as its input and defines the value of the first bit of the digital signal; and a second comparator that includes a second input transistor that is different from the first input transistor and defines the value of the second bit of the digital signal. The correction code determination circuit determines a correction code for correcting the common mode voltage of the differential input voltage based on the conversion end signal output from the voltage quantizer circuit. The common mode voltage regulator circuit adjusts the common mode voltage by adding or subtracting a correction voltage based on the correction code to the differential input voltage.

[0011] By using the semiconductor device according to the embodiment, the speed of the analog-to-digital converter can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram showing an exemplary schematic configuration of a semiconductor device according to a first embodiment.

[0013] Figure 2A is shown as Figure 1 A circuit block diagram of an exemplary configuration of a voltage quantizer circuit of the main body of an analog-to-digital converter.

[0014] Figure 2B It is shown Figure 2A A circuit diagram of an exemplary schematic configuration of a voltage quantizer circuit.

[0015] Figure 3 2 is a circuit diagram showing an exemplary configuration of the relationship of clock signals in the voltage quantizer circuit of FIG. 2 .

[0016] Figure 4 Figure 2 and Figure 3 A timing diagram of an exemplary normal operation of the voltage quantizer circuit.

[0017] Figure 5A It is shown Figure 2A A circuit diagram of an exemplary configuration of each comparator.

[0018] Figure 5B is different from Figure 5A A circuit diagram of an exemplary configuration of each comparator.

[0019] Figure 6It is shown Figure 1 A circuit block diagram of an exemplary schematic configuration of an analog-to-digital conversion unit.

[0020] Figure 7 It is used to explain Figure 6 FIG. 1 is a diagram of an exemplary operation of a common-mode voltage regulator circuit.

[0021] Fig. 8A It is shown Figure 6 A circuit diagram of an exemplary configuration of a common-mode voltage regulator circuit.

[0022] Figure 8B It is shown Fig. 8A FIG. 1 is a timing diagram illustrating an exemplary operation of the control logic.

[0023] Fig.9A It is shown Figure 6 Flowchart of exemplary processing contents of a correction code determination circuit.

[0024] Fig. 9B is different from Fig.9A A flowchart of exemplary processing contents of FIG.

[0025] Fig. 10A It is shown in the use Fig.9A or Fig. 9B FIG. 4 is a diagram of exemplary results of correction code determination in the case of a flowchart.

[0026] Fig. 10B is different from Fig. 10A Figure 2 shows an exemplary result of

[0027] Fig.11A It is shown Figure 6 A circuit diagram of an exemplary configuration of a comparator group.

[0028] Fig. 11B It is used to explain Fig.11A Circuit diagrams of various modified examples.

[0029] Fig. 12A It shows that the generated Figure 6 A method of sampling a clock signal in FIG. 1 and a diagram of an exemplary operation timing of a correction code determination circuit based on the method.

[0030] Fig. 12B It shows that the generated Figure 6 A method of sampling a clock signal in FIG. 1 and a diagram of an exemplary operation timing of a correction code determination circuit based on the method.

[0031] Fig.13 FIG. 1 is a diagram showing a semiconductor device according to a second embodiment. Figure 1 A circuit block diagram of an exemplary schematic configuration of an analog-to-digital conversion unit.

[0032] Fig.14 is a diagram showing a semiconductor device according to a third embodiment. Figure 6 or Fig.13 A circuit diagram of an exemplary configuration of a comparator group.

[0033] Fig.15 is a diagram showing a semiconductor device according to a third embodiment. Figure 6 or Fig.13 Schematic diagram of an exemplary transformation of the differential input voltage.

[0034] Fig.16 It is shown Fig.14 FIG. 1 is a timing diagram of an exemplary variation of the common-mode voltage of a comparator group.

[0035] Fig.17A is shown in simple use Figure 2A Schematic diagram of an exemplary problem in the case of a voltage quantizer circuit.

[0036] Fig. 17B is shown in simple use Figure 2A Schematic diagram of an exemplary problem in the case of a voltage quantizer circuit.

[0037] Fig.18 It is shown in Figure 2A Schematic diagram of an exemplary relationship between a common-mode voltage of a differential input voltage and a comparison time in a voltage quantizer circuit.

[0038] Fig.19 It is shown in Figure 2A A schematic diagram of an exemplary operation of a voltage quantizer circuit in the context of a designed configuration of a comparator group.

[0039] Fig. 20A is used to explain Fig.19 A diagram of the influence of the initial value of the common-mode voltage on the system under assumptions.

[0040] Fig. 20B is used to explain Fig.19 A diagram of the influence of the initial value of the common-mode voltage on the system under assumptions.

[0041] Fig.21 It is shown in Fig. 20A and Fig. 20B A timing diagram of an exemplary operation of the voltage quantizer circuit in the case where the common-mode voltage is inappropriate. DETAILED DESCRIPTION

[0042] In the embodiments described below, for convenience, when necessary, the present invention will be described in multiple parts or embodiments. However, unless otherwise stated, these parts or embodiments are not independent of each other, and one relates to all or part of another, as a modified example, detail or supplementary description thereof. In addition, in the following embodiments, when the number of elements (including number of pieces, value, number, range, etc.) is mentioned, unless otherwise stated, the number of elements is not limited to a specific number, or except that the number is obviously limited to a specific number in principle. Numerical values ​​greater than or less than a specified numerical value also apply.

[0043] Furthermore, in the embodiments described below, it goes without saying that, unless otherwise specified, components (including element steps) are not always indispensable, or except for the case where the components are obviously indispensable in principle. Similarly, in the embodiments described below, when referring to the shapes of components, their positional relationships, etc., substantially similar and similar shapes, etc. are included therein unless otherwise specified, or except for the case where it can be imagined that they are obviously excluded in principle. The same is true for the above-mentioned numerical values ​​and ranges.

[0044] Although not particularly limited, circuit elements configuring the functional blocks according to the embodiments are formed on a semiconductor substrate made of single crystal silicon or the like by integrated circuit technologies such as the well-known complementary MOS (CMOS) transistor. In the embodiments, it is noted that a metal oxide semiconductor field effect transistor (MOSFET, also referred to as a MOS transistor) is used as an exemplary metal insulator semiconductor field effect transistor (MISFET). However, non-oxide films are not excluded as gate insulating films. In addition, in the embodiments, an n-channel MOS transistor is referred to as an nMOS transistor, and a p-channel MOS transistor is referred to as a pMOS transistor.

[0045] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Note that in all the drawings used to describe the embodiments, components having the same functions are represented by the same reference numerals, and their repeated description will be omitted. In addition, unless particularly required in the following embodiments, the description of the same or similar parts will not be repeated in principle.

[0046] (First embodiment)

[0047] <Configuration of semiconductor devices>

[0048] Figure 1 is a block diagram showing an exemplary schematic configuration of a semiconductor device according to a first embodiment. Figure 1 The semiconductor device DEV shown is a system on chip (SoC) or the like, which is used for a digital key of a vehicle, for example, and includes a wireless communication function based on the ultra-wideband (UWB) standard. In fact, the semiconductor device DEV is not limited to Figure 1configuration, and only has to include at least the analog-to-digital converter ADC described later.

[0049] Figure 1 The semiconductor device DEV shown includes a processor PRC, a memory MEM, a peripheral circuit PERI, a UWB digital circuit UWB_D, a UWB analog circuit UWB_A and a bus BS. The bus BS connects the processor PRC, the memory MEM, the peripheral circuit PERI and the UWB digital circuit UWB_D to each other. The UWB analog circuit UWB_A is connected to the UWB digital circuit UWB_D.

[0050] The processor PRC is a central processing unit (CPU), a graphics processing unit (GPU), etc. The memory MEM is made of a combination of a volatile memory such as a static RAM (SRAM) and a non-volatile memory such as a flash memory or a magnetoresistive RAM (MRAM). The peripheral circuit PERI includes various communication interfaces such as a controller area network (CAN) interface or a serial peripheral interface (SPI).

[0051] The UWB digital circuit UWB_D is also used as a baseband processing circuit, responsible for processing in the baseband based on the UWB standard. The processing in the baseband includes, for example, encoding / decoding, modulation / demodulation, encryption / decryption, etc. The UWB analog circuit UWB_A is also used as a high-frequency circuit, responsible for processing in the high-frequency band based on the UWB standard. The UWB analog circuit UWB_A includes a high-frequency transmitting circuit RF_TX configured to process a transmitted signal, a high-frequency receiving circuit RF_RX configured to process a received signal, and a clock generator circuit CKG.

[0052] The clock generator circuit CKG generates and supplies various clock signals used in the high frequency band to the high frequency transmission circuit RF_TX and the high frequency reception circuit RF_RX. The high frequency transmission circuit RF_TX includes a power amplifier, etc. The high frequency transmission circuit RF_TX up-converts the transmission baseband signal output from the UWB digital circuit UWB_D into a high frequency transmission signal made of short pulses by using the clock signal output from the clock generator circuit CKG, and transmits the high frequency transmission signal to an antenna not shown.

[0053] The high-frequency receiving circuit RF_RX includes a low-noise amplifier LNA, a mixer unit MIXU, a filter unit FLTU, an analog-to-digital conversion unit ADCU, etc. The low-noise amplifier LNA amplifies the high-frequency receiving signal received by the antenna not shown. The mixer unit MIXU includes, for example, a plurality of mixer circuits, and down-converts the output signal from the low-noise amplifier LNA into a baseband receiving signal by using a clock signal output from the clock generator circuit CKG. The filter unit FLTU includes a plurality of filter circuits, and limits the baseband receiving signal output from the mixer unit MIXU to, for example, a frequency band of about 500 MHz.

[0054] The analog-to-digital conversion unit ADCU includes a plurality of analog-to-digital converters ADC. For example, the analog-to-digital converter ADC is an asynchronous SAR-ADC. The analog-to-digital converter ADC converts the analog input voltage VA output from the filter unit FLTU into an m-bit digital signal D such as a 6-bit digital signal. Then, the analog-to-digital converter ADC outputs the obtained digital signal D as digital data of a baseband reception signal to the UWB digital circuit UWB_D.

[0055] In this example, the analog-to-digital conversion unit ADCU includes two analog-to-digital converters ADC to perform conversion into a "2×m" bit digital signal D. The analog-to-digital converter ADC is supplied with a master clock signal CKm from a clock generator circuit CKG. The analog-to-digital converter ADC generates a sampling clock signal of, for example, 1 GHz or 2 GHz based on the master clock signal CKm, and operates in synchronization with the sampling clock signal.

[0056] <Analog-to-Digital Converter>

[0057] Figure 2A is shown as Figure 1 A circuit block diagram of an exemplary configuration of a voltage quantizer circuit of the main body of an analog-to-digital converter. Figure 2B It is shown Figure 2A A circuit diagram of an exemplary schematic configuration of a voltage quantizer circuit. Figure 3 2 is a circuit diagram showing an exemplary configuration of the relationship of clock signals in the voltage quantizer circuit of FIG. 2 . Figure 4 Figure 2 and Figure 3 A timing diagram of an exemplary normal operation of the voltage quantizer circuit.

[0058] Figure 2A The voltage quantizer circuit QCT is used as Figure 1The main body of the analog-to-digital converter ADC, in particular, the asynchronous loop expander SAR-ADC. The voltage quantizer circuit QCT includes a sampling switch SSW, a digital-to-analog converter CDAC, and "m" comparators, in this example, the "m" comparators are six comparators CMP[0] to CMP[5]. For the differential input nodes NinP and NinN, in particular, for the conversion capacitor in the digital-to-analog converter CDAC, the sampling switch SSW samples the positive side analog input voltage VApp and the negative side analog input voltage VAn as differential signals during the assertion period of the sampling clock signal CKs.

[0059] The comparators CMP[0] to CMP[5] respectively define the values ​​of the bits of the digital signals, in other words, the values ​​of the positive side digital signals Dp[0] to Dp[5] and the values ​​of the negative side digital signals Dn[0] to Dn[5] on the opposite side of the positive side digital signals. The digital-to-analog converter CDAC adds or subtracts a predetermined voltage to or from the differential input voltages INp and INn of the differential input nodes NinP and NinN according to the values ​​of the digital signals Dp[0] to Dp[5] and Dn[0] to Dn[5]. As a result, the digital-to-analog converter CDAC updates the differential input voltages INp and INn.

[0060] Specifically, the digital-to-analog converter CDAC is, for example, Figure 2B The capacitor type shown. The digital-to-analog converter CDAC includes five capacitors Cp[1] to Cp[5] used as conversion capacitors, a virtual capacitor CpD, five capacitors Cn[1] to Cn[5] used as conversion capacitors, and a virtual capacitor CnD. However, the digital-to-analog converter is not limited to the capacitor type, but can be, for example, a resistor type. Alternatively, the virtual capacitors CpD and CnD can be external capacitors.

[0061] One end of each of the five capacitors Cp[1] to Cp[5] and the virtual capacitor CpD is connected to the positive side differential input node NinP. The positive side digital signals Dp[1] to Dp[5] are applied to the other ends of the five capacitors Cp[1] to Cp[5], respectively. The other end of the virtual capacitor CpD is fixed at the ground power supply voltage GND.

[0062] Similarly, one end of each of the five capacitors Cn[1] to Cn[5] and the virtual capacitor CnD is connected to the negative side differential input node NinN. Negative side digital signals Dn[1] to Dn[5] are applied to the other ends of the five capacitors Cn[1] to Cn[5], respectively. The other end of the virtual capacitor CnD is fixed at the ground power supply voltage GND.

[0063] Each capacitor Cp[k] (k=1, 2, ..., 5) has a value of, for example, "2 k-1×Cu”. Similarly, each capacitor Cn[k] also has a capacitance of “2 k-1 ×Cu”. Based on the range of analog input voltages VApp and VAn, etc., the capacitance values ​​of virtual capacitors CpD and CnD are defined to be the same value.

[0064] Each of the comparators CMP[0] to CMP[5] compares the zero voltage and the voltage difference "INp-INn" between the positive side differential input voltage INp and the negative side differential input voltage INn according to the amplitude relationship. At this time, each comparator CMP[i] (i=5, 4, ..., 0) starts the comparison operation in response to the assertion of the clock signal CK[i]. When the comparison operation is completed, the comparator CMP[i] asserts the clock signal CK[I-1] of the next comparator CMP[I-1].

[0065] As a result, the comparison operation is continuously performed in the order from comparator CMP[5] to comparator CMP[0]. As a result of the comparison, each comparator CMP[i] outputs a positive side digital signal Dp[i] and a negative side digital signal Dn[i] on the opposite side of the positive side digital signal. Conversely, for each completion of the comparison operation of each comparator CMP[i], the digital-to-analog converter CDAC respectively adds or subtracts a phase difference of “1 / 2” to or from the differential input voltages INp and INn based on the comparison result digital signals Dp[i] and Dn[i]. n " to update the differential input voltages INp and INn.

[0066] The next comparator CMP[i-1] performs a comparison operation on the differential input voltages INp and INn updated as described above. Therefore, the analog-to-digital converter ADC can convert the analog input voltages VApp and VAn (in other words, "VAp-VAn") used as differential signals into 6-bit digital signals Dp[0] to Dp[5].

[0067] like Figure 4 As shown, more specifically, since the sampling clock signal CKs is first input, the positive side differential input voltage INp is defined as the level of the positive side analog input voltage VApp, and the negative side differential input voltage INn is defined as the level of the negative side analog input voltage VAn. Subsequently, the clock signal CK[5] is asserted from the level "L" to the level "H" by a logic circuit not shown. As a result, the comparator CMP[5] starts the comparison operation.

[0068] In the comparison operation, the comparator CMP[5] shifts one of the digital signals Dp[5] and Dn[5] from, for example, a level "L" to a level "H" based on the magnitude relationship between the zero voltage and the voltage difference "INp-INn" between the differential input voltages INp and INn. When the comparison operation is completed, the comparator CMP[5] asserts the clock signal CK[4].

[0069] In contrast, in the digital-to-analog converter CDAC, in response to one of the digital signals Dp[5] and Dn[5] shifting to level "H", the charge of the capacitor Cp[5] or Cn[5] is redistributed. Specifically, for example, via control logic not shown, one of the digital signals Dp[5] and Dn[5] shifts from level "L" to level "H", while the other shifts from level "H" to level "L". Thus, one / the other of the differential input nodes NinP and NinN is charged / discharged to add / subtract a predetermined voltage "Vref" to / from the differential input voltages INp and INn, in other words, the voltage difference "INp-INn". Note that the magnitude of "Vref" is adjusted by the capacitance values ​​of the virtual capacitors CpD and CnD.

[0070] When the differential input voltages INp and INn are updated as described above, the comparator CMP[4] starts a comparison operation in response to the assertion of the clock signal CK[4]. In the comparison operation, the comparator CMP[4] shifts one of the digital signals Dp[4] and Dn[4] from the level "L" to the level "H" based on the magnitude relationship between the zero voltage and the voltage difference "INp-INn". Then, when the comparison operation is completed, the comparator CMP[4] asserts the clock signal CK[3].

[0071] In contrast, in the digital-to-analog converter CDAC, in response to one of the digital signals Dp[4] and Dn[4] shifting to the level "H", the charges in the capacitors Cp[4] and Cn[4] are redistributed. Specifically, one of the digital signals Dp[4] and Dn[4] shifts from the level "L" to the level "H", and the other shifts from the level "H" to the level "L". Therefore, a predetermined voltage "Vref / 2" is added / subtracted from the differential input voltages INp and INn, in other words, a voltage difference "INp-INn".

[0072] Subsequently, the same process is continuously performed in order to the comparator CMP[0], while the predetermined voltage is continuously changed to "Vref / 4", "Vref / 8", ... The comparator CMP[0] outputs the digital signals Dp[0] and Dn[0] in the comparison operation, and asserts the clock signal CKfin when the comparison operation is completed. Here, Figure 3As shown, the clock signal CKfin is input to a flip-flop circuit FFed additionally provided in the voltage quantizer circuit QCT. The flip-flop circuit FFed outputs a conversion end signal CED by latching the clock signal CKfin in response to the sampling clock signal CKs.

[0073] The conversion end signal CED indicates whether the analog-to-digital converter ADC has successfully completed the conversion operation. That is, when the conversion end signal CED is asserted, in other words, in this example, when the shift is to the level "H", the conversion operation has been successfully completed. In response to the sampling clock signal CKs, the analog input voltages VAP and VAn are sampled again. In addition, the clock signals CK[5] to CK[0] and CKfin are negated to the level "L", and the digital signals Dp[1] to Dp[5] and Dn[1] to Dn[5] are returned to the initial values.

[0074] <Comparator Details>

[0075] Figure 5A It is shown Figure 2A A circuit diagram of an exemplary configuration of each comparator. Figure 5A An n-channel comparator CMPn including n-channel transistors used as initial input transistors (first input transistor and second input transistor) is shown. Figure 5A The illustrated comparator CMPn is also referred to as a dynamic comparator, and operates with low power consumption in synchronization with the positive-side clock signal CKp[i].

[0076] The comparator CMPn includes an amplifier circuit AMPn, a latch circuit unit LTUn, and an OR gate OR1. The amplifier circuit AMPn differentially amplifies the differential input voltages INp and Inn. The latch circuit unit LTUn outputs a positive side digital signal Dp[i] and a negative side digital signal Dn[i] by latching the output signal from the amplifier circuit AMPn. The OR gate OR1 generates the next positive side clock signal CKp[i-1] by performing an OR operation on the digital signals Dp[i] and Dn[i].

[0077] Specifically, the amplifier circuit AMPn includes nMOS transistors MN0a, MN0b and MN1 and pMOS transistors MP0a and MP0b. The nMOS transistors MN0a and MN0b are initial input transistors (first input transistor and second input transistor) configuring a differential pair. The positive side differential input voltage INp / negative side differential input voltage INn are input to the nMOS transistors MN0a / MN0b, respectively.

[0078] In the period when the clock signal CKp[i] is at the level "L", the pMOS transistors MP0a and MP0b precharge the initial output nodes N0n and N0p serving as the drains of the nMOS transistors MN0a and MN0b to the power supply voltage VDD. In the period when the clock signal CKp[i] is at the level "H", the nMOS transistor MN1 connects the sources of the nMOS transistors MN0a and MN0b to the ground power supply voltage GND to activate the amplifier circuit AMPn.

[0079] The latch circuit unit LTUn includes nMOS transistors MN2a, MN3a, MN2b and MN3b, pMOS transistors MP2a and MP2b, and a CMOS latch circuit CLT. The CMOS latch circuit CLT includes a CMOS inverter Iva made of a pMOS transistor MP4a and an nMOS transistor MN4a, and a CMOS inverter IVb made of a pMOS transistor MP4b and an nMOS transistor MN4b.

[0080] The input terminal of one of the CMOS inverters IVa and IVb is connected to the output terminal of the other. That is, the latch node N1p used as the output node of the CMOS inverter IVa is also used as the input node of the CMOS inverter IVb. Similarly, the latch node N1n used as the output node of the CMOS inverter IVb is also used as the input node of the CMOS inverter IVa. The positive side digital signal Dp[i] is output to the latch node N1p, and the negative side digital signal Dn[i] is output to the latch node N1n.

[0081] The pMOS transistor MP2a and the nMOS transistor MN2a configure a CMOS inverter. The negative side output signal at the output node N0n is input into the CMOS inverter, and the high potential side power supply voltage of the CMOS inverter IVa in the CMOS latch circuit CLT is defined according to the input level. Similarly, the pMOS transistor MP2b and the nMOS transistor MN2b configure a CMOS inverter. The positive side output signal at the output node N0p is input into the CMOS inverter, and the high potential side power supply voltage of the CMOS inverter IVb in the CMOS latch circuit CLT is defined according to the input level.

[0082] The negative side output signal at the output node N0n is input into the nMOS transistor MN3a, and the positive side output signal at the output node N0p is input into the nMOS transistor MN3b. When receiving the level "H" as its input, the nMOS transistor MN3a connects the latch node N1p to the ground power supply voltage GND. Similarly, when receiving the level "H" as its input, the nMOS transistor MN3b connects the latch node N1n to the ground power supply voltage GND.

[0083] The operation performed by the comparator CMPn as described above is classified into an operation in a reset period in which the clock signal CKp[i] is at a level "L", and an operation in a comparison period after the clock signal CKp[i] shifts from a level "L" to a level "H". In the reset period, the nMOS transistor MN1 is turned off, and the pMOS transistors MP0a and MP0b are turned on, so that the output nodes N0n and N0p are both precharged to a level "H". Therefore, the nMOS transistors MN3a and MN3b are turned on, so that the digital signals Dp[i] and Dn[i] are both at a level "L". The clock signal CKp[i-1] output from the OR gate OR1 is also at a level "L".

[0084] In the comparison period after this period, the nMOS transistor MN1 is turned on, and the pMOS transistors MP0a and MP0b are turned off. As a result, in the amplifier circuit AMPn, differential amplification is performed by the input transistors (MN0a and MN0b) used as a differential pair according to the voltage difference "INp-INn" between the differential input voltages INp and INn. For example, in the case of "INp>INn", the potential of the output node N0n drops from the level "H" to the level "L" faster than the potential of the output node N0p.

[0085] Therefore, the power supply voltage VDD is supplied as a high potential side power supply voltage to the CMOS inverter IVa in the CMOS latch circuit CLT via the CMOS inverter made of the pMOS transistor MP2a and the nMOS transistor MN2a. Conversely, the ground power supply voltage GND is supplied as a high potential side power supply voltage to the CMOS inverter IVb in the CMOS latch circuit CLT via the CMOS inverter made of the pMOS transistor MP2b and the nMOS transistor MN2b.

[0086] As a result, the pMOS transistor MP4a is turned on, and the digital signal Dp[i] at the latch node N1p shifts from the level "L" to the level "H". In contrast, for the CMOS inverter IVb in the CMOS latch circuit CLT, the ground power supply voltage GND is supplied as the high potential side power supply voltage, and therefore, the digital signal Dn[i] at the latch node N1n is held at the level "L". When the digital signal Dp[i] shifts to the level "H", in other words, when the comparison operation is completed, the clock signal CKp[i-1] output from the OR gate OR1 is asserted to the level "H".

[0087] Figure 5B is different from Figure 5A A circuit diagram of an exemplary configuration of each comparator. Figure 5A different, Figure 5BFIG. 1 shows a p-channel comparator CMPp including a p-channel transistor as an initial input transistor (ie, a second input transistor or a first input transistor). Figure 5A different, Figure 5B The illustrated comparator CMPp operates in synchronization with the negative-side clock signal CKn[i].

[0088] The comparator CMPp includes an amplifier circuit AMPp, a latch circuit unit LTUp, and an AND gate AD1. The amplifier circuit AMPp and the latch circuit unit LTUp are configured to Figure 5A Similarly, the AND gate AD1 generates the next negative-side clock signal CKn[i-1] by performing an AND operation on the digital signals Dp[i] and Dn[i] output from the latch circuit unit LTUp.

[0089] Specifically, the amplifier circuit AMPp and the latch circuit unit LTUp are configured so that Figure 5A In the configuration of AMPp, the power supply voltage VDD and the ground power supply voltage GND are exchanged, and the nMOS transistor and the pMOS transistor are exchanged at the same time. Therefore, the amplifier circuit AMPp includes pMOS transistors MP5a, MP5b and MP6 and nMOS transistors MN5a and MN5b. The pMOS transistor MP5a or MP5b is the initial input transistor (second input transistor or first input transistor) of the configuration differential pair. The positive side differential input voltage INp / negative side differential input voltage INn is input to the pMOS transistor MP5a / MP5b, respectively.

[0090] The nMOS transistors MN5a and MN5b precharge the initial output nodes N5n and N5p to the ground power supply voltage GND in a period in which the clock signal CKn[i] is at the level “H”, in other words, in a period in which the clock signal CKp[i] is at the level “L”. The pMOS transistor MP6 connects the sources of the pMOS transistors MP5a and MP5b to the power supply voltage VDD to activate the amplifier circuit AMPp in a period in which the clock signal CKn[i] is at the level “L”, in other words, in a period in which the clock signal CKp[i] is at the level “H”.

[0091] The latch circuit unit LTUp includes pMOS transistors MP7a, MP8a, MP7b, and MP8b, nMOS transistors MN7a and MN7b, and a CMOS latch circuit CLT. The CMOS latch circuit CLT includes a CMOS inverter Iva made of a pMOS transistor MP9a and an nMOS transistor MN9a, and a CMOS inverter IVb made of a pMOS transistor MP9b and an nMOS transistor MN9b.

[0092] The latch node N6p used as the output node of the CMOS inverter IVa is also used as the input node of the CMOS inverter IVb. Similarly, the latch node N6n used as the output node of the CMOS inverter IVb is also used as the input node of the CMOS inverter IVa. The positive side digital signal Dp[i] is output to the latch node N6p, and the negative side digital signal Dn[i] is output to the latch node N6n.

[0093] The pMOS transistor MP7a and the nMOS transistor MN7a configure a CMOS inverter. The negative side output signal at the output node N5n is input into the CMOS inverter, and the low potential side power supply voltage of the CMOS inverter IVa in the CMOS latch circuit CLT is defined according to the input level. Similarly, the pMOS transistor MP7b and the nMOS transistor MN7b configure a CMOS inverter. The positive side output signal at the output node N0p is input into the CMOS inverter, and the low potential side power supply voltage of the CMOS inverter IVb in the CMOS latch circuit CLT is defined according to the input level.

[0094] The negative side output signal at the output node N5n is input into the pMOS transistor MP8a, and the positive side output signal at the output node N5p is input into the pMOS transistor MP8b. When receiving the level "L" as its input, the pMOS transistor MP8a connects the latch node N6p to the power supply voltage VDD. Similarly, when receiving the level "L" as its input, the pMOS transistor MP8b connects the latch node N6n to the power supply voltage VDD.

[0095] Figure 5B The operation of comparator CMPp is almost similar to Figure 5A The difference between them is that in the reset period, both digital signals Dp[i] and Dn[i] are at the "H" level. In the comparison period, one of the digital signals Dp[i] and Dn[i] shifts from the "H" level to the "L" level. Therefore, the negative side clock signal CKn[i-1] output from the AND gate AD1 is asserted from the "H" level to the "L" level. In other words, the positive side clock signal CKp[i-1] is asserted from the "L" level to the "H" level, similar to Figure 5A situation.

[0096] <Problems with voltage quantizer circuit>

[0097] For example, UWB needs to process signals in the 500MHz frequency band. Figure 1 A high conversion speed of 1 GS / s or higher is required in an analog-to-digital converter ADC. Figure 2AIn the case of the voltage quantizer circuit QCT shown, such conversion speed requirements can be met ideally. However, in practice, there is a risk of preventing high speed due to the influence of the common mode voltage of the differential input voltage.

[0098] Fig.17A and Fig. 17B is shown in simple use Figure 2A Schematic diagram of an exemplary problem in the case of a voltage quantizer circuit. Fig.17A It is shown that all comparators CMP[0] to CMP[5] in the voltage quantizer circuit QCT are composed of Figure 5B The p-channel comparator CMPp is made for the exemplary operation of the case. Fig. 17B It is shown that all comparators CMP[0] to CMP[5] in the voltage quantizer circuit QCT are composed of Figure 5A An exemplary operation of the case where the n-channel comparator CMPn is made.

[0099] like Fig.17A As shown, when only the p-channel comparator CMPp is used, for each comparison operation, the common mode voltage of the differential input voltage is increased by the amplifier circuit AMPp in the comparator CMPp. Specifically, in response to the shift of the negative side clock signal CKn to the level "L", the current output from the power supply voltage VDD flows to the pMOS transistors MP5a and MP5b via the pMOS transistor MP6. As a result, an upward kickback phenomenon can be caused in the differential input voltages INp and INn via the gate-source capacitance or the gate-drain capacitance of the pMOS transistors MP5a and MP5b. The common mode voltage is defined as "(INp+INn) / 2".

[0100] On the contrary, Fig. 17B As shown in FIG. 1 , when only the n-channel comparator CMPn is used, the common mode voltage of the differential input voltage is lowered by the amplifier circuit AMPn in the comparator CMPn for each comparison operation. Specifically, in response to the shift of the positive-side clock signal CKp to the level "H", the current output from the drains of the nMOS transistors MN0a and MN0b precharged with the power supply voltage VDD flows to the ground power supply voltage GND via the nMOS transistor MN1. As a result, a downward kickback phenomenon may be caused in the differential input voltages INp and INn via the gate-source capacitance or the gate-drain capacitance of the nMOS transistors MN0a and MN0b.

[0101] Fig.18 It is shown in Figure 2ASchematic diagram of an exemplary relationship between the common mode voltage of the differential input voltage and the comparison time in the voltage quantizer circuit of FIG. The lower the common mode voltage, the higher the driving capability of the pMOS transistors MP5a and MP5b used as the input transistors in the amplifier circuit AMPp, and the higher the operating speed thereof. Conversely, the higher the common mode voltage, the higher the driving capability of the nMOS transistors MN0a and MN0b used as the input transistors in the amplifier circuit AMPn, and the higher the operating speed thereof.

[0102] Results, such as Fig.18 As shown in Figure 10, the comparison time of comparators CMPp and CMPn depends largely on the common mode voltage. Specifically, the higher the common mode voltage, the longer the comparison time of comparator CMPp, as shown in property 10p. Conversely, the lower the common mode voltage, the longer the comparison time of comparator CMPn, as shown in property 10n. Therefore, when only one type of comparator is used, there is a problem due to Fig.17A or Fig. 17B The risk of excessively long comparison times due to increasing or decreasing common-mode voltage is shown.

[0103] Fig.19 It is shown in Figure 2A A schematic diagram of an exemplary operation of a voltage quantizer circuit in the context of a designed configuration of a comparator group. Fig.19 An exemplary operation is shown in which the p-channel comparator CMPp and the n-channel comparator CMPn are alternately arranged as comparators CMP[5] to CMP[0] in the voltage quantizer circuit QCT. Since the p-channel comparator CMPp and the n-channel comparator CMPn are alternately arranged as described above, the change in the common mode voltage can be eliminated. Therefore, an excessively long comparison time can be prevented.

[0104] Figure 2A The voltage quantizer circuit QCT is a system that continuously operates a plurality of comparators CMP[5] to CMP[0]. Therefore, the conversion time of the analog-to-digital converter ADC is occupied by the comparison time of the comparators CMP[5] to CMP[0]. Fig.19 The system can suppress the change of common mode voltage to some extent, thus preventing the phenomenon of too long comparison time and ultimately too long conversion time of analog-to-digital converter ADC. However, in order to further reduce the conversion time of analog-to-digital converter ADC, in addition to suppressing the change of common mode voltage caused by comparison operation, the initial value of common mode voltage provided before starting a series of comparison operations is also important.

[0105] Fig. 20A and Fig. 20B is used to explain Fig.19 The influence of the initial value of the common-mode voltage on the system is shown in the figure. Fig. 20AAs shown in FIG. 1 , the initial value of the common mode voltage has an appropriate range of 11. That is, Fig. 20B As shown, in Fig.19 In the assumption of the system, there is a common mode voltage with the shortest comparison time. The appropriate range 11 is a range where the common mode voltage is concentrated with the shortest comparison time, and in which the comparison time is in a range of the target value or less. In addition, the appropriate range 11 is Fig.16 The range around the intersection between the two attributes 10n and 10p in .

[0106] Fig.21 It is shown in Fig. 20A and Fig. 20B A timing diagram of an exemplary operation of the voltage quantizer circuit when the common mode voltage is not appropriate. Figure 4 Different, in Fig.21 In the example of , the clock signal CK[0] of the last comparator CMP[0] is not asserted due to the increase of the comparison time. Therefore, the conversion end signal CED is not asserted either. That is, the conversion operation of the analog-to-digital converter ADC is not completed within the period of the sampling clock signal CKs.

[0107] As described above, even when the change in the common mode voltage of the differential input voltage is suppressed, if the initial value of the common mode voltage is inappropriate, there is a risk that the speed of the analog-to-digital converter ADC cannot be sufficiently increased. If only any one of the two types of comparators CMPp and CMPn is used, an appropriate common mode voltage can be easily generated. That is, when only the p-channel comparator CMPp is used, the common mode voltage is low, and when only the n-channel comparator CMPn is used, the common mode voltage is high. However, when the common mode voltage is high, the common mode voltage is high. Fig.19 When two types of comparators CMPp and CMPn are used as shown, it is not easy to generate a proper common-mode voltage.

[0108] One reason for this is that the appropriate range 11 of the common-mode voltage is very narrow. Another reason is that the common-mode voltage is essentially defined by the external circuitry of the analog-to-digital converter ADC, such as Figure 1 In this case, it is necessary to adjust the external circuit of the analog-to-digital converter ADC so as to generate an appropriate common-mode voltage in the analog-to-digital converter ADC. As a result, the design of the semiconductor device may become complicated. Therefore, it is advantageous to use the following system according to this embodiment.

[0109] <Schematic Configuration of Analog-to-Digital Conversion Unit>

[0110] Figure 6 It is shown Figure 1 A circuit block diagram of an exemplary schematic configuration of an analog-to-digital conversion unit. Figure 6The analog-to-digital conversion unit ADCU includes an analog-to-digital converter ADC and a correction code determination circuit CDCT. Figure 2A and Figure 3 In addition to the voltage quantizer circuit QCT shown, the analog-to-digital converter ADC also includes a common-mode voltage regulator circuit CMCT.

[0111] Based on the sampling clock signal CKs, the voltage quantizer circuit QCT converts the differential input voltages INp and INn into m-bit digital signals, such as 6-bit digital signals Dp[5:0] and Dn[5:0], at each sampling period. Then, when the conversion operation is completed, the voltage quantizer circuit QCT asserts the conversion end signal CED.

[0112] The correction code determination circuit CDCT is connected to the voltage quantization circuit QCT and receives the conversion end signal CED from the voltage quantization circuit QCT as its input. Note that the term "connection" described in the specification refers not only to physical connection but also to electrical connection. Based on the conversion end signal CED, the correction code determination circuit CDCT determines a plurality of bits for correcting the common mode voltage of the differential input voltages INp and INn, such as a 4-bit correction code CAL_CD[3:0] in this example.

[0113] Schematically, at this time, when a sampling period in which the conversion end signal CED is not asserted is detected, in other words, a sampling period in which the conversion operation is not completed is detected, the correction code determination circuit CDCT changes the correction code CAL_CD[3:0]. Then, the correction code determination circuit CDCT continuously changes the correction code CAL_CD[3:0] until a sampling period in which the conversion end signal CED is not asserted is not detected.

[0114] The common mode voltage regulator circuit CMCT is connected to the correction code determination circuit CDCT and the voltage quantizer circuit QCT. The common mode voltage regulator circuit CMCT adjusts the common mode voltage by adding or subtracting a correction voltage based on the correction code CAL_CD[3:0] to or from the differential input voltages INp and INn.

[0115] <Details of Common Mode Voltage Regulator Circuit>

[0116] Figure 7 It is used to explain Figure 6 FIG. 1 is a diagram of an exemplary operation of a common-mode voltage regulator circuit. Figure 7As shown, for example, based on the value of the correction code CAL_CD[3:0], the common mode voltage regulator circuit CMCT adds or subtracts a correction voltage "M" ("M" is an integer from 1 to 7) times greater than the unit voltage ΔV to the differential input voltage INp and INn. In this example, whether to add or subtract the correction voltage is defined by "1" / "0" of the correction code CAL_CD[3:0]. The amplitude "M×ΔV" of the correction voltage is defined based on the value of the correction code CAL_CD[2:0]. For example, "M=1" is defined when "CAL_CD[2:0]=001", and "M=7" is defined when "CAL_CD[2:0]=111".

[0117] Fig. 8A It is shown Figure 6 A circuit diagram of an exemplary configuration of a common-mode voltage regulator circuit. Figure 8B It is shown Fig. 8A FIG. 1 is a timing diagram illustrating an exemplary operation of the control logic. Fig. 8A The common mode voltage regulator circuit CMCT includes a plurality of capacitors Ccp[0] to Ccp[2] and Ccn[0] to Ccn[2] used as correction capacitors and connected to the differential input nodes NinP and NinN. The common mode voltage regulator circuit CMCT also includes a control logic LGC for controlling these correction capacitors.

[0118] Similar to the digital-to-analog converter CDAC, the common-mode voltage regulator circuit CMCT schematically redistributes the charges of the differential input nodes NinP and NinN by using a correction capacitor determined from among a plurality of correction capacitors based on the correction code CAL_CD[2:0]. As a result, the common-mode voltage regulator circuit CMCT adjusts the common-mode voltage of the differential input voltages INp and INn. Note that the common-mode voltage regulator circuit may not be a capacitor type but, for example, a resistor type. However, in terms of consumed power, etc., it is desirable to use a capacitor type.

[0119] One end of the positive side capacitors Ccp[0] to Ccp[2] is connected to the positive side differential input node NinP. Common shift signals CSF[0] to CSF[2] are applied to the other ends of the capacitors Ccp[0] to Ccp[2], respectively. Similarly, one end of the negative side capacitors Ccn[0] to Ccn[2] is connected to the negative side differential input node NinN. Common shift signals CSF[0] to CSF[2] are also applied to the other ends of the capacitors Ccn[0] to Ccn[2], respectively.

[0120] The capacitance values ​​of capacitors Ccp[0] to Ccp[2] differ by, for example, 2 kThat is, capacitors Ccp[0] and Ccn[0] both have a capacitance value of "Cc". In this case, capacitors Ccp[1] and Ccn[1] both have a capacitance value of "2×Cc", and capacitors Ccp[2] and Ccn[2] both have a capacitance value of "4×Cc".

[0121] The control logic LGC includes, for example, an XOR gate AD2 and an XOR gate ENR1. The XOR gate ENR1 receives the inverted sampling clock signal ( / CKs) and the correction code CAL_CD[3] for defining the sign of the correction voltage as its input, and outputs a trigger signal TG. The AND gate AD2 receives the correction code CAL_CD[2:0] and the trigger signal TG as its input, and outputs common shift signals CSF[0] to CSF[2]. That is, the number of AND gates AD2 is as many as the number of three bits.

[0122] like Figure 8B As shown, when the correction code CAL_CD[3] is "0", the XOR gate ENR1 responds to the rising of the inverted sampling clock signal ( / CKs), in other words, responds to the falling of the sampling clock signal CKs, and outputs the falling trigger signal TG. When the correction code CAL_CD[0] is "1", the AND gate AD2 responds to the falling of the trigger signal TG and shifts the common shift signal CSF[0] from the level "H" to the level "L". Therefore, the charges of the capacitors Ccp[0] and Ccn[0] are redistributed, and as shown in FIG. Figure 7 The unit voltage "ΔV" is shown to be subtracted from the common mode voltage, in other words, from the differential input voltages INp and INn.

[0123] On the contrary, when the correction code CAL_CD[3] is "1", the XOR gate ENR1 outputs a rising trigger signal TG in response to the rise of the inverted sampling clock signal ( / CKs). When the correction code CAL_CD[0] is "1", the AND gate AD2 shifts the common shift signal CSF[0] from the level "L" to the level "H" in response to the rise of the trigger signal TG. Therefore, the charges of the capacitors Ccp[0] and Ccn[0] are redistributed, and a unit voltage "ΔV" is added to the common mode voltage. Similarly, for example, when the two common shift signals CSF[0] and CSF[1] are shifted to the level "H", "(1+2)×ΔV" is added to the common mode voltage.

[0124] <Details of the correction code determination circuit>

[0125] Fig.9A It is shown Figure 6 Flowchart of exemplary processing contents of a correction code determination circuit. Fig. 9B is different from Fig.9AThe correction code determination circuit CDCT is configured to perform, for example, Fig.9A or Fig. 9B In the correction period included in the period in which the voltage quantizer circuit QCT does not perform normal operation, the foreground is executed. Fig.9A The correction period is included in, for example, an initial period of the voltage quantizer circuit QCT caused by the startup of the semiconductor device DEV, a standby period of the voltage quantizer circuit QCT, and the like.

[0126] exist Fig.9A In the process, first, the correction code determination circuit CDCT resets the correction code CAL_CD[3:0] to zero (step S101). Subsequently, the correction code determination circuit CDCT causes the voltage quantizer circuit QCT to sample the initial values ​​of the external analog input voltages VApp and VAn, such as "VAp-VAn=0V", to perform a conversion operation (step S102). Then, the correction code determination circuit CDCT saves information about whether the conversion end signal CED output from the voltage quantizer circuit QCT is asserted or remains negated, in other words, saves information about whether the conversion end signal CED is at level "H" or level "L" (step S103).

[0127] Next, the correction code determination circuit CDCT determines whether the information of the conversion end signal CED has been held for a preset "N" number of times ("N" is an integer of 2 or more) (step S104). When the number of times is less than N (step S104: No), the correction code determination circuit CDCT returns the process to step S102, and repeatedly performs the processes in steps S102 and S103. On the contrary, when the number of times reaches N (step S104: Yes), the correction code determination circuit CDCT determines whether the N pieces of information of the conversion end signal CED include one or more negative levels (step S105).

[0128] When the information does not include a negative level (step S105: No), the correction code determination circuit CDCT fixes the current value to the value of the correction code CAL_CD[3:0]. On the contrary, when the information includes any negative level (step S105: Yes), the correction code determination circuit CDCT increments (+1) the correction code CAL_CD[3:0] (step S106). Then, the correction code determination circuit CDCT returns the process to step S102 to acquire the information of the conversion end signal CED again N times, while reflecting the incremented correction code CAL_CD[3:0] on the common mode voltage regulator circuit CMCT.

[0129] In the case of "No" in step S105, the value of the correction code CAL_CD[3:0] that has been fixed is applied to the subsequent normal operation. Figure 8B It can be seen that, for example, after the external analog input voltages VAP and VAn are sampled in the differential input nodes NinP and NinN in response to the sampling clock signal CKs, the common mode voltage of the differential input voltages INp and INn is immediately regulated.

[0130] In contrast, during a period in which the voltage quantizer circuit QCT performs normal operation, Fig. 9B The process operates in the background. Fig. 9B In the embodiment of the present invention, first, the correction code determination circuit CDCT acquires information on whether the conversion end signal CED output from the voltage quantizer circuit QCT has been asserted or remains negated N times for preset (N is an integer of 2 or more) (step S201). In other words, for each of the N sampling periods, the correction code determination circuit CDCT confirms whether the conversion end signal CED has been asserted.

[0131] Subsequently, the correction code determination circuit CDCT determines whether one or more negative levels are included in the N pieces of information of the conversion end signal CED (step S202). When no negative level is included (step S202: No), the correction code determination circuit CDCT maintains the current value as the value of the correction code CAL_CD[3:0] and terminates the processing. In this case, the correction code determination circuit CDCT is executed again as needed. Fig. 9B process.

[0132] On the contrary, when any negative level is included (step S202: Yes), the correction code determination circuit CDCT determines whether the correction code CAL_CD[3:0] has reached a maximum value such as "1111" (step S203). When the maximum value has been reached (step S203: Yes), the correction code determination circuit CDCT returns the value of the correction code CAL_CD[3:0] to a minimum value such as "0000", and proceeds to the processing in step S201 (step S204).

[0133] When the maximum value is not reached in step S203 (No), the correction code determination circuit CDCT increments the correction code CAL_CD[3:0] by (+1) (step S205). Then, the correction code determination circuit CDCT returns to step S201 to obtain the information of the conversion end signal N times again, and at the same time reflects the incremented correction code CAL_CD[3:0] on the common mode voltage regulator circuit CMCT.

[0134] Fig. 10A and Fig. 10B Each is shown in the use Fig.9A or Fig. 9B FIG. 1 is a diagram showing an exemplary determination result of a correction code in the case of a process of FIG. Figure 7 The situation is similar, Fig. 10A and Fig. 10B FIG. 2 shows an exemplary relationship between the value of the correction code CAL_CD[3:0] and the common mode voltage adjustment value as the correction voltage. Fig. 20A As shown in other figures, the common mode voltage and the final common mode voltage adjustment value have an appropriate range 11. Fig. 10A The initial value of the common mode voltage in the proper range 11 exists on the positive side, while in Fig. 10B The medium exists on the negative side.

[0135] When the common mode voltage exists within the appropriate range 11, the conversion end signal CED is always asserted in each sampling period. On the contrary, when the common mode voltage does not exist in the appropriate range 11, the conversion end signal CED may not be asserted for each sampling period. When the correction code CAL_CD[3:0] is continuously changed until the conversion end signal CED is always asserted, once the common mode voltage adjustment value exists in the appropriate range 11, the value of the correction code CAL_CD[3:0] is as follows: Fig. 10A or Fig. 10B As shown was judged.

[0136] As mentioned above, by using Fig.9A and Fig. 9B The common mode voltage can be adjusted to within the appropriate range 11 even in the foreground and background. Therefore, the comparison time of the comparator CMP[5] to CMP[0] can be reduced, and the speed of the voltage quantizer circuit QCT and the final analog-to-digital converter ADC can be increased. In particular, the common mode voltage is adjusted in the background, so that it can be adjusted in real time even if operating conditions such as voltage or temperature change during normal operation.

[0137] Since this is a system that monitors the conversion speed of the analog-to-digital converter ADC by using the conversion end signal CED and adjusts the common mode voltage based on the monitoring result, it is not necessary to additionally provide, for example, a common mode voltage detector circuit, and the like, and the overhead of the circuit area and the like can be suppressed. In addition, the common mode voltage can be adjusted in the analog-to-digital conversion unit ADCU, and therefore, the limitation of the common mode voltage in the external circuit configured to output the analog input voltages VAP and VAn can be alleviated. Therefore, the design of the semiconductor device DEV including the external circuit can be facilitated, and the versatility of the analog-to-digital converter ADC can be enhanced.

[0138] Notice, Fig.9A or Fig. 9B The process is not limited to the example shown and can be modified as needed. For example, Fig.9A The process can be modified so that, for example, the intermediate value is assumed to be the decision code, which is Fig. 10AThe upper and lower limits of the appropriate range 11 shown in FIG. 1 correspond to the respective values ​​of the correction code CAL_CD[3:0], and are acquired based on the conversion end signal CED. Alternatively, Fig.9A The process can be modified to, for example, a process using a binary search method.

[0139] <Details of comparator group>

[0140] Fig.11A It is shown Figure 6 A circuit diagram of an exemplary configuration of a comparator group. Fig.11A In, similar to Fig.19 , p-channel comparators and n-channel comparators are connected alternately. In this example, Figure 6 The comparators CMP[5], CMP[3] and CMP[1] shown are respectively Figure 5B The p-channel comparators CMPp[5], CMPp[3] and CMPp[1] are shown. Figure 6 The comparators CMP[4], CMP[2] and CMP[0] shown are respectively Figure 5A As shown, n-channel comparators CMPn[4], CMPn[2], and CMPn[0] are fabricated.

[0141] Fig. 11B It is used to explain Fig.11A Circuit diagrams of various modified examples of Fig. 11B As shown, the group of comparators can be configured so that the p-channel comparator CMPp and the n-channel comparator CMPn connected in parallel to the differential input nodes NinP and NinN perform a predetermined output via the logic gate LG. Alternatively, the p-channel comparator CMPp and the n-channel comparator CMPn are not always connected alternately, and only one type of comparator can be connected continuously. In fact, the number of p-channel comparators CMPp and the number of n-channel comparators CMPn configuring the comparator group are defined to be equal to some extent.

[0142] <Operation Timing of Correction Code Determination Circuit>

[0143] Fig. 12A and Fig. 12B Each of them shows the generation Figure 6 A method for sampling a clock signal in a method and an exemplary operation timing diagram of a correction code determination circuit in the method. Fig. 12A In the present invention, a sampling clock generator circuit CKSG is provided in the analog-to-digital converter ADC. The sampling clock generator circuit CKSG receives a main clock signal CKm from the outside as its input and output, and generates a sampling clock signal by, for example, Fig. 12B The sparse sampling clock generator circuit CKSG is shown to generate sampling clock signals CKs of 1 GHz, 2 GHz, etc.

[0144] At the rising edge of the sampling clock signal CKs, the flip-flop circuit FFed latches the clock signal CKfin output from the comparator CMP[0] and outputs the conversion end signal CED. On the contrary, at the rising edge of the sampling clock signal CKs, the clock signal CKfin of the assertion level is negated. The flip-flop circuit FFed can latch and hold the clock signal CKfin of the assertion level as the conversion end signal CED before negation.

[0145] The correction code determination circuit CDCT receives the conversion end signal CED held as described above as its input. Fig. 12A As shown in FIG. 1 , the main clock signal CKm is supplied to the correction code determination circuit CDCT. As a result, Fig. 12B As shown, the correction code determination circuit CDCT can capture the conversion end signal CED at the rising edge of the main clock signal CKm caused immediately after the sampling clock signal CKs, for example. Therefore, at an early stage, the correction code determination circuit CDCT can reflect the information of the conversion end signal CED to determine the value of the correction code CAL_CD[3:0].

[0146] <Main Effects of the First Embodiment>

[0147] As described above, by using the system according to the first embodiment, the correction code CAL_CD[3:0] can be determined using the conversion end signal CED, and the common mode voltage of the differential input voltage INp and INn can be adjusted based on the determined correction code in the foreground or background. Therefore, typically, the comparison time of each comparator can be reduced, and the speed of the analog-to-digital converter ADC can be increased. In particular, even changes in operating conditions such as voltage or temperature can be immediately processed by the adjustment of the background, and the high-speed operation of the analog-to-digital converter ADC can be maintained.

[0148] (Second embodiment)

[0149] <Schematic Configuration of Analog-to-Digital Conversion Unit>

[0150] Fig.13 FIG. 1 is a diagram showing a semiconductor device according to a second embodiment. Figure 1 A circuit block diagram of an exemplary schematic configuration of an analog-to-digital conversion unit. Fig.13 The analog-to-digital conversion unit ADCU and Figure 6 The exemplary configuration of is different in that capacitors Csp and Csn as sampling capacitors, and switches SW1 and SW2 are added in the voltage quantizer circuit QCTa.

[0151] One of the two electrodes of the capacitor Csp is connected to the sampling switch SSW, and the other of the two electrodes is connected to the positive differential input node NinP. Similarly, one of the two electrodes of the capacitor Csn is connected to the sampling switch SSW, and the other of the two electrodes is connected to the negative differential input node NinN. The differential input nodes NinP and NinN are connected, and when the switch SW1 is turned on, a predetermined power supply voltage VC is applied to the differential input nodes NinP and NinN. When the switch SW2 is turned on, the electrodes of the two capacitors Csp and Csn are short-circuited, and the electrodes are closer to the sampling switch SSW.

[0152] The sampling switch SSW and the switch SW1 are controlled to be turned on in the sampling period. Therefore, the analog input voltages VAP and VAn are sampled in the capacitors Csp and Csn, respectively. In the comparison period after this period, the sampling switch SSW and the switch SW1 are controlled to be turned off, and the switch SW2 is controlled to be turned on. Therefore, the charges of the capacitors Csp and Csn are redistributed in the capacitors of the digital-to-analog converter CDAC.

[0153] As described in the first embodiment, the predetermined voltage “Vref” of the digital-to-analog converter CDAC is determined by Figure 2B The capacitance value of the virtual capacitors CpD and CnD is adjusted. Specifically, the larger the capacitance value of the virtual capacitors CpD and CnD, the smaller the predetermined voltage "Vref". When the predetermined voltage "Vref" is small, the dynamic range of the analog-to-digital converter ADC becomes narrower, and the system may not be suitable for analog input voltages VApp and VAn with a large differential amplitude, for example.

[0154] Furthermore, in the system according to the second embodiment, if Fig. 8A As shown, capacitors Ccp[0] to Ccp[2] and Ccn[0] to Ccn[2] in the common mode voltage regulator circuit CMCT are connected to the differential input nodes NinP and NinN. The capacitors Ccp[0] to Ccp[2] and Ccn[0] to Ccn[2] can be equivalently regarded as another one of the virtual capacitors CpD and CnD. Therefore, the predetermined voltage "Vref" can be made smaller, and the dynamic range of the analog-to-digital converter ADC can be made narrower.

[0155] In such conditions, for example, Figure 2B The digital-to-analog converter CDAC performs sampling at the top plate of the capacitor, so Figure 6The voltage quantizer circuit QCT is also called a top plate type. In the top plate type, in the early stage of the comparison period, the differential input voltages INp and INn are equal to the analog input voltages VApp and VAn. Therefore, the capacitance values ​​of the capacitors Ccp[0] to Ccp[2] and Ccn[0] to Ccn[2] in the common mode voltage regulator circuit CMCT can be limited so as to maintain the dynamic range of the analog-to-digital converter ADC.

[0156] Instead, sampling is performed in the bottom plates of capacitors CsP and Csn, so, Fig.13 The voltage quantizer circuit QCTa is also called a backplane type. In the backplane type, the larger the capacitance values ​​of the virtual capacitors CpD and CnD and the capacitors Ccp[0] to Ccp[2] and Ccn[0] to Ccn[2] in the common mode voltage regulator circuit CMCT, the smaller the differential input voltages INp and INn in the early stage of the comparison period. Therefore, for example, even when the capacitance values ​​of the capacitors Ccp[0] to Ccp[2] and Ccn[0] to Ccn[2] are large, the dynamic range of the analog-to-digital converter ADC can be ensured.

[0157] <Main Effects of the Second Embodiment>

[0158] Even by using the system according to the second embodiment, effects similar to those of the first embodiment, which are typically high speed of the analog-to-digital converter ADC, can be achieved. Unlike the system according to the first embodiment, restrictions on the capacitance values ​​of the capacitors Ccp[0] to Ccp[2] and Ccn[0] to Ccn[2] in the common-mode voltage regulator circuit CMCT can be relaxed, and thus the design is facilitated. In addition, the dynamic range of the analog-to-digital converter ADC can be easily secured.

[0159] (Third Embodiment)

[0160] <Details of comparator group>

[0161] Fig.14 is a diagram showing a semiconductor device according to a third embodiment. Figure 6 or Fig.13 A circuit diagram of an exemplary configuration of a comparator group. Fig.11A Different, in Fig.14In the example, all comparators CMP[0] to CMP[5] are made of n-channel comparators CMPn[0] to CMPn[5]. In addition, in this example, the input transistors between the comparators CMPn[5] to CMPn[3] and the comparators CMPn[2] to CMPn[0] are different, and the comparators CMPn[5] to CMPn[3] determine the most significant bit of the digital signal and operate in the earlier period of continuous comparison, and the comparators CMPn[2] to CMPn[0] determine the least significant bit of the digital signal and operate in the later period of continuous comparison.

[0162] Specifically, the gate width W1 of the nMOS transistors MN0a and MN0b used as input transistors in the comparators CMPn[5] to CMPn[3] is designed to be smaller than the gate width W2 of the nMOS transistors MN0a and MN0b used as input transistors in the comparators CMPn[2] to CMPn[0]. Note that all the comparators CMP[0] to CMP[5] can be made of p-channel comparators CMPp[0] to CMPp[5] instead of n-channel comparators. In this case as well, the relationship between the gate widths is the same as in the n-channel comparator.

[0163] Fig.15 is a diagram showing a semiconductor device according to a third embodiment. Figure 6 or Fig.13 Schematic diagram of an exemplary transformation of the differential input voltage. Fig.15 As shown, whenever the comparison operation is completed, the voltage difference between the differential input voltages INp and INn |INp-INn| is updated by the digital-to-analog converter CDAC and gradually decreases. Therefore, increasing the speed of the comparison operation in the early stage and increasing the accuracy of the comparison operation in the later stage, more specifically reducing noise, is effective in terms of the balance between speed and accuracy.

[0164] Fig.16 It is shown by Fig.14 A timing diagram of an exemplary change in the common-mode voltage generated by the comparator group. Fig.16 As shown in FIG. 1 , when the n-channel comparator CMPn is used, the common mode voltage is gradually reduced each time a comparison operation is performed. Unlike the first embodiment, by actively utilizing the reduction in the common mode voltage, an increase in speed and an increase in accuracy can be achieved. That is, Fig.16 As shown, the appropriate range 15a of the common mode voltage for speed exists in a relatively high range, while the appropriate range 15b for accuracy exists in a relatively low range. Therefore, high speed can be achieved in the initial comparison operation, and then the common mode voltage is gradually reduced to suppress high speed but achieve high accuracy.

[0165] However, the common-mode voltage needs to be maintained within an appropriate range in order to balance speed and accuracy. Therefore, it is necessary to fully define the initial value of the common-mode voltage. Specifically, it is desirable to appropriately define the initial value of the common-mode voltage to have Fig.16 the property shown by the solid line in Fig.16 . That is, as can be seen from the property shown by the dotted line in

[0166] , if the initial value of the common-mode voltage is too high, the accuracy may be insufficient, and if the initial value of the common-mode voltage is too low, the speed may be insufficient. Fig.16 To fully define the initial value of the common-mode voltage, a correction code determination circuit CDCT and a common-mode voltage regulator circuit CMCT similar to those in the first embodiment can be provided. As can be seen from

[0167] In Fig.16 's example, in order to more effectively balance speed and accuracy, the gate widths W1 and W2 are made different to achieve the difference "W1 < W2". Specifically, when the gate width is small, high-speed operation is achieved while the noise is large, and ultimately, it is difficult to achieve high accuracy. On the contrary, when the gate width is large, high-speed operation becomes difficult while the noise is small, and ultimately high accuracy is achieved. When the gate width is small, the appropriate common-mode voltage is relatively high. When the gate width is large, the common-mode voltage is relatively low.

[0168] <Main effects of the third embodiment>

[0169] Even by using the system according to the third embodiment, effects similar to various effects of the first embodiment can be achieved. Various effects of the first embodiment are typically the high speed of the analog-to-digital converter ADC. In addition, the system according to the third embodiment can suppress excessive speed and achieve high accuracy of the analog-to-digital converter ADC by the degree of suppression.

[0170] In the above, the invention made by the inventors of the present application has been specifically described based on the embodiments. However, needless to say, the present invention is not limited to the foregoing embodiments, and various modifications can be made within the scope of the present invention.

Claims

1. A semiconductor device comprising: a voltage quantizer circuit that converts a differential input voltage to be applied to a differential input node into a digital signal having a plurality of bits for each sampling period and asserts a conversion end signal when the conversion operation is completed; a correction code determination circuit electrically connected to the voltage quantizer circuit and receiving the conversion end signal output from the voltage quantizer circuit as an input of the correction code determination circuit; as well as a common mode voltage regulator circuit electrically connected to the correction code determination circuit and the voltage quantizer circuit, Wherein the voltage quantizer circuit comprises: a first comparator including a first input transistor receiving the differential input voltage as an input to the first comparator and defining a value of a first bit of the digital signal; as well as a second comparator including a second input transistor receiving the differential input voltage as an input to the second comparator, the second input transistor being different from the first input transistor and the second comparator defining a value of a second bit of the digital signal, The correction code determination circuit determines a correction code for correcting the common mode voltage of the differential input voltage based on the conversion end signal output from the voltage quantizer circuit, and The common mode voltage regulator circuit regulates the common mode voltage by adding or subtracting a correction voltage based on the correction code to or from the differential input voltage.

2. The semiconductor device according to claim 1, The voltage quantizer circuit further comprises: A sampling switch for sampling an external analog input voltage of the differential input node; as well as a digital-to-analog converter that updates the differential input voltage by adding or subtracting a predetermined voltage to or from the differential input voltage according to the value of the first bit, and The second comparator receives the differential input voltage updated by the digital-to-analog converter as an input of the second comparator.

3. The semiconductor device according to claim 1, wherein the correction code determination circuit changes the correction code when the sampling period in which the conversion end signal is not asserted is detected.

4. The semiconductor device according to claim 3, wherein the correction code decision circuit changes the correction code until the sampling period in which the conversion end signal is not asserted is not detected.

5. The semiconductor device according to claim 3, In the period when the voltage quantizer circuit performs normal operation, the correction code determination circuit and the common mode voltage regulator circuit operate in the background.

6. The semiconductor device according to claim 5, The correction code determination circuit and the common mode voltage regulator circuit operate by causing the voltage quantizer circuit to sample an initial value of an external analog input voltage during a correction period included in a period during which the voltage quantizer circuit does not perform normal operation.

7. The semiconductor device according to claim 2, The common mode voltage regulator circuit includes a plurality of correction capacitors electrically connected to the differential input node, and adjusts the common mode voltage by redistributing the charge of the differential input node using correction capacitors defined between the plurality of correction capacitors based on the correction code.

8. The semiconductor device according to claim 1, One of the first input transistor and the second input transistor is a p-channel transistor, and the other of the first input transistor and the second input transistor is an n-channel transistor.

9. The semiconductor device according to claim 2, wherein the first input transistor and the second input transistor are both p-channel transistors or n-channel transistors, and A gate width of the first input transistor is smaller than a gate width of the second input transistor.

10. The semiconductor device according to claim 7, comprising: wherein the digital-to-analog converter includes a plurality of conversion capacitors electrically connected to the differential input node, and the differential input voltage is updated by redistributing the charge of the differential input node using a conversion capacitor corresponding to the first bit between the plurality of conversion capacitors, The semiconductor device further comprises: two sampling capacitors, each sampling capacitor having a first electrode electrically connected to the differential input node and a second electrode electrically connected to the sampling switch; a first switch that, when turned on, applies a predetermined power supply voltage to the differential input node; and The second switch, when turned on, short-circuits the second electrodes of the two sampling capacitors.

11. A semiconductor device comprising: Baseband processing circuitry that performs processing in the baseband of wireless communications; a high frequency circuit that performs processing in a high frequency band of the wireless communication and includes a high frequency transmission circuit that processes a transmission signal and a high frequency reception circuit that processes a reception signal using an analog-to-digital conversion unit; as well as A processor connected to a baseband processing circuit via a bus, Wherein the analog-to-digital conversion unit comprises: a voltage quantizer circuit that converts a differential input voltage to be applied to a differential input node into a digital signal having a plurality of bits for each sampling period and asserts a conversion end signal when the conversion operation is completed; a correction code determination circuit electrically connected to the voltage quantizer circuit and receiving the conversion end signal output from the voltage quantizer circuit as an input of the correction code determination circuit; and a common mode voltage regulator circuit electrically connected to the correction code determination circuit and the voltage quantizer circuit, The voltage quantizer circuit comprises: a first comparator including a first input transistor receiving the differential input voltage as an input to the first comparator and defining a value of a first bit of the digital signal; and a second comparator including a second input transistor receiving the differential input voltage as an input to the second comparator, the second input transistor being different from the first input transistor and the second comparator defining a value of a second bit of the digital signal, The correction code determination circuit determines a correction code for correcting a common mode voltage of the differential input voltage based on the conversion end signal output from the voltage quantizer circuit, and The common mode voltage regulator circuit regulates the common mode voltage by adding or subtracting a correction voltage based on the correction code to or from the differential input voltage.

12. The semiconductor device according to claim 11, The voltage quantizer circuit further comprises: A sampling switch for sampling an external analog input voltage of the differential input node; as well as a digital-to-analog converter that updates the differential input voltage by adding or subtracting the predetermined voltage to or from the differential input voltage according to the value of the first bit, and The second comparator receives the differential input voltage updated by the digital-to-analog converter as an input of the second comparator.

13. The semiconductor device according to claim 11, wherein the correction code determination circuit changes the correction code when the sampling period in which the conversion end signal is not asserted is detected.

14. The semiconductor device according to claim 13, wherein the correction code decision circuit changes the correction code until the sampling period in which the conversion end signal is not asserted is not detected.

15. The semiconductor device according to claim 13, In the period when the voltage quantizer circuit performs normal operation, the correction code determination circuit and the common mode voltage regulator circuit operate in the background.

16. The semiconductor device according to claim 12, The common mode voltage regulator circuit includes a plurality of correction capacitors electrically connected to the differential input node, and adjusts the common mode voltage by redistributing the charge of the differential input node using correction capacitors defined between the plurality of correction capacitors based on the correction code.

17. The semiconductor device according to claim 11, One of the first input transistor and the second input transistor is a p-channel transistor, and the other of the first input transistor and the second input transistor is an n-channel transistor.

18. The semiconductor device according to claim 12, wherein the first input transistor and the second input transistor are both p-channel transistors or n-channel transistors, and A gate width of the first input transistor is smaller than a gate width of the second input transistor.

19. The semiconductor device according to claim 11, The wireless communication is based on the ultra-wideband (UWB) standard.

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