Mutual calibration method applied to ADC differential capacitor array

Abstract

The invention belongs to the technical field of integrated circuit design, and discloses a mutual calibration method applied to an ADC differential capacitor array, and the method comprises the following steps: 1, extracting and quantifying the error voltage of each capacitor in a CDAC capacitor array; and step 2, adding a corresponding error code value to the output code value of the ADC. By adopting the calibration method provided by the invention, an additional calibration CDAC in a traditional simulation calibration method is removed, the capacitance area is remarkably reduced, an error code value and a code value normally quantized by the ADC are combined to obtain a final output code value, the operation process can be operated on an on-chip or on off-chip software, and the calculation efficiency is greatly improved. And the complexity of circuit design is reduced, and meanwhile, the ADC conversion precision loss caused by capacitor array mismatch can be remarkably reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to a mutual calibration method applied to an ADC differential capacitor array. Background Art

[0002] Generally, in the design of high-precision ADC (analog-to-digital converter) greater than 12 bits, the requirements for CDAC (capacitive digital-to-analog converter) composed of capacitor array are very high. However, the capacitors manufactured by current integrated circuit technology are difficult to meet their stringent mismatch requirements. The traditional method of reducing the relative mismatch of capacitors by increasing the capacitor area is very inefficient and cannot be applied to the design of high-precision ADC. Therefore, in order to solve the mismatch problem of capacitors in high-precision ADC, many ADC calibration methods have been proposed by predecessors. The current ADC calibration methods mainly include calibration algorithms in the analog domain and calibration algorithms in the digital domain. The calibration algorithm in the analog domain is mainly a self-calibration algorithm, which is achieved by adding a calibration CDAC capacitor array to the main CDAC capacitor array. Its working principle is to quantize the error voltage caused by the mismatch of each capacitor in the main CDAC into a digital code value through the calibration CDAC through a specific capacitor flipping sequence, and store the mismatch code value of each capacitor in the RAM. During the normal conversion process of the ADC, the mismatch code value of each capacitor is read from the RAM and the error voltage is compensated to the entire array of the main CDAC capacitors through the calibration CDAC capacitor array to complete the calibration. The calibration algorithm in the digital domain mainly adjusts the weight of each capacitor in the main CDAC to complete the calibration process. There are mainly "disturbance" algorithm and "split" ADC algorithm. The "disturbance" algorithm adds "positive" and "negative" disturbance signals to the input signal of the ADC to obtain the output code value of the ADC and then adjusts the weight of the ADC code value in the digital domain through the LMS (least mean square algorithm) algorithm to complete the calibration process. The "split" ADC quantizes the input signal through two ADCs respectively, and adjusts the weight of the ADC code value in the digital domain through the LMS algorithm to complete the calibration process.

[0003] Although the above calibration methods can improve the accuracy of ADC, their disadvantages are also very obvious. For example, the analog self-calibration technology requires additional calibration of the CDAC capacitor array. The capacitor occupies a very large layout area in the integrated circuit manufacturing process. At the same time, during the normal conversion process of the ADC, the error code value of the entire capacitor array needs to be frequently read from the RAM. This process also requires a large amount of adder resources and the algorithm can only run on the chip and cannot be moved off the chip, which increases the cost of chip manufacturing and use. The calibration algorithm in the digital domain mainly uses the LMS algorithm. The calibration algorithm in the digital domain usually increases the hardware overhead. For example, the "splitting" algorithm requires two ADCs to quantize the input signal. At the same time, improper design of the LMS algorithm parameters will cause the algorithm to not converge and cause calibration failure, which requires careful adjustment. In addition, the LMS algorithm requires a long correction time to complete the calibration. These all limit the application field of the algorithm. Summary of the invention

[0004] The present invention aims to provide a mutual calibration method applied to an ADC differential capacitor array to solve the above technical problems.

[0005] In order to solve the above technical problems, a specific technical solution of a mutual calibration method applied to an ADC differential capacitor array of the present invention is as follows: A mutual calibration method for an ADC differential capacitor array, the ADC differential capacitor array comprising two capacitors Cu, one capacitor Cu having capacitors C1, P~C13, P connected in parallel at both ends, the other capacitor Cu having capacitors C1, N~C13, N connected in parallel at both ends, the two capacitors Cu being connected to capacitor Cal via switches S5 and S6, one end of capacitor C8, P~C13, P connected to a positive end of a comparator via switch S1, and the other ... The capacitor C8, N-C13, N is connected to Cu, and the other end can be connected to Vip, Vrefp, Vrefn, and Vcm through a switch; one end of the capacitor C8, N-C13, N is connected to the negative end of the comparator through a switch S2, and the other end can be connected to Vin, Vrefp, Vrefn, and Vcm through a switch; one end of the capacitor C1, N-C7, N is connected to Cu, and the other end can be connected to Vin, Vrefp, Vrefn, and Vcm through a switch; the positive and negative ends of the comparator are connected to Vcm through switches S3 and S4 respectively; the method comprises the following steps: Step 1: Extract and quantize the error voltage of each capacitor in the CDAC capacitor array; after power-on, perform the CDAC calibration process first, and then perform the normal quantization process of the ADC; Step 2: Add the corresponding error code value to the output code value of the ADC.

[0006] Furthermore, the step 1 comprises the following steps: Step 1.1: First, calibrate the highest capacitor C13,P in the comparator positive capacitor array: close switches S1, S3, S4, S5, and S6, and open S2. At this time, the negative end of the comparator is connected to Vcm and the positive end of the comparator is connected to the capacitor array. At the same time, the lower plates of the comparator negative capacitor array C1,N~C13,N are all connected to Vcm, the lower plate of the highest capacitor C13,P in the comparator positive capacitor array is connected to Vrefn, and the lower plates of the other capacitors C1,P~C12,P are connected to Vrefp; Step 1.2: Switch S3 is disconnected, and the states of switches S1, S2, S4, S5, S6 remain unchanged. At the same time, the lower plate of the highest capacitor C13,P in the positive terminal capacitor array of the comparator is connected to Vrefp, and the lower plates of the other capacitors C1,P~C12,P are connected to Vrefn; this process completes the error voltage extraction of the highest capacitor C13,P at the positive terminal of the comparator; Step 1.3: The error voltage is quantized by switching the lower plate switch of the comparator negative terminal capacitor C1,N~C13,N, and the quantized code value is stored in the RAM. After the error voltage of the highest bit capacitor C13,P of the comparator positive terminal is quantized, the lower plate of the capacitor C13,P is connected to Vrefn and remains unchanged in the subsequent process.

[0007] Furthermore, the step 1 includes step 1.4: completing the error voltage quantization of other bit capacitors C1,P~C12,P in the same manner as steps 1.1-1.3 and storing the quantized error voltages in RAM.

[0008] Furthermore, the step 1 includes step 1.5: after the positive terminal capacitance of the comparator is quantized, the negative terminal capacitance is quantized in the same manner as steps 1.1-1.4.

[0009] Furthermore, step 2 includes: after the calibration process is completed, the normal conversion process of the ADC is started to obtain the output code. If the code value of the capacitor at this bit is 1, the error code value of this bit is added; if it is 0, the error code value of this bit is not added, and the ADC output code value with the error code value added is used as the final conversion output code value.

[0010] The mutual calibration method for ADC differential capacitor array of the present invention has the following advantages: the calibration method proposed by the present invention removes the additional calibration CDAC in the traditional analog calibration method, significantly reduces the capacitor area, and combines the error code value with the code value of the normal quantization of the ADC to obtain the final output code value. The operation process can not only be run on the chip but also be operated on the software outside the chip. Therefore, the proposed calibration method reduces the complexity of circuit design and can also significantly reduce the ADC conversion accuracy loss caused by capacitor array mismatch. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of a 14-bit ADC differential capacitor array structure; Figure 2 A flow chart of the calibration method proposed by the present invention; Figure 3 This is a comparison chart of the results before and after calibration of a 14-bit ADC with a relative capacitor mismatch error of 1%. DETAILED DESCRIPTION

[0012] In order to better understand the purpose, structure and function of the present invention, a mutual calibration method for an ADC differential capacitor array of the present invention is further described in detail below with reference to the accompanying drawings.

[0013] This embodiment takes the calibration process of a 14-bit ADC differential capacitor array as an example for explanation. Figure 1 As shown, a 14-bit ADC differential capacitor array includes two capacitors Cu, one capacitor Cu has capacitors C1,P~C13,P connected in parallel at both ends, and the other capacitor Cu has capacitors C1,N~C13,N connected in parallel at both ends. Capacitor Cal is connected between the two capacitors Cu through switches S5 and S6. One end of capacitor C8, P~C13, P is connected to the positive end of the comparator through switch S1, and the other end can be connected to Vip, Vrefp, Vrefn, and Vcm through switches. One end of capacitor C1, P~C7, P is connected to Cu, and the other end can be connected to Vip, Vrefp, Vrefn, and Vcm through switches. One end of capacitor C8, N-C13, N is connected to the negative end of the comparator through switch S2, and the other end can be connected to Vin, Vrefp, Vrefn, and Vcm through switches. One end of capacitor C1, N-C7, N is connected to Cu, and the other end can be connected to Vin, Vrefp, Vrefn, and Vcm through switches. The positive and negative ends of the comparator are connected to Vcm through switches S3 and S4, respectively.

[0014] like Figure 2 As shown, a mutual calibration method for an ADC differential capacitor array of the present invention comprises the following steps: Step 1: Extract and quantify the error voltage of each capacitor in the CDAC capacitor array; After power-on, the CDAC calibration process is performed first, and then the normal quantization process of the ADC is performed.

[0015] Step 1.1: First calibrate the highest capacitor (C13, P) of the comparator positive capacitor array: close switches S1, S3, S4, S5, and S6, and open S2. At this time, the negative end of the comparator is connected to Vcm and the positive end of the comparator is connected to the capacitor array. At the same time, the lower plates of the negative end capacitor array (C1, N ~ C13, N) of the comparator are all connected to Vcm, and the lower plate of the highest capacitor (C13, P) in the positive end capacitor array of the comparator is connected to Vrefn. The lower plates of the other capacitors (C1, P ~ C12, P) are connected to Vrefp; Step 1.2: Switch S3 is disconnected, and the states of switches S1, S2, S4, S5, and S6 remain unchanged. At the same time, the lower plate of the highest capacitor (C13, P) in the positive terminal capacitor array of the comparator is connected to Vrefp, and the lower plates of the other capacitors (C1, P~C12, P) are connected to Vrefn; this process completes the error voltage extraction of the highest capacitor (C13, P) at the positive terminal of the comparator.

[0016] Step 1.3: The error voltage is quantized by switching the lower plate switch of the negative terminal capacitor (C1,N~C13,N) of the comparator, and the quantized code value is stored in RAM. After the error voltage of the highest bit capacitor (C13,P) of the positive terminal of the comparator is quantized, the lower plate of C13,P is connected to Vrefn and remains unchanged in the subsequent process. Step 1.4: Complete the error voltage quantization of other bits (C1,P~C12,P) in the same way as steps 1.1-1.3 and store them in RAM.

[0017] Step 1.5: After the positive terminal capacitance of the comparator is quantized, the negative terminal capacitance is quantized in the same manner as steps 1.1-1.4.

[0018] Step 2: Add the corresponding error code value to the output code value of the ADC.

[0019] After the calibration process is completed, the normal conversion process of the ADC is started to obtain the output code. If the code value of the capacitor at that bit is 1, the error code value of that bit is added. If it is 0, the error code value of the capacitor at that bit is not added. The ADC output code value with the added error code value is used as the final conversion output code value.

[0020] The above process completes the ADC calibration process and conversion process. The principle of extracting the capacitor error voltage can refer to the existing technical method.

[0021] like Figure 3As shown, the calibration method proposed in the present invention removes the additional calibration CDAC in the traditional analog calibration method, significantly reduces the capacitor area, and combines the error code value with the code value of the normal quantization of the ADC to obtain the final output code value. The operation process can not only be run on the chip but also be operated on software outside the chip. Therefore, the proposed calibration method reduces the complexity of circuit design and can also significantly reduce the ADC conversion accuracy loss caused by capacitor array mismatch.

[0022] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A mutual calibration method for an ADC differential capacitor array, the ADC differential capacitor array comprising two capacitors Cu, one capacitor Cu having capacitors C1, P~C13, P in parallel at both ends, and another capacitor Cu having capacitors C1, N~C13, N in parallel at both ends, the two capacitors Cu being connected to capacitor Cal via switches S5 and S6, one end of capacitor C8, P~C13, P being connected to the positive end of a comparator via switch S1, and the other end being connected to Vip, Vrefp, Vrefn, and Vcm via switches, respectively, and capacitors C1, P~C7, P One end is connected to Cu, and the other end can be connected to Vip, Vrefp, Vrefn, and Vcm through a switch; one end of capacitor C8, N-C13, N is connected to the negative end of the comparator through a switch S2, and the other end can be connected to Vin, Vrefp, Vrefn, and Vcm through a switch; one end of capacitor C1, N-C7, N is connected to Cu, and the other end can be connected to Vin, Vrefp, Vrefn, and Vcm through a switch; the positive and negative ends of the comparator are connected to Vcm through switches S3 and S4 respectively; it is characterized in that The method comprises the following steps: Step 1: Extract and quantize the error voltage of each capacitor in the CDAC capacitor array; after power-on, perform the CDAC calibration process first, and then perform the normal quantization process of the ADC; Step 2: Add the corresponding error code value to the output code value of the ADC.

2. The mutual calibration method for ADC differential capacitor array according to claim 1, characterized in that: The step 1 comprises the following steps: Step 1.1: First, calibrate the highest capacitor C13,P in the comparator positive capacitor array: close switches S1, S3, S4, S5, and S6, and open S2. At this time, the negative end of the comparator is connected to Vcm and the positive end of the comparator is connected to the capacitor array. At the same time, the lower plates of the comparator negative capacitor array C1,N~C13,N are all connected to Vcm, the lower plate of the highest capacitor C13,P in the comparator positive capacitor array is connected to Vrefn, and the lower plates of the other capacitors C1,P~C12,P are connected to Vrefp; Step 1.2: Switch S3 is disconnected, and the states of switches S1, S2, S4, S5, S6 remain unchanged. At the same time, the lower plate of the highest capacitor C13,P in the positive terminal capacitor array of the comparator is connected to Vrefp, and the lower plates of the other capacitors C1,P~C12,P are connected to Vrefn; this process completes the error voltage extraction of the highest capacitor C13,P at the positive terminal of the comparator; Step 1.3: The error voltage is quantized by switching the lower plate switch of the comparator negative terminal capacitor C1,N~C13,N, and the quantized code value is stored in the RAM. After the error voltage of the highest bit capacitor C13,P of the comparator positive terminal is quantized, the lower plate of the capacitor C13,P is connected to Vrefn and remains unchanged in the subsequent process.

3. The mutual calibration method for ADC differential capacitor array according to claim 2, characterized in that: The step 1 includes step 1.4: completing the error voltage quantization of other bit capacitors C1,P~C12,P in the same manner as steps 1.1-1.3 and storing them in RAM.

4. The mutual calibration method for ADC differential capacitor array according to claim 3, characterized in that: The step 1 includes step 1.5: after the positive terminal capacitance of the comparator is quantized, the negative terminal capacitance is quantized in the same manner as steps 1.1-1.

4.

5. The mutual calibration method for ADC differential capacitor array according to claim 4, characterized in that: The step 2 comprises: after the calibration process is completed, the normal conversion process of the ADC is started to obtain the output code, if the code value of the capacitor at that position is 1, the error code value of that position is added, if it is 0, the error code value of that capacitor at that position is not added, and the ADC output code value with the error code value added is used as the final conversion output code value.

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