Deviation calibration circuit and method, chip and electronic equipment

Abstract

The invention relates to a deviation calibration circuit and method, a chip and an electronic device, the deviation calibration circuit comprises a first switch and a second switch, the first end of the first switch is used for receiving a reference level, the first end of the second switch is connected with the first input end of a comparator and is used for receiving a direct current common mode level, and the second end of the comparator is connected with the second input end of the comparator. The second end of the first switch, the second end of the second switch and the second input end of the comparator are connected with one another. According to the deviation calibration circuit, the switch connection mode of the input end of the comparator is changed, and the number of switches on an input signal line is reduced, so that a data signal (such as a direct-current common-mode level) can be directly connected to the input end of the comparator, parasitic resistance and capacitance of an input path of the comparator can be reduced, and the reliability of the comparator is improved. Attenuation of data signals is reduced, and the bit error rate of a system (such as various systems including comparators) is reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic circuits, and in particular to a deviation calibration circuit and method, a chip, and an electronic device. Background Art

[0002] In a high-speed single-ended receiver (Receiver, RX), the single-ended high-speed data signal and the reference voltage enter the comparator, and then output the complete data information. Among them, the transmission rate, bit error rate, signal bandwidth and signal deviation are all closely related circuit design parameters. With the popularity of double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM) communication interface (IO) system and flash memory (NAND) communication interface (IO) system, the data transmission rate is getting faster and faster. In order to increase the circuit bandwidth, the receiver will add various equalization technologies to increase the complexity of circuit design, which will inevitably increase the deviation of the circuit, and the bit error rate of the circuit will also be reduced. Summary of the invention

[0003] The present disclosure proposes a deviation calibration technical solution.

[0004] According to one aspect of the present disclosure, a deviation calibration circuit is provided, which is used to calibrate a comparator. The deviation calibration circuit includes a first switch and a second switch. The first end of the first switch is used to receive a reference level, the first end of the second switch is connected to the first input end of the comparator to receive a DC common mode level, and the second end of the first switch, the second end of the second switch, and the second input end of the comparator are connected to each other.

[0005] In a possible implementation, the DC common-mode level comes from a transmitting circuit, and the transmitting circuit configures the DC common-mode level to a calibration level that is the same as the reference level; the first switch is disconnected and the second switch is turned on so that the first input terminal and the second input terminal of the comparator receive the calibration level; the comparator is calibrated according to the calibration level until the comparator outputs a jump signal, and the jump signal is used to indicate that the deviation calibration of the comparator is completed.

[0006] In one possible implementation, the comparator is calibrated according to the calibration level until the comparator outputs a jump signal, including: when the comparator outputs a steady-state signal, the comparator is calibrated according to the calibration level until the comparator outputs a jump signal, wherein the steady-state signal is a signal whose amplitude remains unchanged within a preset time, and the jump signal is a signal whose amplitude changes between a high level and a low level within the preset time.

[0007] In a possible implementation, the transmitting circuit configures the DC common mode level to a level to be measured that is the same as or different from the reference level; turns on the first switch and turns off the second switch, so that the first input terminal of the comparator receives the level to be measured and the second input terminal of the comparator receives the reference level; the comparator compares the level to be measured with the reference level to obtain a comparison result.

[0008] In a possible implementation, the control end of the first switch and the control end of the second switch are used to receive an enable signal, and in response to the enable signal being at a first level, the first switch is turned off and the second switch is turned on; in response to the enable signal being at a second level, the first switch is turned on and the second switch is turned off.

[0009] In a possible implementation, the transmitting circuit includes N first circuits, each of which includes a fifth transistor, a sixth transistor, a first resistor, a second resistor, and a third resistor. The first end of the fifth transistor is connected to a high level, the second end of the fifth transistor is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor and the first end of the third resistor, the second end of the second resistor is connected to the first end of the sixth transistor, the second end of the sixth transistor is grounded, the control end of the fifth transistor is used to receive a first control signal, the control end of the sixth transistor is used to receive a second control signal, the second ends of the N third resistors are connected to output the DC common mode level, and N is a positive integer.

[0010] In a possible implementation manner, the comparator includes a dynamic comparator and a linear comparator.

[0011] According to one aspect of the present disclosure, a deviation calibration method is provided, which is applied to the deviation calibration circuit, which is used to calibrate a comparator, and the deviation calibration circuit includes a first switch and a second switch, wherein the first end of the first switch is used to receive a reference level, the first end of the second switch is connected to the first input end of the comparator to receive a DC common mode level, the second end of the first switch, the second end of the second switch, and the second input end of the comparator are connected to each other, and the DC common mode level comes from a transmitting circuit; the method includes: the transmitting circuit configures the DC common mode level to a calibration level that is the same as the reference level; disconnects the first switch and turns on the second switch, and both the first input end and the second input end of the comparator are used to receive the calibration level; calibrates the comparator according to the calibration level until the comparator outputs a jump signal, and the jump signal is used to indicate that the deviation calibration of the comparator is completed.

[0012] In one possible implementation, the comparator is calibrated according to the calibration level until the comparator outputs a jump signal, including: when the comparator outputs a steady-state signal, the comparator is calibrated according to the calibration level until the comparator outputs a jump signal, wherein the steady-state signal is a signal whose amplitude remains unchanged within a preset time, and the jump signal is a signal whose amplitude changes between a high level and a low level within the preset time.

[0013] In a possible implementation, the method further includes: the transmitting circuit configures the DC common mode level to a level to be measured that is the same as or different from the reference level; turning on the first switch and turning off the second switch so that the first input terminal of the comparator receives the level to be measured and the second input terminal of the comparator receives the reference level; the comparator compares the level to be measured with the reference level to obtain a comparison result.

[0014] In a possible implementation, the control end of the first switch and the control end of the second switch are used to receive an enable signal, and in response to the enable signal being at a first level, the first switch is turned off and the second switch is turned on; in response to the enable signal being at a second level, the first switch is turned on and the second switch is turned off.

[0015] In a possible implementation, the transmitting circuit includes N first circuits, each of which includes a fifth transistor, a sixth transistor, a first resistor, a second resistor, and a third resistor. The first end of the fifth transistor is connected to a high level, the second end of the fifth transistor is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor and the first end of the third resistor, the second end of the second resistor is connected to the first end of the sixth transistor, the second end of the sixth transistor is grounded, the control end of the fifth transistor is used to receive a first control signal, the control end of the sixth transistor is used to receive a second control signal, the second ends of the N third resistors are connected to output the DC common mode level, and N is a positive integer.

[0016] In a possible implementation manner, the comparator includes a dynamic comparator and a linear comparator.

[0017] According to one aspect of the present disclosure, a chip is provided, wherein the chip includes the deviation calibration circuit as described above.

[0018] According to one aspect of the present disclosure, an electronic device is provided, comprising the deviation calibration circuit as described above.

[0019] The deviation calibration circuit of the disclosed embodiment is used to calibrate a comparator, and the deviation calibration circuit includes a first switch and a second switch, wherein the first end of the first switch is used to receive a reference level, the first end of the second switch is connected to the first input end of the comparator to receive a DC common mode level, and the second end of the first switch, the second end of the second switch, and the second input end of the comparator are connected to each other. The deviation calibration circuit of the disclosed embodiment changes the switch connection mode of the comparator input end and reduces the number of switches on the input signal line, so that the data signal (such as the DC common mode level) can be directly connected to the input end of the comparator, which is conducive to reducing the parasitic resistance and capacitance of the comparator input path, reducing the attenuation of the data signal, and reducing the bit error rate of the system (such as various systems including comparators).

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0022] Figure 1 A schematic diagram of a deviation calibration circuit in the related art is shown.

[0023] Figure 2 A schematic diagram of an offset calibration circuit according to an embodiment of the present disclosure is shown.

[0024] Figure 3 A schematic diagram of a transmitting circuit according to an embodiment of the present disclosure is shown.

[0025] Figure 4 A circuit diagram showing a comparator performing offset calibration according to an embodiment of the present disclosure is shown.

[0026] Figure 5 A flow chart of a deviation calibration method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0027] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0028] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0029] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0030] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0031] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0032] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0033] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0034] It should be noted that the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present disclosure are mainly switch transistors. Since the source and drain of the switch transistor used here are symmetrical, the source and drain are interchangeable, and the source is referred to as the first end and the drain is referred to as the second end, or the drain is referred to as the first end and the source is referred to as the second end. For example, the middle end of the transistor may be defined as the gate, the signal input end as the source, and the signal output end as the drain according to the form in the accompanying drawings. In addition, the switch transistors used in the embodiments of the present disclosure may include any one of a P-type transistor and an N-type transistor or a combination thereof. Among them, the P-type transistor is turned on when the gate is a low voltage and is turned off when the gate is a high voltage, and the N-type transistor is turned on when the gate is a high voltage and is turned off when the gate is a low voltage. In addition, multiple signals in each embodiment may correspond to a first potential and a second potential, and the first potential and the second potential only represent that the potential of the signal has two different state quantities, and do not represent that the first potential or the second potential has a specific value.

[0035] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0036] For high-speed comparator circuits, in order to optimize the comparator performance, the receiver will add equalization technology, including but not limited to continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE). The addition of various equalization technologies optimizes the circuit bandwidth and reduces the circuit bit error rate. However, due to the addition of various functional circuits, the circuit deviation will also increase. Therefore, before the high-speed receiver works normally, the receiver's comparator can be calibrated for deviation, thereby improving system performance.

[0037] The deviation calibration scheme in the related technology is usually suitable for low-speed comparators. A matching control switch can be added to the differential signal line of the comparator. The differential signal can be connected to the same reference voltage at the same time through the control switch. Since multiple switches (for example, at least four switches) are connected in series on the signal line and each switch has parasitic capacitance and resistance, it may cause attenuation of high-frequency signals and increase the bit error rate of the system.

[0038] Figure 1 A schematic diagram of a deviation calibration circuit in the related art is shown, Figure 1 As shown, the receiver may include a deviation calibration circuit MUX and a comparator, and the deviation calibration circuit MUX includes a switch SW3, a switch SW4, a switch SW5, and a switch SW6, wherein a first end of the switch SW3 is used to receive an input signal INP1, a second end of the switch SW3 is connected to a first input end (positive input end) of the comparator, a first end of the switch SW4 is used to receive a reference level VREF, a second end of the switch SW4 is connected to a second input end (reverse input end) of the comparator, a first end of the switch SW5 is used to receive a reference level VREF, a second end of the switch SW5 is connected to the first input end (positive input end) of the comparator, a first end of the switch SW6 is used to receive a reference level VREF, and a second end of the switch SW6 is connected to a second input end (reverse input end) of the comparator.

[0039] The input end of the comparator can be controlled by four switches (i.e., switch SW3, switch SW4, switch SW5, and switch SW6). When the comparator is working normally, switch SW3 and switch SW4 are turned on, and switch SW5 and switch SW6 remain in an off state. During deviation calibration, switch SW3 and switch SW4 are turned off, and switch SW5 and switch SW6 are turned on. Therefore, the signals at the differential input end of the comparator are equal, and then the deviation calibration of the comparator is performed.

[0040] The switch enable signal can be used to indicate the on / off state of switch SW3, switch SW4, switch SW5, and switch SW6. If the enable signal is at the first level EN, switch SW3 and switch SW4 are disconnected, and switch SW5 and switch SW6 are turned on; if the enable signal is at the second level ENB, switch SW3 and switch SW4 are turned on, and switch SW5 and switch SW6 are disconnected. It should be understood that the first level EN and the second level ENB only represent that the potential of the signal has two different state quantities, and do not represent that it has a specific value.

[0041] Depend on Figure 1 It can be seen that the calibration method in the related art limits the data transmission rate. In order to calibrate the deviation of the signal, multiple control switches (such as Figure 1 The on-resistance and parasitic capacitance of the switches will reduce the bandwidth of the signal path, and the quality of the high-speed signal passing through the switches will be reduced. Therefore, the bandwidth of the receiver will also be reduced, and the bit error rate of the circuit will also increase.

[0042] Figure 2 A schematic diagram of a deviation calibration circuit according to an embodiment of the present disclosure is shown. Figure 2 As shown, the deviation calibration circuit 1 is used to calibrate the comparator 2. The deviation calibration circuit 1 includes a first switch SW1 and a second switch SW2. The first end of the first switch SW1 is used to receive a reference level VREF. The first end of the second switch SW2 is connected to the first input end (positive input end) of the comparator 2 to receive a DC common mode level INP. The second end of the first switch SW1, the second end of the second switch SW2, and the second input end (reverse input end) of the comparator 2 are connected to each other.

[0043] and Figure 1 Compared with the deviation calibration technology shown in the figure, in the related art, when the high-speed input signal INP1 enters the receiver, a switch (e.g. Figure 1The switch SW3, switch SW4, switch SW5, switch SW6) in the middle will introduce parasitic resistance and capacitance to the input signal line, thereby reducing the bandwidth of the input signal and increasing the bit error rate of the receiver. On the contrary, the deviation calibration circuit of the embodiment of the present disclosure changes Figure 1 The switch connection method of the input end of the comparator 2 reduces the number of switches on the input signal line, so that the data signal (such as the DC common mode level INP) can be directly connected to the input end of the comparator 2, which is beneficial to reduce the parasitic resistance and capacitance of the input path of the comparator 2, reduce the attenuation of the data signal, and reduce the bit error rate of the system (such as various systems including comparators).

[0044] It should be understood that for a high-speed signal receiver including the comparator 2 , the parasitic resistance and capacitance of the high-speed signal line should be reduced as much as possible, and the deviation calibration circuit of the embodiment of the present disclosure can reduce the series resistance on the high-speed signal.

[0045] In a possible implementation, the comparator 2 is used to compare two voltages or signals and output a corresponding logic level. For example, the comparator 2 is a circuit that compares an analog voltage signal (e.g., a DC common-mode level INP) with a reference voltage (e.g., a reference level VREF). The two inputs of the comparator 2 are analog signals, and the output terminal OUT outputs a binary signal 0 or 1. When the difference in input voltage (e.g., the difference between the DC common-mode level INP and the reference level VREF) increases or decreases and the positive and negative signs remain unchanged, its output remains unchanged.

[0046] In one possible implementation, the deviation calibration circuit of the embodiment of the present disclosure is suitable for high-frequency systems such as double data rate synchronous dynamic random access memory (DDRSDRAM) communication interface (IO) system and flash memory (NAND) communication interface (IO) system, and can perform deviation calibration on the comparator in the system without reducing the bandwidth design requirements.

[0047] In a possible implementation, the comparator 2 includes a dynamic comparator and a linear comparator. The embodiments of the present disclosure do not limit the type of the comparator, and the deviation calibration circuit provided by the embodiments of the present disclosure can be applied to various comparators.

[0048] For the comparator 2 circuit, when performing deviation calibration on it, the differential input signal needs to maintain the same input level signal. For example, the first input terminal and the second input terminal of the comparator 2 input the same level signal. By observing the state of the differential output terminal OUT, it is determined whether the comparator 2 circuit deviation is biased towards the positive end or the negative end.

[0049] When comparator 2 is a linear comparator, if the differential input has the same common-mode level signal (for example, the DC common-mode level INP is the same as the reference level VREF), and the linear comparator output remains 1 or 0, it indicates that the deviation of the linear comparator circuit is biased toward the positive end or the negative end. The calibration module of the linear comparator can be adjusted to make the linear comparator output jump from 0 to 1 or from 1 to 0. At this time, the linear comparator circuit deviation calibration is completed.

[0050] When comparator 2 is a dynamic comparator, by inputting the sampling clock, if the dynamic comparator output remains in the state of 0 or 1, deviation calibration is required to adjust the calibration module of the dynamic comparator. When a jump occurs at the output end of the dynamic comparator, from 0 to 1 or from 1 to 0, the deviation calibration of the dynamic comparator circuit is completed.

[0051] In a possible implementation, the control end of the first switch SW1 and the control end of the second switch SW2 are used to receive an enable signal. In response to the enable signal being at a first level EN, the first switch SW1 is turned off and the second switch SW2 is turned on; in response to the enable signal being at a second level ENB, the first switch SW1 is turned on and the second switch SW2 is turned off.

[0052] Exemplarily, the first switch SW1 (or the second switch SW2) may be composed of at least one switch transistor. When the number of switch transistors constituting the first switch SW1 (or the second switch SW2) exceeds one, the switch transistors may be connected in series or in parallel, and the embodiments of the present disclosure do not impose specific restrictions on this. It should be understood that in order to reduce the parasitic resistance and parasitic capacitance of the input path of the comparator 2, preferably, a single switch transistor is used as the first switch SW1 (or the second switch SW2).

[0053] Among them, the control end of the switch transistor is the gate, the first end can be the source, and the second end can be the drain; or, the first end can be the drain, and the second end can be the source, which is not specifically distinguished here. Further, in a specific implementation, the N-type switch tube is turned on by a high-level signal and turned off by a low-level signal. The P-type switch tube is turned off by a high-level signal and turned on by a low-level signal.

[0054] For example, an N-type switch tube may be used as the first switch SW1 , a P-type switch tube may be used as the second switch SW2 , the first level EN may be set to a low level, and the second level ENB may be set to a high level.

[0055] The gate of the first switch SW1 (eg, an N-type switch tube) is controlled by a low level, and the first switch SW1 is in an off state. The gate of the second switch SW2 (eg, a P-type switch tube) is controlled by a low level, and the second switch SW2 is in an on state.

[0056] The gate of the first switch SW1 (eg, an N-type switch tube) is controlled by a high level, and the first switch SW1 is in an on state. The gate of the second switch SW2 (eg, a P-type switch tube) is controlled by a high level, and the second switch SW2 is in an off state.

[0057] For another example, a P-type switch tube may be used as the first switch SW1 , an N-type switch tube may be used as the second switch SW2 , the first level EN may be set to a high level, and the second level ENB may be set to a low level.

[0058] The gate of the first switch SW1 (eg, a P-type switch tube) is controlled by a high level, and the first switch SW1 is in an off state. The gate of the second switch SW2 (eg, an N-type switch tube) is controlled by a high level, and the second switch SW2 is in an on state.

[0059] The gate of the first switch SW1 (eg, a P-type switch tube) is controlled by a low level, and the first switch SW1 is in an on state. The gate of the second switch SW2 (eg, an N-type switch tube) is controlled by a low level, and the second switch SW2 is in an off state.

[0060] It should be understood that the first level EN and the second level ENB only represent that the potential of the enable signal has two different state quantities, and do not represent that it has a specific value. The above is only an example to illustrate the specific structure of the first switch SW1 and the second switch SW2 provided in the embodiment of the present disclosure. In the specific implementation, it is not limited to the above structure provided in the embodiment of the present disclosure, and can be adjusted according to the actual application scenario, which is not limited here.

[0061] By enabling the signal at different levels, the on / off states of the two switches (eg, the first switch SW1 and the second switch SW2) can be flexibly controlled. This control method is conducive to making the circuit design more flexible, improving circuit reliability, reducing power consumption, and simplifying circuit design.

[0062] In a possible implementation, the DC common mode level INP includes a high-speed signal with a transmission rate higher than a preset threshold, and the DC common mode level INP comes from a transmitting circuit. Figure 3 A schematic diagram of a transmitting circuit according to an embodiment of the present disclosure is shown. Figure 3As shown, the transmitting circuit 3 includes N first circuits, each of which includes a fifth transistor M5 (for example, a P-type transistor), a sixth transistor M6 (for example, an N-type transistor), a first resistor R1, a second resistor R2, and a third resistor R3. The first end (for example, the source) of the fifth transistor M5 is connected to a high level (for example, a high level provided by a power supply), the second end (for example, the drain) of the fifth transistor M5 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the first end of the third resistor R3, the second end of the second resistor R2 is connected to the first end (for example, the drain) of the sixth transistor M6, the second end (for example, the source) of the sixth transistor M6 is grounded, the control end (for example, the gate) of the fifth transistor M5 is used to receive the first control signal PD, the control end (for example, the gate) of the sixth transistor M6 is used to receive the second control signal PU, and the second ends of the N third resistors R3 are connected to output the DC common mode level INP, and N is a positive integer.

[0063] According to the principle of resistance voltage division, by controlling the first control signal PD and the second control signal PU corresponding to each first circuit in the transmitting circuit 3, the switching state (for example, on or off) of the fifth transistor M5 and the sixth transistor M6 in each first circuit can be controlled, and various resistance voltage division ratios can be formed to configure the desired target amplitude level as the DC common-mode level INP.

[0064] In a possible implementation, the working status of the power supply and ground line of the comparator 2 and the transmitting circuit 3 can be confirmed. In the comparator calibration stage, the transmitting circuit 3 configures the DC common mode level INP to be the same calibration level as the reference level VREF; the first switch SW1 is disconnected, and the second switch SW2 is turned on, so that the first input terminal (positive input terminal) and the second input terminal (reverse input terminal) of the comparator 2 receive the calibration level; the comparator 2 is calibrated according to the calibration level until the comparator 2 outputs a jump signal, and the jump signal is used to indicate that the deviation calibration of the comparator 2 is completed.

[0065] Since the output end of the transmitting circuit 3 is directly connected to the first input end (positive input end) of the comparator 2 without passing through any switch, there is no parasitic resistance and parasitic capacitance introduced by the switch in the path where the first input end (positive input end) of the comparator 2 is located, which is conducive to calibrating the deviation of the comparator 2 without reducing the bandwidth design requirements, reducing the probability of attenuation of the high-frequency input signal, and improving the accuracy of the calibration of the comparator 2.

[0066] In the calibration stage, the first and second input terminals of the comparator 2 both receive the calibration level INP, that is, the input levels of the two input terminals are strictly consistent, ensuring the accuracy of the calibration. At the same time, the DC common mode level INP is configured as the same calibration level as the reference level VREF, so that the calibrated comparator has a higher accuracy when working under the reference level VREF.

[0067] Figure 4 A circuit diagram of a comparator for performing deviation calibration according to an embodiment of the present disclosure is shown. Figure 4 As shown, the comparator 2 includes a comparison module and a calibration module. The comparison module includes a first differential resistor Rd1, a second differential resistor Rd2, a first transistor M1, a second transistor M2, and a first current source I1; the calibration module includes a third transistor M3, a fourth transistor M4, and a second current source I2.

[0068] Among them, the first end of the first differential resistor Rd1 and the first end of the second differential resistor Rd2 are connected to receive the power supply signal VDD, the second end of the first differential resistor Rd1, the drain of the first transistor M1, and the drain of the third transistor M3 are connected to provide an inverted output signal VON, the second end of the second differential resistor Rd2, the drain of the second transistor M2, and the drain of the fourth transistor M4 are connected to provide a positive output signal VOP, and the gate of the first transistor M1 can be used as the first input end (positive input end) of the comparator 2 for receiving the DC common mode level INP , the gate of the second transistor M2 can be used as the second input terminal (reverse input terminal) of the comparator 2 to receive the reference level VREF, the source of the first transistor M1 and the source of the second transistor M2 are connected to the first terminal of the first current source I1, the source of the third transistor M3 and the source of the fourth transistor M4 are connected to the first terminal of the second current source I2, the gate of the third transistor M3 receives the third control signal CTRLA, the gate of the fourth transistor M4 receives the fourth control signal CTRLB, and the second terminal of the first current source I1 and the second terminal of the second current source I2 are connected to the ground.

[0069] The comparator 2 can perform deviation calibration by changing the current passing through the first differential resistor Rd1 and the second differential resistor Rd2. For example, the deviation calibration register of the comparator 2 can be set to OFST <m:0>, by changing the register control word OFST <m:0>, select to turn on the third transistor M3 or the fourth transistor M4, and change the current size of the second current source I2, adjust the current value flowing through the first differential resistor Rd1 and the second differential resistor Rd2, and change the differential output of the comparator 2 (see Figure 4 The common mode level of VOP, VON) in the register is set until the comparator 2 outputs a jump signal, indicating that the calibration of the comparator is completed. Wherein, M is a positive integer, indicating that the register OFST <m:0>It is an M+1-bit register. The embodiments of the present disclosure do not limit the number of bits of the register, and it can be set according to the actual application scenario.

[0070] By controlling the first switch SW1 and the second switch SW2 , the comparator 2 can be switched to the calibration state more quickly and flexibly.

[0071] In one possible implementation, the comparator 2 is calibrated according to the calibration level until the comparator 2 outputs a jump signal, including, when the comparator 2 outputs a steady-state signal, the comparator 2 is calibrated according to the calibration level until the comparator 2 outputs a jump signal, wherein the steady-state signal is a signal whose amplitude remains unchanged within a preset time, and the jump signal is a signal whose amplitude changes between a high level and a low level within the preset time.

[0072] Among them, when the first input terminal (positive input terminal) and the second input terminal (reverse input terminal) of comparator 2 receive the same signal (for example, a calibration level), if comparator 2 outputs a steady-state signal, it means that comparator 2 outputs an erroneous result and comparator 2 needs to be calibrated; if comparator 2 outputs a jump signal, it means that comparator 2 outputs a correct result and comparator 2 does not need to be calibrated, and comparator 2 can be directly used for comparison operations.

[0073] In order to improve the calibration efficiency of the comparator 2, when the first input terminal (positive input terminal) and the second input terminal (reverse input terminal) of the comparator 2 receive the same signal (e.g., calibration level), the output signal state of the comparator 2 can be first determined. If the comparator 2 outputs a jump signal, the calibration step can be omitted, and the comparator 2 can be used directly to perform the comparison task. If the comparator 2 outputs a steady-state signal, the comparator 2 can be calibrated according to the calibration level until the comparator 2 outputs a jump signal.

[0074] For example, assuming that comparator 2 is a dynamic comparator, the output data of comparator 2 can be read through the sampling clock. If the output maintains a steady-state signal, such as 0 or 1, the calibration module of comparator 2 can be enabled, and the register control word can be scanned until the output signal state of comparator 2 jumps from 0 to 1 or from 1 to 0; the register configuration is recorded and saved, and the calibration of comparator 2 is completed.

[0075] For example, assuming that comparator 2 is a linear comparator, the output data of comparator 2 can be read directly (without involving a sampling clock). If the output maintains a steady-state signal, such as 0 or 1, the calibration module of comparator 2 can be enabled, and the register control word can be scanned until the output signal state of comparator 2 jumps from 0 to 1 or from 1 to 0; the register configuration is recorded and saved, and the calibration of comparator 2 is completed.

[0076] This method of determining whether to calibrate the comparator 2 by judging the output signal state of the comparator 2 can improve the calibration efficiency.

[0077] After the calibration of the comparator 2 is completed, the comparator 2 can work normally and accurately compare the measured level received at its first input terminal (positive input terminal) with the reference level VREF received at its second input terminal (negative input terminal).

[0078] In a possible implementation, in the comparison stage after calibration is completed, the transmitting circuit 3 configures the DC common mode level INP to a level to be measured that is the same as or different from the reference level VREF; turns on the first switch SW1 and turns off the second switch SW2, so that the first input terminal (positive input terminal) of the comparator 2 receives the level to be measured, and the second input terminal (reverse input terminal) of the comparator 2 receives the reference level VREF; the comparator 2 compares the level to be measured with the reference level VREF to obtain a comparison result.

[0079] For example, if the level to be measured is higher than the reference level VREF, the comparison result output by comparator 2 is a high level (e.g., 1). If the level to be measured is lower than the reference level VREF, the comparison result output by comparator 2 is a low level (e.g., 0). If the level to be measured is equal to the reference level VREF, the comparison result output by comparator 2 is a transition signal (a transition from 0 to 1 or a transition from 1 to 0).

[0080] By controlling the first switch SW1 and the second switch SW2 , the comparator 2 can be switched from the calibration state to the normal working state more quickly and flexibly.

[0081] In summary, the deviation calibration circuit of the embodiment of the present disclosure changes the switch connection mode of the input terminal of the comparator 2, and reduces the number of switches on the input signal line. For example, the switch on the data signal line (for example Figure 1 The middle switch SW3), the data signal (such as the DC common mode level INP) can be directly connected to the input pair of the comparator 2, which is beneficial to reduce the parasitic resistance and capacitance of the input path of the comparator 2, reduce the attenuation of the data signal, and reduce the bit error rate of the system.

[0082] It can be understood that the above-mentioned various embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not go into details.

[0083] Figure 5 A flow chart of a deviation calibration method according to an embodiment of the present disclosure is shown as follows: Figure 5 As shown, the deviation calibration method is applied to Figure 1 The deviation calibration circuit 1 shown is used to calibrate the comparator 2. The deviation calibration circuit 1 includes a first switch SW1 and a second switch SW2. The first end of the first switch SW1 is used to receive a reference level VREF. The first end of the second switch SW2 is connected to the first input end of the comparator 2 to receive a DC common mode level INP. The second end of the first switch SW1, the second end of the second switch SW2, and the second input end of the comparator 2 are connected to each other. The DC common mode level INP comes from the transmitting circuit 3. The method includes:

[0084] In step S11, the transmitting circuit 3 configures the DC common mode level INP to be a calibration level that is the same as the reference level VREF;

[0085] In step S12, the first switch SW1 is turned off, the second switch SW2 is turned on, and the first input terminal and the second input terminal of the comparator 2 are both used to receive the calibration level;

[0086] In step S13 , the comparator 2 is calibrated according to the calibration level until the comparator 2 outputs a jump signal, wherein the jump signal is used to indicate that the deviation calibration of the comparator 2 is completed.

[0087] This method has a specific technical connection with the internal structure of the computer system, and can solve the technical problem of how to improve the hardware computing efficiency or execution effect (including reducing the amount of data storage, reducing the amount of data transmission, increasing the hardware processing speed, etc.), thereby obtaining the technical effect of improving the internal performance of the computer system in accordance with the laws of nature.

[0088] In one possible implementation, step S13 may include: when the comparator 2 outputs a steady-state signal, the comparator 2 is calibrated according to the calibration level until the comparator 2 outputs a jump signal, wherein the steady-state signal is a signal whose amplitude remains unchanged within a preset time, and the jump signal is a signal whose amplitude changes between a high level and a low level within the preset time.

[0089] In a possible implementation, the method further includes: the transmitting circuit 3 configures the DC common mode level INP to be a level to be measured that is the same as or different from the reference level VREF; turns on the first switch SW1 and turns off the second switch SW2, so that the first input terminal of the comparator 2 receives the level to be measured, and the second input terminal of the comparator 2 receives the reference level VREF; the comparator 2 compares the level to be measured with the reference level VREF to obtain a comparison result.

[0090] In a possible implementation, the control end of the first switch SW1 and the control end of the second switch SW2 are used to receive an enable signal. In response to the enable signal being at a first level EN, the first switch SW1 is turned off and the second switch SW2 is turned on; in response to the enable signal being at a second level ENB, the first switch SW1 is turned on and the second switch SW2 is turned off.

[0091] In one possible implementation, Figure 3 As shown, the transmitting circuit 3 includes N first circuits, each of which includes a fifth transistor M5, a sixth transistor M6, a first resistor R1, a second resistor R2, and a third resistor R3. The first end of the fifth transistor M5 is connected to a high level, the second end of the fifth transistor M5 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the first end of the third resistor R3, the second end of the second resistor R2 is connected to the first end of the sixth transistor M6, the second end of the sixth transistor M6 is grounded, the control end of the fifth transistor M5 is used to receive the first control signal PD, the control end of the sixth transistor M6 is used to receive the second control signal PU, the second ends of the N third resistors R3 are connected to output the DC common mode level INP, and N is a positive integer.

[0092] In a possible implementation, the comparator 2 includes a dynamic comparator and a linear comparator.

[0093] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0094] According to another aspect of the present disclosure, a chip is provided, wherein the chip includes the deviation calibration circuit 1 as described above.

[0095] According to another aspect of the present disclosure, an electronic device is provided, the electronic device comprising the above-mentioned deviation calibration circuit 1. The electronic device may be a mobile phone, a computer, a digital broadcast terminal, a message transceiver device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc., and the present disclosure does not limit this.

[0096] Based on the same concept, the present application also provides a terminal device, including a shell, a processor, a memory and the analog-to-digital converter with a deviation calibration circuit 1 described in the above embodiment, the processor and the memory are arranged in the shell, the memory is coupled to the processor, the analog-to-digital converter with the deviation calibration circuit 1 is used to convert an analog signal into a digital signal, and input the digital signal to the processor; the processor is used to process the digital signal.

[0097] The terminal device may be a mobile phone, tablet computer, television, display, laptop, user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, vehicle-mounted device, wearable device, or any other product or component with data processing function. Other essential components of the terminal device should be understood by ordinary technicians in the field, and will not be elaborated here, nor should they be used as limitations to this application.

[0098] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0099] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0100] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0101] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0102] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0103] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0104] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0105] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A deviation calibration circuit, characterized in that: The deviation calibration circuit is used to calibrate the comparator, and the deviation calibration circuit includes a first switch, a second switch, The first end of the first switch is used to receive a reference level, the first end of the second switch is connected to the first input end of the comparator to receive a DC common mode level, and the second end of the first switch, the second end of the second switch, and the second input end of the comparator are connected to each other.

2. The circuit according to claim 1, characterized in that The DC common mode level comes from a transmitting circuit, and the transmitting circuit configures the DC common mode level to be a calibration level that is the same as the reference level; Turning off the first switch and turning on the second switch so that the first input terminal and the second input terminal of the comparator receive the calibration level; The comparator is calibrated according to the calibration level until the comparator outputs a jump signal, and the jump signal is used to indicate that the deviation calibration of the comparator is completed.

3. The circuit according to claim 2, characterized in that Calibrating the comparator according to the calibration level until the comparator outputs a jump signal, comprising: When the comparator outputs a steady-state signal, the comparator is calibrated according to the calibration level until the comparator outputs a jump signal, wherein the steady-state signal is a signal whose amplitude remains unchanged within a preset time, and the jump signal is a signal whose amplitude changes between a high level and a low level within the preset time.

4. The circuit according to claim 2, characterized in that The transmitting circuit configures the DC common mode level to be a level to be measured that is the same as or different from the reference level; Turning on the first switch and turning off the second switch, so that the first input terminal of the comparator receives the level to be measured and the second input terminal of the comparator receives a reference level; The comparator compares the level to be measured with the reference level to obtain a comparison result.

5. The circuit according to any one of claims 1 to 4, characterized in that: The control end of the first switch and the control end of the second switch are used to receive an enable signal, In response to the enable signal being at a first level, turning off the first switch and turning on the second switch; In response to the enable signal being at a second level, the first switch is turned on and the second switch is turned off.

6. The circuit according to any one of claims 2 to 4, characterized in that The transmitting circuit includes N first circuits, Each first circuit includes a fifth transistor, a sixth transistor, a first resistor, a second resistor, and a third resistor. The first end of the fifth transistor is connected to a high level, the second end of the fifth transistor is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor and the first end of the third resistor, the second end of the second resistor is connected to the first end of the sixth transistor, the second end of the sixth transistor is grounded, the control end of the fifth transistor is used to receive a first control signal, and the control end of the sixth transistor is used to receive a second control signal. The second ends of N third resistors are connected to output the DC common mode level, and N is a positive integer.

7. The circuit according to any one of claims 2 to 4, characterized in that The comparator includes a dynamic comparator and a linear comparator.

8. A deviation calibration method, characterized in that: The deviation calibration method is applied to the deviation calibration circuit, which is used to calibrate a comparator. The deviation calibration circuit includes a first switch and a second switch. The first end of the first switch is used to receive a reference level. The first end of the second switch is connected to the first input end of the comparator to receive a DC common mode level. The second end of the first switch, the second end of the second switch, and the second input end of the comparator are connected to each other. The DC common mode level comes from a transmitting circuit. The method comprises: The transmitting circuit configures the DC common mode level to be a calibration level that is the same as the reference level; The first switch is turned off, and the second switch is turned on, and the first input terminal and the second input terminal of the comparator are both used to receive a calibration level; The comparator is calibrated according to the calibration level until the comparator outputs a jump signal, wherein the jump signal is used to indicate that the deviation calibration of the comparator is completed.

9. A chip, characterized in that: The chip comprises the deviation calibration circuit as claimed in any one of claims 1 to 7.

10. An electronic device, characterized in that: The electronic device comprises the offset calibration circuit as claimed in any one of claims 1 to 7.

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