Signal sampling circuit and method for signal sampling and holding

Abstract

A signal sampling circuit comprises: a plurality of sampling cells receiving an input signal for time-interleaved sampling, each sampling cell comprising: a sampling capacitor having a first plate connected to an output terminal of the sampling cell; a first plate switch between the first plate and a first reference voltage; a second plate switch between a second plate of the sampling capacitor and a second reference voltage; an input buffer for outputting a buffered input signal to a second plate; wherein the input buffer is connected to at least one power gating switch for powering off the input buffer.

Description

Technical Field

[0001] The present specification relates to a signal sampling circuit and a method for signal sampling and holding. In particular, the present specification relates to time-interleaved sampling. Background Art

[0002] Analog-to-digital converters (ADCs) are commonly used to allow digital processing of analog signals. In many applications, very high sampling speeds are required in order to convert analog signals with high frequency content into digital signals.

[0003] For high speed sampling, for example sampling speeds in the GHz range, it may not be practical to use a single sampling unit. Of course, multiple sampling units can be used, where the sampling units are arranged in parallel and provide samples that are shifted in time relative to each other, so that the multiple sampling units operate in a time-interleaved manner, thereby providing an overall high sampling speed.

[0004] The sampling circuit needs to have a high bandwidth so that it can sample input signals with high frequency content. Therefore, it is necessary to ensure a high bandwidth of the sampling circuit. It is also necessary to ensure low power consumption for sampling the input signal. Summary of the invention

[0005] An object of the present specification is to facilitate sampling of high frequency input signals. Another object of the present specification is to provide a sampling circuit with high bandwidth. Another object of the present specification is to provide a sampling circuit with low power consumption.

[0006] These and other objects of the present description are at least partly met by the invention as defined in the independent claims.Preferred embodiments are listed in the dependent claims.

[0007] According to a first aspect, a signal sampling circuit is provided, comprising: a plurality of sampling cells configured to receive an input signal for time-interleaved sampling, wherein each of the plurality of sampling cells comprises: a sampling capacitor having a first plate and a second plate, wherein the first plate is connected to an output terminal of the sampling cell; a first plate switch arranged between the first plate of the sampling capacitor and a first reference voltage, wherein the first plate switch is configured to receive a first clock signal at a gate of the first plate switch for controlling the first plate switch between an active state and an inactive state; a second plate switch arranged between the second plate of the sampling capacitor and a second reference voltage, wherein the second plate switch is configured to receive a second clock signal at a gate of the second plate switch for controlling the second plate switch between an active state and an inactive state; an input buffer configured to receive an input signal and to output a buffered input signal at an output node, wherein the output node of the input buffer is connected to the second plate of the sampling capacitor; wherein the input buffer is connected to at least one power gating switch for powering off the input buffer.

[0008] An input signal received by a signal sampling circuit is distributed to a plurality of sampling units so that the input signal is received by each sampling unit. Each sampling unit of the sampling circuit comprises an input buffer. This means that the resistance and capacitance of the network used to distribute the input signal to the sampling unit do not affect the sampling bandwidth. Therefore, the use of a plurality of input buffers (each sampling unit comprising an input buffer) ensures that a high bandwidth of the sampling circuit is provided. Each input buffer can be much smaller than a single buffer should be in order to drive a plurality of sampling units.

[0009] Due to the at least one power gate switch, the signal at the second plate of the sampling capacitor can be controlled, and the input buffer can also be powered off when the sampling unit is not used for sampling. Therefore, the sampling circuit can provide low power consumption. In addition, the resistance of the power gate switch does not affect the sampling bandwidth.

[0010] The input signal is an analog signal. The input signal may be, for example, a signal generated by a sensor, but it should be appreciated that the input signal may be any kind of analog signal.

[0011] The plurality of sampling units are configured to perform time-interleaved sampling, which means that different sampling units in the plurality of sampling units provide samples at different time points and continuously in time, so that the plurality of sampling units can provide an overall high sampling rate, while each individual sampling unit has a relatively low sampling rate.

[0012] The sampling unit may provide a sampled output signal at an output of the sampling unit. The sampling unit may be configured to hold the sampled output signal at the output. The sampling unit may be configured to form a sample and hold unit.

[0013] The sampling unit may further be connected to an analog-to-digital converter (ADC). The ADC may be connected to an output of the sampling unit to receive the sampled values ​​and may be configured to convert the sampled values ​​into a digital representation. Each sampling unit may be connected to a corresponding ADC.

[0014] The first reference voltage and the second reference voltage may each be provided by a fixed voltage available to the signal sampling circuit. The first reference voltage is different from the second reference voltage.

[0015] For example, the first reference voltage may be a lower voltage level supplied to the sampling circuit (such as a ground voltage), and the second reference voltage may be a higher voltage level supplied to the sampling circuit (such as a voltage based on a power supply voltage of the circuit). However, it should be appreciated that the first reference voltage may instead be based on a power supply voltage and the second reference voltage may be a ground voltage.

[0016] The switch can be provided as a transistor switch. Therefore, the switches can each be formed by a transistor, and the transistor includes a source, a drain and a gate. The switch can be configured to receive a signal at the gate for controlling whether the channel between the source and the drain is disconnected or closed. Therefore, the transistor can be operated as a switch and can be controlled by a signal at the gate. It should be appreciated that the switch can also be formed by more than one transistor, such as using a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor, wherein the NMOS transistor can be configured to receive a first clock signal at the gate of the NMOS transistor, and the PMOS transistor can be configured to receive the inverse of the first clock signal at the gate of the PMOS transistor.

[0017] The term "first plate switch" is used herein to denote a switch connected to the first plate of the sampling capacitor. Thus, the first plate switch may control the connection between the first plate of the sampling capacitor and the first reference voltage to be opened or closed. Thus, the first plate switch may provide that the connection between the first plate of the sampling capacitor and the first reference voltage is closed in an active state of the first plate switch, and the first plate switch may provide that the connection between the first plate of the sampling capacitor and the first reference voltage is open in an inactive state of the first plate switch.

[0018] The term "second plate switch" is used herein to denote a switch connected to the second plate of the sampling capacitor. Thus, the second plate switch may control whether the connection between the second plate of the sampling capacitor and the second reference voltage is opened or closed. Thus, the second plate switch may provide that the connection between the second plate of the sampling capacitor and the second reference voltage is closed in an active state of the second plate switch, and the second plate switch may provide that the connection between the second plate of the sampling capacitor and the second reference voltage is open in an inactive state of the second plate switch.

[0019] An input buffer is a buffer amplifier that provides an electrical impedance transformation from an input of the input buffer to an output of the input buffer. The input buffer may provide unity gain so that the signal level does not change between the input and output of the input buffer. The input buffer may be a voltage buffer amplifier.

[0020] According to one embodiment, at least one power-gating switch includes an interrupt switch arranged between a connection to a low voltage level of an input buffer and a connection to a high voltage level of the input buffer, wherein the interrupt switch is configured to receive a second clock signal at a gate of the interrupt switch for controlling the interrupt switch between an active state and an inactive state.

[0021] Thus, the input buffer can be connected to a low voltage level, such as a ground voltage, as well as a high voltage level, such as a power supply voltage of the circuit. The interrupt switch can be configured to interrupt the path from the power supply voltage to ground so that the interrupt switch can be used to power off the input buffer. A low voltage level is referred to as being lower than a high voltage level, such that the low voltage level is lower than the high voltage level.

[0022] The interrupt switch can be placed anywhere in the path from the low voltage level to the high voltage level relative to the input buffer. The interrupt switch can thus be arranged between the input buffer and the connection to the high voltage level or between the input buffer and the connection to the low voltage level.

[0023] The signal sampling circuit may comprise a single interrupt switch. This means that the signal sampling circuit may be controlled using only the first and second clock signals. For high operation, the clock signal needs to be a high frequency signal providing a steep edge to properly control the sampling unit. Therefore, the process for generating the clock signal may require high power consumption. Therefore, by ensuring that only the first and second clock signals need to be generated, low power consumption is ensured.

[0024] The output of the input buffer is connected to the second plate. The second plate switch can also ensure that the node of the input buffer is pulled up to the second reference voltage which can correspond to the high voltage level. This means that a single interrupt switch can be arranged between the input buffer and the connection to the low voltage level, while still ensuring that the input buffer can be powered off. Accordingly, if the second reference voltage corresponds to the low voltage level, a single interrupt switch can be arranged between the input buffer and the connection to the high voltage level.

[0025] According to one embodiment, the interrupt switch is a first interrupt switch arranged between the input buffer and the low voltage level, and wherein the at least one power-gating switch further comprises a second interrupt switch arranged between the input buffer and the high voltage level, wherein the second interrupt switch is configured to receive a third clock signal at a gate of the second interrupt switch for controlling the second interrupt switch between an active state and an inactive state, wherein the third clock signal is an inverse of the second clock signal.

[0026] Therefore, the signal sampling circuit may include two interrupt switches. The two interrupt switches may be used to ensure that the input buffer is powered off. However, the two interrupt switches may need to provide a third clock signal, which requires additional power consumption to generate the third clock signal.

[0027] According to another embodiment, the input buffer includes a bias transistor for providing a bias signal of the input buffer, wherein at least one power gate switch includes a bias switch connected to a gate of the bias transistor, wherein the bias switch is configured to selectively connect a control voltage of the bias transistor to a bias voltage or a fixed reference voltage corresponding to an active state and an inactive state of the input buffer, respectively.

[0028] The input buffer may thus be provided with a bias signal and the input buffer may be powered down by disabling the bias switch.Thus, at least one power gating switch may be implemented by a bias switch which may be configured to power down the input buffer by disabling a connection to a gate of a bias transistor.

[0029] According to an embodiment, the input signal is a differential input signal including a positive input signal and a negative input signal, and wherein for each sampling unit, the sampling capacitor is a first sampling capacitor, the first plate switch is connected to a first output terminal of the sampling unit, and the input buffer is a first input buffer, wherein the first input buffer is configured to receive the positive input signal and is configured to output a buffered positive input signal at a second plate of the first sampling capacitor, and wherein each sampling unit further comprises: a second sampling capacitor having a third plate and a fourth plate, wherein the third plate is connected to the second output terminal of the sampling unit; a third plate switch arranged between the third plate of the second sampling capacitor and the first reference voltage, wherein the third plate switch is configured to receive a signal for receiving a voltage at a gate of the third plate switch for receiving a voltage ... a first clock signal that controls the third plate switch between an active state and an inactive state; a fourth plate switch disposed between a fourth plate of the second sampling capacitor and a second reference voltage, wherein the fourth plate switch is configured to receive at a gate of the fourth plate switch a second clock signal that controls the fourth plate switch between an active state and an inactive state; a second input buffer that is configured to receive a negative input signal and is configured to output a buffered negative input signal at a second output node, wherein a second output node of the second input buffer is connected to the fourth plate of the second sampling capacitor; wherein the first input buffer is connected to the second input buffer via at least one power gating switch, the at least one power gating switch comprising a shared switch for powering down the first and second input buffers.

[0030] This means that each sampling unit may be adapted to sample a differential input signal, which provides a positive sampled output signal at a first output terminal of the sampling unit and a negative sampled output signal at a second output terminal of the sampling unit.

[0031] The sampling circuit may comprise a shared switch for powering down the first and second input buffers. This means that the first and second input buffers may be powered down in an energy-saving manner.

[0032] Furthermore, the use of a shared switch ensures that any mismatch between the two different switches used for each of the first and second input buffers, respectively, is eliminated.

[0033] The term "third plate switch" is used herein to denote a switch connected to a third plate belonging to the second sampling capacitor. Thus, the third plate switch may control whether the connection between the third plate of the second sampling capacitor and the first reference voltage is opened or closed. Thus, the third plate switch may provide that the connection between the third plate of the second sampling capacitor and the first reference voltage is closed in an active state of the third plate switch, and the third plate switch may provide that the connection between the third plate of the second sampling capacitor and the first reference voltage is opened in an inactive state of the third plate switch.

[0034] The term "third plate switch" is used herein to denote a switch connected to a fourth plate belonging to the second sampling capacitor. Thus, the fourth plate switch may control the connection between the fourth plate of the second sampling capacitor and the second reference voltage to be opened or closed. Thus, the fourth plate switch may provide that the connection between the fourth plate of the second sampling capacitor and the second reference voltage is closed in an active state of the fourth plate switch, and the fourth plate switch may provide that the connection between the fourth plate of the second sampling capacitor and the second reference voltage is open in an inactive state of the fourth plate switch.

[0035] According to an embodiment, a ground connection of the first input buffer is connected to a ground connection of the second input buffer, wherein the shared switch is arranged between the ground and the first and second input buffers.

[0036] The interrupt switch may be configured to interrupt a path from the supply voltage to ground such that the interrupt switch may be used to power off the first and second input buffers.

[0037] The outputs of the first and second input buffers are connected to the second plate of the first sampling capacitor and the fourth plate of the second sampling capacitor, respectively. The second and fourth plate switches can also ensure that the nodes of the input buffers are pulled up to a second reference voltage, which can correspond to a high voltage level and ensure that the input buffers are completely disabled. This means that a single shared switch can be arranged between the input buffer and a connection to a low voltage level (such as ground) while still ensuring that the input buffer can be powered off. Accordingly, if the second reference voltage corresponds to a low voltage level, a shared switch can be arranged between the input buffer and the connection to the high voltage level. According to yet another alternative, the first and second input buffers can share a bias transistor, which can be selectively connected to a bias voltage or a fixed reference voltage.

[0038] According to an embodiment, each sampling unit further comprises a fifth switch arranged between the second plate of the first sampling capacitor and the fourth plate of the second sampling capacitor, wherein the fifth switch is configured to receive a second clock signal at a gate of the fifth switch for controlling the fifth switch between an active state and an inactive state.

[0039] The term “fifth switch” is used herein to refer to a switch connected to the second plate of the first sampling capacitor and the fourth plate of the second sampling capacitor.

[0040] Additionally or alternatively, each sampling unit further comprises a sixth switch arranged between the first plate of the first sampling capacitor and the third plate of the second sampling capacitor, wherein the sixth switch is configured to receive a first clock signal at a gate of the sixth switch for controlling the sixth switch between an active state and an inactive state.

[0041] The term “sixth switch” is used herein to refer to a switch connected to the first plate of the first sampling capacitor and the third plate of the second sampling capacitor.

[0042] The fifth and sixth switches may be used to reduce the differential resistance of the signal sampling circuit for the same clock signal load. Alternatively, the fifth and sixth switches may be used to reduce the load of the clock signal for the same resistance of the signal sampling circuit.

[0043] It should be appreciated that the signal sampling circuit may include only the fifth switch or only the sixth switch. Alternatively, the signal sampling circuit may include both the fifth switch and the sixth switch.

[0044] Using equal sizes for the second and fourth plate switches and / or using the same sizes for the first and third plate switches may facilitate sizing of switches used to control resistance of a signal sampling circuit and / or a load of a clock signal.

[0045] According to an embodiment, the second and fourth plate switches have equal dimensions related to the dimensions of the fifth switch.

[0046] The relationship between the size of the fifth switch and the size of the second and fourth board switches can be defined depending on whether the resistance of the signal sampling circuit or the load of the clock signal is to be controlled. Therefore, the size of the fifth switch can be designed to have a desired relationship with the size of the second and fourth board switches.

[0047] Additionally or alternatively, the first and third plate switches may have equal dimensions related to the dimensions of the sixth switch.

[0048] The relationship between the size of the sixth switch and the size of the first and third board switches can be defined depending on whether the resistance of the signal sampling circuit or the load of the clock signal is to be controlled. Therefore, the size of the sixth switch can be designed to have a desired relationship with the size of the first and third board switches.

[0049] According to an embodiment, different sampling units are configured to receive different clock signals which are phase shifted with respect to each other.

[0050] This can be used to ensure that different sampling units provide samples at different time points in a time-interleaved manner.

[0051] According to an embodiment, the signal sampling circuit further comprises a distribution network for distributing the input signal to each sampling unit.

[0052] The distribution network may be formed of passive components (such as only wires) for connecting the input signal to each sampling unit. The distribution network may thus provide passive routing of the input signal to each sampling unit. However, it should be appreciated that the distribution network may be more complex and may, for example, include inductors for increasing the bandwidth of the distribution network.

[0053] Since each sampling unit includes an input buffer, the resistance and capacitance of the distribution network do not affect the sampling bandwidth. Since the size of the input buffer within the sampling unit is reduced compared to a single buffer used to drive multiple sampling units, the impact on the distribution network bandwidth can be small.

[0054] According to an embodiment, the first reference voltage is a ground voltage.

[0055] This is a suitable way to implement a signal sampling circuit.

[0056] According to a second aspect, a method for sampling and holding a signal using a plurality of sampling units for time-interleaved sampling is provided, the method comprising, by each of the plurality of sampling units: receiving an input signal at an input buffer; controlling the input buffer to be active; providing a buffered input signal from the input buffer at a second plate of a sampling capacitor; providing a sampled output signal at an output of the sampling unit connected to a first plate of the sampling capacitor by opening a first plate switch between the first plate of the sampling capacitor and a first reference voltage; thereafter holding the sampled output signal at the output by closing a second plate switch between the second plate of the sampling capacitor and a second reference voltage; and powering down the input buffer by controlling at least one power gating switch.

[0057] The effects and features of the second aspect are largely similar to the effects and features described above in conjunction with the first aspect. The embodiments mentioned with respect to the second aspect are largely compatible with the first aspect.

[0058] Since the input signal is buffered by the input buffer at each sampling unit, the resistance and capacitance of the network used to distribute the input signal to the sampling units will not affect the sampling bandwidth. Therefore, this method can ensure that a high sampling bandwidth is provided.

[0059] The input buffer can be powered down while the sampled output signal is held at the output of the sampling unit. This means that the method is energy efficient.

[0060] At least one power gate switch can be in an active state to control the input buffer to be active. The at least one power gate switch can also be in an inactive state to power off the input buffer.

[0061] According to an embodiment, the method further comprises receiving, by each sampling unit of the plurality of sampling units, first and second clock signals for controlling the first and second board switches, wherein different sampling units receive different clock signals phase-shifted relative to each other.

[0062] This means that the phase-shifted clock may control the sampling unit to provide sequential samples of the input signal such that time-interleaved sampling is provided.

[0063] The method may include controlling the first plate switch based on a first clock signal at a gate of the first plate switch, wherein the first clock signal controls the first plate switch between an active state and an inactive state. The first clock signal may control the first plate switch to be in an inactive state to open the first plate switch.

[0064] The method may further include controlling the second plate switch based on a second clock signal at a gate of the second plate switch, wherein the second clock signal controls the first plate switch between an active state and an inactive state. The second clock signal may control the second plate switch to be in an active state to close the second plate switch, whereby the sampled output signal is held at an output of the sampling unit.

[0065] The at least one power gated switch may be a single power gated switch. The method may further include powering off the input buffer by controlling the single power gated switch using the second clock signal. Thus, the second clock signal may be used to control both the at least one power gated switch and the second board switch. This means that the power consumption for generating the clock signal is reduced compared to generating separate clock signals for controlling the power gated switch and the second board switch.

[0066] The input signal may be a differential input signal including a positive input signal and a negative input signal. The input buffer of each sampling unit is a first input buffer, the sampling capacitor of each sampling unit is a first sampling capacitor, and the output end of the sampling unit is a first output end. The method may then include receiving a positive input signal at the first input buffer by each sampling unit, controlling the first input buffer to be active, providing a buffered positive input signal from the first input buffer at the second plate of the first sampling capacitor, providing a sampled positive output signal at the first output end of the sampling capacitor by opening a first plate switch between the first plate of the first sampling capacitor and a first reference voltage, and thereafter maintaining the sampled positive output signal at the first output end by closing a second plate switch between the second plate of the first sampling capacitor and a second reference voltage. The method may also include receiving a negative input signal at the second input buffer by each sampling unit,

[0067] The second input buffer is controlled to be active, a buffered negative input signal from the second input buffer is provided at a fourth plate of the second sampling capacitor, a sampled negative output signal is provided at a second output terminal of the second sampling capacitor by opening a third plate switch between a third plate of the second sampling capacitor and a first reference voltage, and thereafter the sampled negative output signal is maintained at the second output terminal by closing a fourth plate switch between a fourth plate of the second sampling capacitor and a second reference voltage. The method may also include powering off the first and second input buffers by each sampling unit by controlling a shared switch of at least one power gating switch.

[0068] This means that the method can be adapted to sample a differential input signal. The method can also use a shared switch to power down the first and second input buffers. This means that the first and second input buffers can be powered down in an energy-saving manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The above content and additional objects, features and advantages of the present specification will be better understood through the following illustrative and non-limiting detailed description with reference to the accompanying drawings. Unless otherwise specified, the same reference numerals will be used for the same elements in the accompanying drawings.

[0070] Figure 1 is a schematic diagram of a signal sampling circuit according to an embodiment.

[0071] Figure 2 is a schematic diagram of a sampling unit according to the first embodiment.

[0072] Figure 3 is a schematic diagram of a sampling unit according to a second embodiment.

[0073] Figure 4 is a schematic diagram of a sampling unit according to a third embodiment.

[0074] Figure 5 is a schematic diagram of a sampling unit according to a fourth embodiment.

[0075] Figure 6 is a flow chart of a method according to an embodiment. DETAILED DESCRIPTION

[0076] Reference now Figure 1 , a signal sampling circuit 100 will be described. The signal sampling circuit 100 may include an input node 102 for receiving an input signal. The input signal may be any analog signal that is to be sampled to generate a digital representation of the analog signal. For example, the input signal may be a signal from a sensor.

[0077] The signal sampling circuit 100 may include a matching network 104 connected to the input node 102. The matching network 104 may be configured to adjust the input impedance of the distribution network in conjunction with the signal sampling circuit 100 to ensure that the input signal is properly transmitted from the input node 102 to the signal sampling circuit 200.

[0078] The signal sampling circuit 100 may further include a distribution network 106. The distribution network 106 may be configured to distribute an input signal received at the input node 102 to each of the plurality of sampling cells 110a-c.

[0079] The distribution network may be formed of passive components (such as only wires) for connecting the input signal to each of the sampling cells 110a-c. The distribution network 106 may thus provide passive routing of the input signal to each of the sampling cells 110a-c. However, it should be appreciated that the distribution network may be more complex and may, for example, include inductors for increasing the bandwidth of the distribution network 106.

[0080] The signal sampling unit 100 uses a plurality of sampling units 110a-c so that the sampling units 110a-c can sequentially provide samples of the input signal. This means that each sampling unit 110a-c does not need to have a very high sampling rate, while any combination of the plurality of sampling units 110a-c provides a high sampling rate.

[0081] The plurality of sampling units 110a-c may thus provide time-interleaved sampling, thereby providing a sample sequence comprising a plurality of sub-sample sequences. Each sub-sequence may include one sample from each of the sampling units 110a-c, wherein samples from different sampling units 110a-c represent input signals at different points in time. Thus, two samples from a single sampling unit are interleaved with samples from other sampling units.

[0082] Figure 1 The signal sampling circuit 100 is shown as having three sampling units 110a-c. It should be appreciated that the number of sampling units may be greater and a small number of sampling units is shown for simplicity. The number of sampling units may depend on the desired total sampling rate. In some embodiments, the number of sampling units may be at least four or at least eight.

[0083] The sampling units 110a-c may be controlled to provide samples at different time points. The sampling units 110a-c may receive clock signals that control the timing of the samples at the respective sampling units 110a-c. The clock signals may be phase-shifted relative to each other to achieve time-interleaved sampling, such as Figure 1 As shown in the clock signals CK1, CK2, and CK3.

[0084] The signal sampling circuit 100 may be used to sample input signals having high frequency content. Therefore, the signal sampling circuit 100 may require a high bandwidth.

[0085] If the signal sampling circuit includes a plurality of parallel input buffers between the matching network 104 and the distribution network 106, the bandwidth BW of the signal sampling circuit can be expressed as:

[0086]

[0087] Where R in is the output impedance of the color, R dist is the resistance of the distribution network from the input buffer to the sampling unit, C in is the parasitic capacitance of the color, C dist is the capacitance of the distribution network from the input buffer to the sampling unit, N ov is the number of overlapping clock signals used to provide time-interleaved sampling by the sampling unit, C sample is the capacitance of the sampling capacitor of the corresponding sampling unit, N buffers is the number of parallel input buffers, IL is the number of interleaved sampling units, C sw is the total capacitance of the switches of each sampling unit, and R sw is the total resistance of the switches of each sampling unit.

[0088] Sampling units 110a-c according to various embodiments will now be described in more detail. It should be appreciated that any of the sampling units described below may be used in Figure 1 The signal sampling circuit 100 is shown.

[0089] Reference now Figure 2 , a sampling unit 210 according to a first embodiment will be discussed. A single sampling unit 210 is described, and it should be appreciated that each of a plurality of sampling units may be implemented in the same manner.

[0090] The sampling unit 210 comprises an input 212 for receiving an input signal from the distribution network 106. The sampling unit 210 further comprises an input buffer 214 configured to receive the input signal from the input 212.

[0091] Therefore, the signal sampling circuit 100 provides an input buffer 214 in each sampling unit 210, so that no input buffer is required between the matching network 104 and the distribution network 106. This means that the resistance and capacitance of the distribution network 106 can be removed from the above formula that defines the bandwidth of the signal sampling circuit 100, thereby increasing the bandwidth. Instead, the distribution network 106 becomes a load for the matching network 104, and the matching network 104 can be easily adjusted accordingly. In addition, the number of overlapping clocks N in the above formula is ovis reduced to one, which further increases the sampling bandwidth.

[0092] The input buffer 214 is configured to output a buffered input signal at an output node of the input buffer 214. The input buffer 214 may be implemented by a buffer amplifier that may have unity gain.

[0093] The sampling unit 210 also includes a sampling capacitor 220 having a first plate 222 and a second plate 224. The first plate 222 is connected to a first reference voltage and the second plate 224 is connected to a second reference voltage. The first reference voltage may be less than the second reference voltage. For example, Figure 2 As shown, the first reference voltage may be a ground voltage, and the second reference voltage may be a power supply voltage V DD The first plate 222 may then be referred to as the bottom plate of the sampling capacitor 220, and the second plate 224 may be referred to as the top plate of the sampling capacitor 220. However, it should be appreciated that the first reference voltage may instead be greater than the second reference voltage.

[0094] The second plate 224 of the sampling capacitor 220 is connected to the output node of the input buffer 214. Thus, the sampling capacitor 220 is configured to receive the buffered input signal at the second plate 224 of the sampling capacitor 220.

[0095] A first plate 222 of the sampling capacitor 220 is connected to the output 216 of the sampling unit 210. The sampling capacitor 220 may be controlled to provide a sample of the input signal and hold the sample at the output 216.

[0096] The sampling unit 210 includes a first plate switch 230 and a second plate switch 234 for controlling sampling by the sampling unit 210. The first plate switch 230 is arranged between the first plate 222 of the sampling capacitor 220 and the first reference voltage, and the second plate switch 234 is arranged between the second plate 224 of the sampling capacitor 220 and the second reference voltage.

[0097] Each of the first plate switch 230 and the second plate switch 234 may be implemented by a transistor operating as a switch, wherein a signal at a gate controls whether a channel between a source and a drain is opened or closed for opening or closing the switch.

[0098] Therefore, the first board switch 230 includes a gate 232 and is configured to receive a first clock signal for controlling the first board switch 230 between an active state and an inactive state at the gate 232. In the active state, the first board switch 230 is closed. In the inactive state, the first board switch 230 is open.

[0099] Similarly, the second board switch 234 includes a gate 236 and is configured to receive a second clock signal for controlling the second board switch 234 between an active state and an inactive state at the gate 236. In the active state, the second board switch 234 is closed. In the inactive state, the second board switch 234 is open.

[0100] The first board switch 230 may be implemented by an n-type metal oxide semiconductor (NMOS) transistor, such as Figure 2 In this case, when the clock signal is high, the switch is in an active state, and when the clock signal is low, the switch is in an inactive state. In addition, the second board switch 234 can be implemented by a p-type metal oxide semiconductor (PMOS) transistor, such as Figure 2 In this case, when the clock signal is low, the switch is active, and when the clock signal is high, the switch is inactive.

[0101] However, if the first reference voltage is greater than the second reference voltage, the first plate switch 230 may instead be implemented by a PMOS transistor, and the second plate switch 234 may be implemented by an NMOS transistor.Each switch may also be implemented by a combination of PMOS and NMOS transistors.

[0102] The first clock signal CK e and the second clock signal CK Figure 2 The first clock signal CK e May be referred to as an "early clock" and is almost identical to the second clock signal, but changes from the track state to the hold state slightly earlier than the second clock signal. The first and second clock signals can be generated relatively easily. The second clock signal can be generated based on the first clock signal by providing a short delay of the first clock signal used to form the second clock signal. For high speed clock signals, a common clock signal can be used to create the first and second clock signals from drivers of different sizes. This means that the first and second clock signals can be generated using low power consumption.

[0103] The input buffer 214 is also connected to two power gate switches, namely a first interrupt switch 238 and a second interrupt switch 242. The first interrupt switch 238 is arranged between the input buffer 214 and a connection to a low voltage level of the input buffer 214. The second interrupt switch 242 is arranged between the input buffer 214 and a connection to a high voltage level of the input buffer 214. The low voltage level may be a ground voltage V SS , the high voltage level can be the power supply voltage V DD .

[0104] Each of the first interrupter switch 238 and the second interrupter switch 242 may be implemented by a transistor operating as a switch, wherein a signal at a gate controls whether a channel between a source and a drain is opened or closed for opening or closing the switch.

[0105] The first interrupt switch 238 includes a gate 240 and is configured to receive a second clock signal for controlling the first interrupt switch 238 between an active state and an inactive state at the gate 240. In the active state, the first interrupt switch 238 is closed. In the inactive state, the first interrupt switch 238 is open. The first interrupt switch 238 may be implemented as an NMOS transistor.

[0106] The second interrupt switch 242 includes a gate 244 for controlling the second interrupt switch 242 between an active state and an inactive state. In the active state, the first interrupt switch 242 is closed. In the inactive state, the first interrupt switch 242 is open. The second interrupt switch 242 may be implemented as a PMOS transistor. The second interrupt switch 242 may be configured to receive a third clock signal at the gate of the second interrupt switch 242. The third clock signal is the inverse of the clock signal, which means that the first and second interrupt switches 238 , 242 are active at the same time.

[0107] The first and second interrupt switches 238, 242 provide for the input buffer 214 to be in a high impedance output state. This corresponds to opening the switch between the input buffer 214 and the second plate 224 of the sampling capacitor 220. Thus, the arrangement of the first and second interrupt switches 238, 242 means that no sampling switch is required between the input buffer 214 and the second plate 224 of the sampling capacitor 220.

[0108] When the first and second clock signals are high and the third clock signal is low, the signal at the second plate 224 of the sampling capacitor 220 of the sampling unit 210 tracks the input signal while the first plate 222 is maintained at the first reference voltage. When the first clock signal goes low to fix the charge stored in the sampling capacitor 220, the first plate switch 230 receiving the first clock signal opens slightly earlier than the first and second interrupt switches 238, 242. This means that the input signal is sampled onto the sampling capacitor 220. Thereafter, the signal from the input buffer 214 is disconnected from the second plate 224 of the sampling capacitor 220 by the second clock signal and the third clock signal received by the first and second interrupt switches 238, 242 causing the first and second interrupt switches 238, 242 to take an inactive state. In addition, when the second clock signal goes low, the second plate switch 234 receiving the second clock signal closes so that the second plate 224 of the sampling capacitor 220 is pulled to the second reference voltage. Due to charge conservation, this means that the sampled input signal now appears at the first plate 222 of the sampling capacitor 220 to provide a sampled output signal at the output 216 for analog-to-digital conversion.

[0109] The first plate switch 230 may be referred to as a sampling switch and the second plate switch 234 may be referred to as a holding switch.

[0110] Each sampling unit 210 may be followed by an analog-to-digital converter (ADC). The ADC may receive the sampled output signal of the sampling unit 210 and may convert the sampled output signal into a digital representation.

[0111] Since the first interrupt switch 238 and the second interrupt switch 242 are disposed between the input buffer 214 and the connections to the low and high voltage levels, respectively, the resistance of the first interrupt switch 238 and the second interrupt switch 242 do not affect the bandwidth of the signal sampling circuit 100 .

[0112] The first interrupter switch 238 and the second interrupter switch 242 are connected to the sources of the switches 238, 242 connected to a fixed voltage, a low voltage level, and a high voltage level, respectively. In addition, the first and second interrupter switches 238, 242 have a maximum driving voltage equal to the power supply voltage of the circuit 100. This means that the first interrupter switch 238 and the second interrupter switch 242 can have a small size so that the first interrupter switch 238 and the second interrupter switch 242 require low power to drive the switches.

[0113] In addition, the arrangement of the first and second interrupt switches 238, 242 in relation to the input buffer 214 in the path from a low voltage level to a high voltage level means that when the first and second interrupt switches 238, 242 assume an inactive state and are open, the input buffer 214 is powered off. This means that the power consumption of the sampling unit 210 can be lower because the input buffer 214 is powered off when not in use.

[0114] It should be appreciated that the sampling unit may include a switch that controls a signal at the gate of a bias transistor of the input buffer, rather than the first and second interrupt switches 238, 242 associated with the input buffer 214 in the path from the low voltage level to the high voltage level. Thus, the input buffer may include a bias transistor for providing a bias signal for the input buffer. At least one power gate switch of the sampling unit may be implemented by a bias switch connected to the gate of the bias transistor.

[0115] The bias switch may be implemented by two transistors operating as switches, wherein a signal at each gate of the transistor controls whether the channel between the source and the drain is open or closed for opening or closing the switch.

[0116] Thus, the bias switch comprises a gate and is configured to receive at the gate a second clock signal for controlling the bias switch between two states. In a first state, the bias switch brings a bias voltage to the gate of the bias transistor, which corresponds to an active state of the input buffer. In a second state, the bias switch brings a reference voltage to the gate of the bias transistor, which causes the bias transistor to be in an inactive state corresponding to powering off the input buffer.

[0117] Reference now Figure 3 , a sampling unit 310 according to a second embodiment will be discussed. A single sampling unit 310 is described, and it should be appreciated that each of a plurality of sampling units may be implemented in the same manner.

[0118] The sampling unit 310 is similar to the sampling unit 210 described above. The only differences between the sampling unit 310 and the sampling unit 210 will be described below. Similar to the sampling unit 210, the sampling unit 310 includes an input terminal 312, an input buffer 314, a sampling capacitor 320 having a first plate 322 and a second plate 324, the first plate 322 being connected to the output terminal 316 of the sampling unit 310. In addition, the sampling unit 310 includes a first plate switch 330 having a gate 332 configured to receive a first clock signal and a second plate switch 334 having a gate 336 configured to receive a second clock signal.

[0119] The sampling unit 310 includes only a single power gated switch connected to the input buffer 314. Therefore, the sampling unit 310 includes an interrupt switch 338 arranged between the input buffer 314 and a connection to a low voltage level of the input buffer 314, such as a ground voltage.

[0120] The interrupt switch 338 may be implemented by a transistor operating as a switch, wherein a signal at a gate 340 of the interrupt switch 338 controls whether a channel between a source and a drain is opened or closed for opening or closing the switch.

[0121] The interrupt switch 338 is configured to receive a second clock signal at a gate 340 for controlling the interrupt switch 238 between an active state and an inactive state. In the active state, the interrupt switch 338 is closed. In the inactive state, the interrupt switch 338 is open. The first interrupt switch 338 may be implemented as an NMOS transistor.

[0122] When the second clock signal is low, the interrupt switch 338 is turned off, so that the power supply in the input buffer 314 is cut off to a low voltage level via the interrupt switch 338. However, compared with the first embodiment, the input buffer 314 is not necessarily in a completely high impedance state, because only the conductive path from the input buffer 314 to the low voltage level is cut off. The input buffer 314 still has a high voltage level (e.g., V DD ). However, when the second clock signal is low, the second board switch 324 is closed. This means that the output node of the input buffer 314 is connected to the second reference voltage (such as V DD ) to pull the output node to V DD As a result, all nodes of input buffer 314 are pulled to V DD .

[0123] This means that the second interrupt switch 242 of the first embodiment may not be necessary. This also means that the sampling unit 310 does not need a third clock signal. By eliminating the need to generate a third clock signal, energy is saved in clock generation.

[0124] It should be recognized that Figure 3 The opposite implementation of the embodiment shown is possible. Thus, the input buffer may alternatively include a single interrupt switch arranged between the input buffer and the connection to the high voltage level of the input buffer. Furthermore, the second fixed reference voltage may be a ground voltage so as to pull the output node of the input buffer to ground instead.

[0125] Reference now Figure 4 , a sampling unit 410 according to a third embodiment will be discussed. A single sampling unit 410 is described, and it should be appreciated that each of a plurality of sampling units may be implemented in the same manner.

[0126] The sampling unit 410 is similar to the above-described sampling unit 310. However, the sampling unit 410 is configured to receive a differential input signal including a positive input signal and a negative input signal. This means that the circuitry of the sampling unit 310 is repeated to process both positive and negative input signals.

[0127] Thus, the sampling unit 410 includes a first component configured to sample a positive input signal. The first component includes a first input terminal 412a for receiving the positive input signal, a first input buffer 414a, a first sampling capacitor 420a having a first plate 422a and a second plate 424a, the first plate 422a being connected to a first output terminal 416a of the sampling unit 410. Furthermore, the sampling unit 410 includes a first plate switch 430a having a gate 432a configured to receive a first clock signal and a second plate switch 434a having a gate 436a configured to receive a second clock signal.

[0128] Similarly, the sampling unit 410 includes a second component configured to sample the negative input signal. The second component includes a second input terminal 412b for receiving the negative input signal, a second input buffer 414b, a second sampling capacitor 420b having a third plate 422b and a fourth plate 424b, and the third plate 422b is connected to the second output terminal 416b of the sampling unit 410. In addition, the sampling unit 410 includes a first plate switch 430b having a gate 432b configured to receive the first clock signal and a second plate switch 434b having a gate 436b configured to receive the second clock signal.

[0129] The first input buffer 414a is connected to the second input buffer 414b in a path to a low voltage level. Thus, the sampling unit 410 may include a single power gate switch associated with the first input buffer 414a and the second input buffer 414b.

[0130] The sampling unit 410 therefore comprises a shared switch 438 arranged between each of the first input buffer 414a and the second input buffer 414b and a connection to a low voltage level of the input buffer, such as a ground voltage.

[0131] The shared switch 438 may be implemented by a transistor operating as a switch, wherein a signal at a gate 440 of the shared switch 438 controls whether a channel between a source and a drain is opened or closed for opening or closing the switch.

[0132] The shared switch 438 is configured to receive a second clock signal at a gate 440 for controlling the shared switch 438 between an active state and an inactive state. In the active state, the shared switch 438 is closed. In the inactive state, the shared switch 438 is open. The shared switch 438 may be implemented as an NMOS transistor.

[0133] When the second clock signal is low, the sharing switch 438 is turned off so that the power supply in each of the first input buffer 414 a and the second input buffer 414 b is cut off to a low voltage level via the sharing switch 438 .

[0134] Using a shared switch 438 instead of two different switches each for one of the input buffers 414a, 414b means that mismatches between the two different switches are avoided.

[0135] Reference now Figure 5 , a sampling unit 510 according to a fourth embodiment will be discussed. A single sampling unit 510 is described, and it should be appreciated that each of a plurality of sampling units may be implemented in the same manner.

[0136] The sampling unit 510 is similar to the sampling unit 410 described above, and is also configured to receive a differential input signal including a positive input signal and a negative input signal.

[0137] Thus, the sampling unit 510 includes a first component configured to sample a positive input signal. The first component includes a first input terminal 512a for receiving a positive input signal, a first input buffer 514a, a first sampling capacitor 524a having a first plate 520a and a second plate 522a, and the first plate 522a is connected to a first output terminal 516a of the sampling unit 510. In addition, the sampling unit 510 includes a second component configured to sample a negative input signal. The second component includes a second input terminal 512b for receiving a negative input signal, a second input buffer 514b, a second sampling capacitor 520b having a third plate 522b and a fourth plate 524b, and the third plate 522b is connected to a second output terminal 516b of the sampling unit 510.

[0138] exist Figure 5 In the illustrated embodiment, the sampling unit 510 includes a shared switch 538 disposed between each of the first input buffer 514a and the second input buffer 514b and a connection to a low voltage level (such as a ground voltage) of the input buffer. The shared switch 538 is configured to receive a second clock signal at a gate 540 for controlling the shared switch 538 between an active state and an inactive state. However, it should be appreciated that separate power gating switches may be used for the first input buffer 514a and the second input buffer 514b.

[0139] like Figure 5 As shown, industry holding can be achieved by three switches. Alternatively or additionally, the holding switch can be achieved by three switches.

[0140] Therefore, sampling unit 510 includes a second plate switch 534a having a gate 536a configured to receive the second clock signal and a fourth plate switch 534b having a gate 536b configured to receive the second clock signal. Sampling unit 510 also includes a fifth switch 534c having a gate 536c configured to receive the second clock signal.

[0141] The fifth switch 534c may be implemented by a transistor operating as a switch, wherein a signal at a gate 536c of the fifth switch 534c controls whether a channel between a source and a drain is opened or closed for opening or closing the switch.

[0142] The fifth switch 534c is configured to receive a second clock signal at a gate 536c for controlling the fifth switch 534c between an active state and an inactive state. In the active state, the fifth switch 534c is closed. In the inactive state, the fifth switch 534c is open.

[0143] The fifth switch 534c may be implemented as a transistor of the same type as the second and fourth plate switches 534a, 534b. Thus, the fifth switch 534c may be implemented as a PMOS transistor, with the source of the fifth switch 534c connected to the fourth plate 524b of the second sampling capacitor 520b, and the drain of the fifth switch 534c connected to the second plate 524a of the first sampling capacitor 520a.

[0144] Furthermore, the sampling unit 510 includes a first plate switch 530a having a gate 532a configured to receive the first clock signal and a third plate switch 530b having a gate 532b configured to receive the first clock signal. The sampling unit 510 also includes a sixth switch 530c having a gate 532c configured to receive the first clock signal.

[0145] The sixth switch 530c may be implemented by a transistor operating as a switch, wherein a signal at a gate 532c of the sixth switch 530c controls whether a channel between a source and a drain is opened or closed for opening or closing the switch.

[0146] The sixth switch 530c is configured to receive a second clock signal at a gate 532c for controlling the sixth switch 530c between an active state and an inactive state. In the active state, the sixth switch 530c is closed. In the inactive state, the sixth switch 530c is open.

[0147] The sixth switch 530c may be implemented as a transistor of the same type as the first and third plate switches 530a, 530b. Thus, the sixth switch 530c may be implemented as an NMOS transistor, with the source of the sixth switch 530c connected to the third plate 522b of the second sampling capacitor 520b, and the source of the sixth switch 530c connected to the first plate 522a of the first sampling capacitor 520a.

[0148] Using three switches 530a, 530b, 530c forming a sampling switch and / or three switches 534a, 534b, 534c forming a holding switch may be used to reduce the differential resistance for the same clock signal load or to reduce the load for the same resistance.

[0149] Compared to the third embodiment, a fifth switch 534c and a sixth switch 530c are added in the fourth embodiment. Now, consider comparing the second and fourth plate switches 434a, 434b in the third embodiment with the second, fourth and fifth switches 534a, 534b, 534c in the third embodiment. A similar comparison can be made between the first and third plate switches 430a, 430b in the third embodiment and the first, third and sixth switches 530a, 530b, 530c in the fourth embodiment.

[0150] If each of the second and fourth plate switches 434a, 434b has a size S1 and a resistance R1, the total load S of each clock signal tot =2×S1, and the total differential resistance is 2×R1. Since the resistance is inversely proportional to the switch size, the resistance can be defined as R1=K / S1, where K is the proportionality constant. Therefore, for the third embodiment, the resistance R emb3 and the total load S tot Can be defined as:

[0151] R emb3 =2R1=2×K / S1 (1a)

[0152] S tot =2S1 (1b)

[0153] For the second, fourth and fifth switches 534a, 534b, 534c in the fourth embodiment, an additional parallel fifth switch 534c may be designed to reduce the differential resistance for the same clock signal load. It may be assumed that the size of the fifth switch 534c is a×S1, and the two second and fourth switches 534a, 534b may have equal sizes, each with a size of (1-a / 2)×S1. The resistance of the fifth switch 534c is then R a =K / (a×S1), and the resistance of the second and fourth plate switches 534a, 534b is then R b=K / ((1–a / 2)×S1).

[0154] Therefore, for the fourth embodiment, the resistor R emb3 and the total load S tot Can be defined as:

[0155] R emb4 =R a / / R b =[2 / (1+3a / 2)]×K / S1 (2a)

[0156] S tot =aS1+2(1-a / 2)S1=2S1 (2b)

[0157] It can be seen that the various equations are applicable to values ​​of a between 0 and 2. In addition, it can be seen from the above equations 1b and 2b that for all such values ​​of a, the total load of the clock signal is always the same. In addition, the differential resistance in the fourth embodiment is reduced relative to the differential resistance in the third embodiment, and as the value of a increases, the resistance gradually decreases.

[0158] The resistance in the fourth embodiment can be written as a function of the resistance in the third embodiment:

[0159]

[0160] For example, by selecting a=2 / 3, each of the second, fourth and fifth switches 534a, 534b, 534c has the same size, and the differential resistance is halved to R1. By selecting a=1, the resistance is further reduced to 0.4×R1.

[0161] Alternatively, the additional parallel fifth switch 534 c may be designed to reduce the load for the same resistance. Reducing the load means energy saving in the sampling unit 510 compared to the sampling unit 410 .

[0162] The resistance of the fifth switch 534c may be set to be equal to R a = R1 / q, and the resistance of the second and fourth plate switches 534a, 534b can be set equal to R b = R1 / (1–2q). This would mean that the total resistance in the fourth embodiment would be 2×R1, ie, equal to the total resistance in the third embodiment.

[0163] By setting the resistance of the fifth switch 534c in this manner, the size of the fifth switch 534c is S a =q×S1. In addition, the second and fourth plate switches 534a, 534b each have a size S b =(1-2q)×S1. The total size S of the switch in the fourth embodiment emb4 So it is defined as Semb4 =S a +2×S b =(2–3q)×S1. The size of the switch in the fourth embodiment can be written as the switch size S in the third embodiment: emb3 (see equation 1b above) is a function:

[0164]

[0165] It can be seen that the various formulas are applicable to q values ​​between 0 and 0.5. For example, choosing q=1 / 4 results in two parallel paths, each with a resistance of 4×R1, thus resulting in a total resistance of 2×R1, while the total size of the switch is only 62.5% of the total size of the corresponding switch in the third embodiment. This also means that the load is reduced accordingly, thereby reducing the power consumption of the sampling unit 510.

[0166] Reference now Figure 6 , a method for signal sampling and holding will be described. The method may include receiving an input signal at a signal sampling circuit and distributing the input signal to each sampling unit in a plurality of sampling units. The sampling units may be clocked to provide time-interleaved sampling of the input signal.

[0167] The method comprises the steps described below, wherein the steps are performed by each sampling unit of a plurality of sampling units to provide and hold a sample by the sampling unit.

[0168] Thus, the method comprises receiving 602 an input signal at an input buffer. The method further comprises controlling 604 the input buffer to be active and providing 606 a buffered input signal from the input buffer at a second plate of the sampling capacitor.

[0169] The method further includes providing 608 a sampled output signal at an output of a sampling unit connected to a first plate of the sampling capacitor by opening a first plate switch between the first plate of the sampling capacitor and a first reference voltage. This may involve controlling the first plate switch based on a first clock signal at a gate of the first plate switch, wherein the first clock signal controls the first plate switch between an active state and an inactive state. The first clock signal may control the first plate switch to assume an inactive state to open the first plate switch.

[0170] The method further includes holding 610 the sampled output signal at the output terminal by closing a second plate switch between a second plate of the sampling capacitor and a second reference voltage. This may involve controlling the second plate switch based on a second clock signal at a gate of the second plate switch, wherein the second clock signal controls the second plate switch between an active state and an inactive state. The second clock signal may control the first plate switch to assume an inactive state to close the second plate switch.

[0171] The first clock signal may change from the tracking state to the holding state slightly earlier than the second clock signal. The first plate switch receiving the first clock signal opens to provide a sampled output signal at the output terminal. Thereafter, the input buffer may be disconnected from the second plate of the sampling capacitor and the second plate switch may be closed to hold the sampled value.

[0172] The method includes powering off the input buffer by controlling at least one power gating switch 612. Powering off the input buffer can ensure that the input buffer is disconnected from the second plate of the sampling capacitor without requiring a switch between the output of the input buffer and the second plate of the sampling capacitor. The at least one power gating switch can also be controlled to ensure that the input buffer is active when sampling of the value of the input signal is to be performed.

[0173] The sampled output signal is held at the output of the sampling unit to allow it to be provided for analog-to-digital conversion.

[0174] Powering off the input buffer can be achieved by controlling at least one power-gated switch to assume an inactive state. This can be achieved by controlling only a single power-gated switch using the second clock signal. Alternatively, the second clock signal and an additional third clock signal that is the inverse of the second clock signal are used to control two power-gated switches.

[0175] In the above, the inventive concept has mainly been described with reference to a limited number of examples. However, as readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept as defined by the appended claims.

Claims

1. A signal sampling circuit, comprising: A plurality of sampling units configured to receive an input signal for time-interleaved sampling, wherein each sampling unit of the plurality of sampling units comprises: a second sampling capacitor having a first plate and a second plate, wherein the first plate is connected to an output of the sampling unit; a first plate switch disposed between the first plate of the sampling capacitor and a first reference voltage, wherein the first plate switch is configured to receive a first clock signal at a gate of the first plate switch for controlling the first plate switch between an active state and an inactive state; a second plate switch disposed between the second plate of the sampling capacitor and a second reference voltage, wherein the second plate switch is configured to receive a second clock signal at a gate of the second plate switch for controlling the second plate switch between an active state and an inactive state; an input buffer configured to receive the input signal and configured to output a buffered input signal at an output node, wherein the output node of the input buffer is connected to the second plate of the sampling capacitor; Wherein the input buffer is connected to at least one power gate switch for powering off the input buffer.

2. The signal sampling circuit of claim 1 , wherein the at least one power-gated switch comprises an interrupt switch arranged between a connection to a low voltage level of the input buffer and a connection to a high voltage level of the input buffer, wherein the interrupt switch is configured to receive the second clock signal at a gate of the interrupt switch for controlling the interrupt switch between an active state and an inactive state.

3. The signal sampling circuit of claim 2, wherein the interrupt switch is a first interrupt switch arranged between the input buffer and ground, and wherein the at least one power-gating switch further comprises a second interrupt switch arranged between the input buffer and the high voltage level, wherein the second interrupt switch is configured to receive a third clock signal at a gate of the second interrupt switch for controlling the second interrupt switch between an active state and an inactive state, wherein the third clock signal is an inverse of the second clock signal.

4. The signal sampling circuit of claim 1 , wherein the input buffer comprises a bias transistor for providing a bias signal of the input buffer, wherein the at least one power gate switch comprises a bias switch connected to a gate of the bias transistor, wherein the bias switch is configured to selectively connect a control voltage of the bias transistor to a bias voltage or a fixed reference voltage corresponding to an active state and an inactive state of the input buffer, respectively.

5. The signal sampling circuit of claim 1 , wherein the input signal is a differential input signal including a positive input signal and a negative input signal, and wherein, For each sampling unit, the sampling capacitor is a first sampling capacitor, the first plate switch is connected to a first output terminal of the sampling unit, and the input buffer is a first input buffer, wherein the first input buffer is configured to receive the positive input signal and is configured to output a buffered positive input signal at a second plate of the first sampling capacitor, and wherein each sampling unit further comprises: a second sampling capacitor having a third plate and a fourth plate, wherein the third plate is connected to a second output terminal of the sampling unit; a third plate switch disposed between the third plate of the second sampling capacitor and the first reference voltage, wherein the third plate switch is configured to receive the first clock signal at a gate of the third plate switch for controlling the third plate switch between an active state and an inactive state; a fourth plate switch disposed between the fourth plate of the second sampling capacitor and the second reference voltage, wherein the fourth plate switch is configured to receive the second clock signal at a gate of the fourth plate switch for controlling the fourth plate switch between an active state and an inactive state; a second input buffer configured to receive the negative input signal and configured to output a buffered negative input signal at a second output node, wherein the second output node of the second input buffer is connected to the fourth plate of the second sampling capacitor; Wherein the first input buffer is connected to the second input buffer via the at least one power gate switch, the at least one power gate switch includes a shared switch for powering off the first input buffer and the second input buffer.

6. The signal sampling circuit of claim 5, wherein a ground connection of the first input buffer is connected to a ground connection of the second input buffer, and wherein the shared switch is arranged between ground and the first input buffer and the second input buffer.

7. The signal sampling circuit of claim 5 , wherein each sampling unit further comprises a fifth switch, the fifth switch being arranged between the second plate of the first sampling capacitor and the fourth plate of the second sampling capacitor, wherein the fifth switch is configured to receive the second clock signal at a gate of the fifth switch for controlling the fifth switch between an active state and an inactive state.

8. The signal sampling circuit of claim 5 , wherein each sampling unit further comprises a sixth switch disposed between the first plate of the first sampling capacitor and the third plate of the second sampling capacitor, wherein the sixth switch is configured to receive the first clock signal at a gate of the sixth switch for controlling the sixth switch between an active state and an inactive state.

9. The signal sampling circuit of claim 7, wherein the second plate switch and the fourth plate switch have equal sizes related to a size of the fifth switch.

10. The signal sampling circuit of claim 8, wherein the first plate switch and the third plate switch have equal sizes related to a size of the sixth switch.

11. The signal sampling circuit of claim 1, wherein different sampling units are configured to receive different clock signals that are phase-shifted relative to each other. 12 . The signal sampling circuit of claim 1 , wherein the signal sampling circuit further comprises a distribution network for distributing the input signal to each sampling unit.

13. The signal sampling circuit as claimed in claim 1, wherein the first reference voltage is a low voltage.

14. A method for sampling and holding a signal using a plurality of sampling units for time-interleaved sampling, the method comprising, by each sampling unit of the plurality of sampling units: receiving an input signal at an input buffer; Controlling the input buffer to be active; providing a buffered input signal from the input buffer at a second plate of a sampling capacitor; providing a sampled output signal at an output of the sampling unit connected to the first plate of the sampling capacitor by opening a first plate switch between the first plate of the sampling capacitor and a first reference voltage; thereafter holding the sampled output signal at the output terminal by closing a second plate switch between the second plate of the sampling capacitor and a second reference voltage; as well as The input buffer is powered down by controlling at least one power gating switch.

15. The method of claim 14, wherein the method further comprises receiving, by each of the plurality of sampling units, a first clock signal and a second clock signal for controlling the first and second board switches, wherein different sampling units receive different clock signals phase-shifted relative to each other.

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