A differential delay chain and decoding method thereof

Abstract

The present invention discloses a differential delay chain and a decoding method thereof, which relates to the technical field of high-precision time measurement. The differential delay chain includes two measurement chains, which are used to receive the same measurement signal with a time difference and output the corresponding sampling results. The measurement chain includes: a plurality of cascaded delay units, which are used to receive the measurement signal and perform delay processing on the portion between the measurement signal and the sampling clock edge of the current clock cycle; a plurality of triggers, whose input ends are respectively connected to the output ends of the plurality of delay units, which are used to sample the outputs of the plurality of delay units to obtain the sampling results of the entire chain; a sampling unit, which is connected to the output ends of the plurality of triggers, which is used to output the sampling results of the entire chain; the time difference is half of the delay length of a single delay unit. The present invention can improve the resolution to half of the delay of a commonly used delay unit by a differential method, and at the same time, the decoding pressure is reduced due to the reduction in the number of delay units, thereby improving the decoding efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of high-precision time measurement, and in particular to a differential delay chain and a decoding method thereof. Background Art

[0002] High-precision time interval measurement is widely used in the back-end readout of nuclear resonance scattering experiments in high-energy physics, and its performance directly affects the result analysis and energy spectrum drawing of nuclear resonance scattering experiments. In addition, by accurately measuring the flight time of photons using the time of flight (ToF) method, accurate position information can be calculated. Therefore, in addition to the field of high-energy physics, high-precision time measurement solutions are also widely used in fluorescence imaging, space exploration, astronomical observation, positron emission tomography, laser ranging, autonomous driving, aerospace, radar positioning, three-dimensional imaging, and fluid flow measurement.

[0003] High-precision time interval measurement is mainly achieved through two platforms: FPGA and Application Specific Integrated Circuit (ASIC). The main implementation schemes include direct counting method, clock phase method and interpolation delay chain method. The ASIC platform has higher flexibility than the FPGA platform, and its time interval resolution capability has reached the level of less than 100 picoseconds. In recent years, from the increased demand for high-energy physics experiments to the rapid development of autonomous driving technology, high-precision and high-resolution time measurement has become particularly important. In the ToF method, the higher the time resolution, the more accurate the location information can be located. Therefore, time interval measurement urgently needs to achieve higher time resolution capabilities.

[0004] The resolution of time interval measurement based on the interpolation delay chain method is mainly determined by the delay time and process of the delay unit. The existing interpolation delay chain method adopts enough delay units to form a delay chain to improve the resolution during design, but the cost is to sacrifice area and increase cost. Too many delay units will also lead to high decoding pressure and low efficiency. Summary of the invention

[0005] Based on the above technical problems, the present invention provides a differential delay chain, which solves the problems of large area, high cost and low efficiency in the high-resolution design of the existing ASIC platform.

[0006] In a first aspect, the present invention provides a differential delay chain, comprising:

[0007] Two measurement chains for receiving the same measurement signal with a time difference and outputting corresponding sampling results;

[0008] The measurement chain comprises:

[0009] A plurality of cascaded delay units are used to receive a measurement signal and perform delay processing on the time between the measurement signal and a sampling clock edge of a current clock cycle;

[0010] A plurality of triggers, whose input ends are respectively connected to the output ends of the plurality of delay units, are used to sample the outputs of the plurality of delay units to obtain a whole chain sampling result;

[0011] A sampling unit, connected to the output terminals of the plurality of triggers, for outputting the sampling results of the entire chain;

[0012] The time difference is half of the delay time of a single delay unit.

[0013] Preferably, the delay unit is an inverter, and its output end is in phase opposition with its input end.

[0014] Preferably, the number of the plurality of delay units is obtained by the clock cycle and the delay time length of the inverter, as shown below:

[0015] N=T clk / T d ;

[0016] Where N is the number of inverters, T clk is the clock period, T d is the delay length of a single inverter.

[0017] Preferably, the trigger is a D trigger, and the data range of the whole chain sampling result is [0 to (N-1)].

[0018] Preferably, all triggers use the same working clock.

[0019] In a second aspect, the present invention further provides a decoding method for decoding a differential delay chain, comprising:

[0020] The two whole-chain sampling results of the two delay chains are back-labeled to a merged chain to obtain a merged result;

[0021] Obtaining a transition point in the merged result, where the transition point is the boundary between 0 and 1;

[0022] The level at which the transition point on the merge chain is located is taken as the decoding result.

[0023] Compared with the prior art, at least one of the above technical solutions adopted by the present invention can achieve the following beneficial effects:

[0024] The present invention proposes a differential delay chain, which uses two identical measurement chains to receive the same measurement signal with a time difference. Compared with the existing method that requires a sufficient number of delay units to form a delay chain, the number of delay units in each delay chain of the present invention only needs half the number of delay units in the existing method, which greatly reduces the area and cost.

[0025] In terms of decoding method, the present invention reduces the number of delay units to half of the existing method through a differential method, and at the same time, back-labels the two whole chain sampling results with time difference of the two delay chains to a merged chain to obtain a merged result, obtain the jump point in the merged result, and use the level of the jump point on the merged chain as the decoding result, which not only reduces the decoding difficulty, but also increases the resolution to half of the delay of a single-stage delay unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 This is the principle diagram of the interpolation delay chain method;

[0028] Figure 2 It is a schematic diagram of the basic structure of the measurement chain of the present invention;

[0029] Figure 3 It is the physical implementation layout of the basic structure of the differential delay chain of the present invention;

[0030] Figure 4 This is a sampling result diagram of structure 1 of the present invention;

[0031] Figure 5 It is a structural schematic diagram of the differential delay chain of the present invention;

[0032] Figure 6 It is a schematic diagram of the differential chain back-labeling of the present invention. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] The interpolation delay chain method expresses the time interval ΔT between the start signal and the stop signal to be measured in the form of "coarse count" + "fine count". Coarse count means that time is measured in clock cycles. When the time interval is less than one cycle, coarse count cannot be quantified, and the measurement result of the time interval less than one clock cycle will be expressed by fine count. By combining coarse and fine quantization, high-precision time measurement can be achieved.

[0035] Interpolation delay chain method Figure 1 As shown, the interpolation delay chain divides a clock cycle into N delay units for interpolation, wherein the first fine counting result t1 is the interval between the start signal and the sampling clock edge, the second fine counting result t2 is the interval between the stop signal and the sampling clock edge, and the coarse counting result is T. T d is the delay of the first-stage interpolation delay unit, T clk is the clock cycle, N clk The first fine counting result t1 and the second fine counting result t2 are represented by the number of interpolated delay units in the corresponding interval. For the first fine counting result t1, N1 is the number of interpolated delay units of t1. d For the second detailed counting result t2, N2 is the interpolated T of t2. d ΔT is the time interval of the signal to be measured. The time interval calculation formula is shown in formula (1).

[0036] ΔT=t1+T-t2=(N1-N2)×T d +N clk ×T clk (1).

[0037] The trigger samples the output of each level of the delay chain and then decodes the sampling results to find the transition level. The total delay duration accumulated to this level is the fine quantization result, which is t1 and t2.

[0038] Based on the above content, the present invention provides a differential delay chain, including two measurement chains, which are used to receive the same measurement signal with a time difference and output corresponding sampling results. The time difference is half of the delay length of a single delay unit.

[0039] The basic structure of the measurement chain is as follows: Figure 2 As shown, the physical implementation layout is as follows Figure 3As shown, it includes multiple cascaded delay units, multiple triggers and processing units. Multiple cascaded delay units constitute a delay chain, which is used to receive a measurement signal and delay the time between the measurement signal and the sampling clock edge of the current clock cycle. Multiple trigger input ends are respectively connected to the output ends of multiple delay units, which are used to sample the outputs of multiple delay units to obtain the whole chain sampling result SumD, where Sum is the summation symbol and D represents a D flip-flop (Data flip-flop). The sampling unit is connected to the output ends of multiple triggers to output the whole chain sampling result.

[0040] The delay chain is formed by cascading inverters as delay units, and the output of each delay unit is sampled by a trigger. The function of the inverter is to flip the input signal and then output it. The input signal will be output after the propagation delay inherent in the device. Therefore, the inverter can be regarded as a delay unit. When an even number of inverters are cascaded, the logic level of the output signal and the input signal will not change, and there will only be a time-accumulated delay. The present invention inserts a certain number of inverters in a certain clock cycle, and the number of inverters is calculated as shown in formula (2).

[0041] N=T clk / T d (2);

[0042] Where N represents the number of inverters, T clk represents the clock cycle, and t represents the delay time of a single-stage inverter.

[0043] In the application process, affected by environmental changes, the delay of the inverter will change within a certain range, so the number of inverters finally used in the present invention retains a margin of about 30% on the number calculated by formula (2) to form the final delay chain. The output of each delay unit of the delay chain is sampled by a D trigger. The delay chain and the trigger finally form a complete measurement chain.

[0044] The differential delay chain of the present invention is composed of at least 4 measurement chains. Each measurement chain is composed of a delay chain and a corresponding trigger. When each differential interpolation delay chain is used independently, it can be used to measure the time interval between 2 start signals and 2 stop signals, that is, to measure 2 different groups of signals. The single measurement chain structures are combined into a group in pairs to form a differential structure, which corresponds to the time interval measurement of 1 start signal and 1 stop signal, that is, to measure 1 group of signals.

[0045] Based on the above differential delay chain, the present invention further proposes a decoding method, including two decoding structures corresponding to different precisions and resolutions.

[0046] Structure 1: This structure corresponds to the basic measurement chain structure. Four measurement chains can measure two groups of signals (two start signals and two stop signals). The function of the inverter is to flip the input signal and then output it. Therefore, when the input signal propagates in the inverter chain, the output signal ZN of each inverter will be flipped, and the sampling result will flip between "0" and "1". The sampling results of each level of trigger are output. At the edge of the sampling clock, if the sampling results of two adjacent levels are consistent, it means that the jump level occurs at the lower level of the two adjacent levels. The accumulated time when the signal propagates to the inverter of this level is equal to the time difference between the signal and the clock edge. When the sampling results of two adjacent levels are different, it means that the jump has not occurred, and the accumulated time is not equal to the time difference. See Figure 4 , there are N levels of inverters, from 0 to N-1. The sampling point is based on the rising edge of the sampling clock of the trigger. For example, at the sampling point shown in the figure, the sampling result is "0101...0110...010", where "...11..." is the jump point, which occurs at the N-1 and N level inverters, and the final delay propagation end point can be locked at the N-1 level inverter. Similarly, the sampling result based on different sampling points can also be "0101...1001...010", where "...00..." is regarded as the jump point. For this structure, the XOR method is used to decode the output result of the trigger to obtain a "fine count" result in the range of [0~(N-1)], corresponding to high-resolution time interval measurement.

[0047] Structure 2: Structure 2 adjusts the chain to a differential structure. Under this structure, only one set of signals (one Start signal and one Stop signal) can be responded to. The specific differential structure is to input the same signal into two measurement chains respectively, that is, the two start delay chains share one start signal input, and the two stop delay chains share one stop signal input. Originally, one delay chain received an independent signal. Then, in the back-end design, the layout and routing rules are constrained so that the time difference Δt when the signal reaches the input of the two delay chains remains at 1 / 2 the delay time of the single-stage delay unit, that is like Figure 5 As shown in the figure, the difference between chain A and chain B is Δt. At this time, through the structure of the differential chain, the fine counting results of the two delay chains will also differ in time by Δt. In summary, when the two chains are reversed into one chain, the series range is expanded to [0~(2N-1)], and the total series is increased to 2N, which can increase the minimum distinguishable time to Δt. Figure 6 After back-labeling to one chain, the resolution of the differential chain structure will be doubled compared to structure one, achieving ultra-high resolution measurement.

[0048] The present invention is not limited to a specific process and working clock cycle. Under the 130 nanometer process, time interval measurement of more than ten picoseconds can be achieved.

[0049] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0050] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A differential delay chain, characterized in that: include: Two measurement chains for receiving the same measurement signal with a time difference and outputting corresponding sampling results; The measurement chain comprises: A plurality of cascaded delay units are used to receive a measurement signal and perform delay processing on the time between the measurement signal and a sampling clock edge of a current clock cycle; A plurality of triggers, whose input ends are respectively connected to the output ends of the plurality of delay units, are used to sample the outputs of the plurality of delay units to obtain a whole chain sampling result; A sampling unit, connected to the output terminals of the plurality of triggers, for outputting the sampling results of the entire chain; The time difference is half of the delay time of a single delay unit.

2. A differential delay chain as claimed in claim 1, characterized in that: The delay unit is an inverter, and its output end is in phase opposition with its input end.

3. A differential delay chain as claimed in claim 2, characterized in that: The number of multiple delay units is obtained by the clock cycle and the delay time of the inverter, as shown below: N=T clk / T d ; Where N is the number of inverters, T clk is the clock period, T d is the delay length of a single inverter.

4. A differential delay chain as claimed in claim 3, characterized in that: The trigger is a D trigger, and the data range of the whole chain sampling result is [0 to (N-1)].

5. A differential delay chain as claimed in claim 1, characterized in that: All flip-flops use the same operating clock.

6. A decoding method for decoding the differential delay chain according to any one of claims 1 to 5, characterized in that: include: Back-label the two whole-chain sampling results of the two measurement chains to a combined chain to obtain a combined result; Obtaining a transition point in the merged result, where the transition point is the boundary between 0 and 1; The level at which the transition point on the merge chain is located is taken as the decoding result.

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