Analog to digital converter (ADC) of heterogeneous channel architecture based on neural network enhancement

Abstract

The invention discloses an ADC of a heterogeneous channel architecture based on neural network enhancement, and relates to the technical field of ADC design, the ADC comprises two heterogeneous ADC channels, a delay module, a neural network circuit and a streaming training controller; the two paths of heterogeneous ADC channels are respectively a high-speed low-precision channel and a low-speed high-precision channel, and the two channels are connected to the same signal source; a time delay module carries out time delay and alignment processing on output data of the two channels, and multi-time-dimension data formed by the high-speed channel after time delay is aligned with single-time-dimension data of the low-speed channel; the neural network circuit takes the high-speed channel data as training data and takes the low-speed channel data as label data, and high-speed and high-precision quantitative output is generated through training; the streaming training controller globally manages data acquisition and batch processing operation, and training data is generated through down-sampling, time migration and batch processing; according to the invention, combination of high speed and high precision can be realized, and complex signal processing requirements are met.

Description

Technical Field

[0001] The present invention relates to the technical field of ADC design, and in particular to an ADC based on a heterogeneous channel architecture enhanced by a neural network. Background Art

[0002] Analog-to-Digital Converter (ADC) is a core component in modern electronic devices that converts analog signals into digital signals. It is widely used in communications, medical treatment, industrial control, consumer electronics and other fields. In order to meet the needs of different application scenarios, ADC usually needs to take into account both high sampling speed and high quantization accuracy.

[0003] High-speed, low-precision ADC: It captures signals quickly at a higher sampling frequency, but due to hardware design limitations, its quantization accuracy is low and it is easy to introduce errors.

[0004] Low-speed, high-precision ADC: It can provide accurate signal quantization, but the sampling frequency is low and it is difficult to meet the needs of real-time processing of dynamic signals.

[0005] Although high-speed low-precision and low-speed high-precision ADCs each have their own advantages, it is difficult to achieve an effective combination of the two with existing technologies. In applications that require both fast response and high-precision quantization, such as real-time data analysis and dynamic signal detection, a single type of ADC is often difficult to meet the needs at the same time. Some systems attempt to combine high-speed low-precision ADCs with low-speed high-precision ADCs, but due to the essential difference in sampling frequency between the two, their data output is difficult to synchronize on the time axis, and there is a lack of efficient data fusion methods, resulting in the overall system performance not being significantly improved. Summary of the invention

[0006] The purpose of the present invention is to construct a heterogeneous channel architecture based on neural network enhancement, integrating the advantages of high-speed low-precision channels and low-speed high-precision channels, and realizing an ADC system with both high-speed sampling and high-precision quantized output to meet the needs of complex signal processing.

[0007] The technical solution of the present invention is: to provide an ADC based on a heterogeneous channel architecture enhanced by a neural network, the ADC comprising: two heterogeneous ADC channels, a delay module, a neural network circuit, and a streaming training controller;

[0008] The two heterogeneous ADC channels are a high-speed low-precision channel and a low-speed high-precision channel. The two channels are ADCs with different performances and are connected to the same signal source. The high-speed low-precision channel has a higher sampling frequency than the low-speed high-precision channel and is used to quickly capture changes in high-frequency signals. The low-speed high-precision channel is used to provide high-precision quantized data as a benchmark.

[0009] The delay module is connected to the output of the two heterogeneous ADC channels to perform delay and alignment processing on the two output data. The multi-time dimension data of the high-speed and low-precision channel is aligned with the single time dimension data of the low-speed and high-precision channel after delay processing.

[0010] The neural network circuit consists of an input layer, a hidden layer, and an output layer. The number of neurons in the input layer is consistent with the characteristic dimension of the input data, the number of neurons in the hidden layer is adjustable, the number of neurons in the output layer is 1, and all nodes in the front and back layers are interconnected. The neural network circuit integrates the advantages of high-speed low-precision channels and low-speed high-precision channels through training, uses the output of the high-speed low-precision channel as training data, and the output of the low-speed high-precision channel as label data. The weights and biases are adjusted during the training process to generate high-speed and high-precision quantized outputs.

[0011] The streaming training controller is used to globally control the data acquisition of two heterogeneous ADC channels, the alignment operation of the delay module, and the training data generation of the neural network circuit. It generates diversified training data through downsampling, time offset and batch processing operations.

[0012] In any of the above technical solutions, further, the delay module is connected to the outputs of the high-speed low-precision channel and the low-speed high-precision channel respectively, and the delay module delays the high-speed data according to the frequency of the sampling clock of the low-speed high-precision channel to ensure that the high-speed data is aligned with the low-speed data; the delay module temporarily stores the multi-time dimension data output by the high-speed low-precision channel through a register, aligns it with the single time dimension data of the low-speed high-precision channel after delay, and outputs synchronous data for use by the neural network circuit.

[0013] In any of the above technical solutions, further, the flow training controller workflow is as follows:

[0014] S1, parameter setting: set the sampling clock frequency fa of the high-speed low-precision channel ADC and the sampling clock frequency fb of the low-speed high-precision channel ADC, and set the interval acquisition number N that determines the amount of high-speed low-precision data collected each time, and the offset constant M that controls the time offset number of the low-speed channel;

[0015] S2, downsampling operation: after the sampling clocks of the two channel ADCs are aligned for the first time, the sampling clock of the low-speed channel ADC is used as the reference, and the output data of multiple time dimensions of N high-speed and low-precision channel ADCs are collected each time as training data, and the output data of one time dimension of the low-speed and high-precision channel ADC is collected at the same time as the label data;

[0016] S3, offset operation: After each downsampling operation is completed, the streaming training controller performs a time offset on the sampling clock of the low-speed and high-precision channel. The offset is the high-speed and low-precision channel clock cycle 1 / fa. The low-speed and high-precision channel data after the time offset will be downsampled with the new high-speed and low-precision data.

[0017] S4, batch operation: M offset operations are used as a batch cycle, each batch contains N*(M+1) label data and corresponding training data, which are input into the neural network circuit for training.

[0018] In any of the above technical solutions, further, the neural network circuit adapts to the quantization requirements of different signal characteristics by adjusting the number of neurons in the input layer and the hidden layer, thereby improving the generalization performance and reasoning accuracy of the model.

[0019] In any of the above technical solutions, further, a verification system for an ADC based on a heterogeneous channel architecture enhanced by a neural network is built. The verification system uses a signal fitting method to obtain high-precision quantization results as label data for the neural network circuit to replace the output of the low-speed and high-precision channel.

[0020] The beneficial effects of the present invention are:

[0021] The technical solution in the present invention achieves a balance between high speed and high precision through a combination of software and hardware. Through the joint use of two heterogeneous ADC channels (a high-speed low-precision channel and a low-speed high-precision channel), the high-speed channel captures dynamic signal characteristics and the low-speed channel provides accurate reference data, giving full play to the advantages of both. The delay module is used to synchronize the outputs of the heterogeneous channels, overcoming the data alignment problem caused by sampling frequency differences in traditional methods.

[0022] The neural network circuit uses the multi-time dimension data provided by the high-speed channel as input and the high-precision data provided by the low-speed channel as labels. Through training, it achieves fast and high-precision signal quantization output, which greatly improves the intelligence level of the system and significantly improves performance without increasing hardware complexity.

[0023] In a preferred implementation of the present invention, dynamic generation of training data is achieved through a streaming training controller, and a combined strategy of downsampling, time offset and batch processing is adopted to effectively overcome the problem of sparsity of low-speed and high-precision channel data, generate rich training data, and ensure the training effect of the model. This strategy also generates diversified label data through time offset operations, which significantly improves the generalization ability of the neural network model.

[0024] The present invention does not need to rely on expensive hardware optimization, but achieves high-speed and high-precision collaborative work through delay modules and AI algorithms, greatly reducing the complexity and cost of hardware design.

[0025] The present invention provides a new ADC architecture and realizes chip-level verification of the ADC of the architecture. In addition to calibrating the error of the high-speed and low-precision channel in the ADC, the architecture can also make the expression limit of the channel ADC exceed the expression limit of the target to be calibrated itself, and provide a new quantization bit number, which has pioneering value. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The advantages of the above and additional aspects of the present invention will become apparent and easily understood in the description of the embodiments in conjunction with the following drawings, in which:

[0027] Figure 1 is a schematic diagram of a principle of an ADC based on a heterogeneous channel architecture enhanced by a neural network according to an embodiment of the present invention;

[0028] Figure 2 is a working diagram of a streaming training controller of an ADC based on a heterogeneous channel architecture enhanced by a neural network according to an embodiment of the present invention;

[0029] Figure 3 is a schematic diagram of a verification system principle of an ADC based on a heterogeneous channel architecture enhanced by a neural network according to an embodiment of the present invention;

[0030] Figure 4 is a pipeline ADC output spectrum diagram of an ADC based on a heterogeneous channel architecture enhanced by a neural network according to an embodiment of the present invention;

[0031] Figure 5 is a fitted output spectrum diagram of an ADC based on a heterogeneous channel architecture enhanced by a neural network according to an embodiment of the present invention;

[0032] Figure 6 is a schematic diagram of a neural network quantization output of an ADC based on a heterogeneous channel architecture enhanced by a neural network according to an embodiment of the present invention;

[0033] Figure 7 It is a schematic diagram of a signal acquisition system of an ADC based on a heterogeneous channel architecture enhanced by a neural network according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0035] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0036] like Figure 1 As shown, this embodiment provides an ADC based on a heterogeneous channel architecture enhanced by a neural network, and the ADC includes: two heterogeneous ADC channels, a delay module, a neural network circuit, and a streaming training controller.

[0037] The two heterogeneous ADC channels are composed of two ADCs with different performances, one is a high-speed and low-precision ADC, and the other is a low-speed and high-precision ADC, which are connected to the same signal source. The two-channel ADCs of the heterogeneous channel architecture have different output characteristics. The high-speed and low-precision channel is responsible for quickly capturing changes in high-frequency signals, and the low-speed and high-precision channel is responsible for providing high-precision quantized data as a benchmark.

[0038] The high-speed, low-precision channel can make up for the delay problem of the low-speed, high-precision channel under rapidly changing signals, and the low-speed, high-precision channel can make up for the error caused by insufficient precision of the high-speed, low-precision channel. When faced with different signal requirements, the two channels of data can be flexibly combined to improve overall performance; the data of the two channels provide richer and more complete information for subsequent AI neural networks: the high-speed, low-precision channel provides multi-time dimension data, which can provide training data for subsequent neural network circuit training; the low-speed, high-precision channel provides accurate reference data to provide label data for neural network training.

[0039] Due to the different sampling speeds of the two heterogeneous ADC channels, the data acquisition frequency of the high-speed, low-precision channel is higher, the amount of data generated is large and the interval time is short, while the data acquisition frequency of the low-speed, high-precision channel is lower, the amount of data is small and the interval time is long. The outputs of the two do not match in the time dimension and cannot be directly used for the training and reasoning of neural network circuits. They need to be aligned and processed through subsequent delay modules to ensure the timing consistency of the data.

[0040] The delay module is a key part of the whole system for processing the data output by two heterogeneous ADC channels. The delay module is connected to the output of the high-speed low-precision channel and the low-speed high-precision channel respectively. The delay module calculates the appropriate delay time according to the sampling clock of the low-speed high-precision channel, and delays the high-speed data to ensure that they are aligned with the low-speed data; using registers ( Figure 1 The "+" module in the middle temporarily stores the multi-time dimension data output by the high-speed and low-precision channel, aligns it with the output frequency of the low-speed and high-precision channel, and outputs it to the neural network circuit synchronously.

[0041] The neural network circuit integrates the advantages of two heterogeneous ADC channels by learning the data characteristics of the two channels, and ultimately achieves high-speed and high-precision signal quantization output.

[0042] The neural network circuit consists of an input layer, a hidden layer, and an output layer. The number of neurons in the input layer is consistent with the characteristic dimension of the input data, the number of neurons in the hidden layer is adjustable, the number of neurons in the output layer is 1, and all nodes in the front and back layers are interconnected. By adjusting the number of neurons in the input layer and the hidden layer, it is possible to adapt to the quantization requirements of different signal characteristics and improve the generalization performance and reasoning accuracy of the model.

[0043] The neural network circuit uses the output of the high-speed, low-precision channel as training data and the output of the low-speed, high-precision channel as label data. The neural network circuit adjusts its own weights and biases to minimize the error between the output layer neuron output and the label data, providing users with nearly high-precision and high-speed quantized data.

[0044] The streaming training controller controls the global operation of the ADC based on the heterogeneous channel architecture enhanced by the neural network, such as Figure 2 As shown, the flow training controller workflow is as follows:

[0045] S1. Parameter setting: Set the sampling clock frequency fa of the high-speed low-precision channel ADC and the sampling clock frequency fb of the low-speed high-precision channel ADC, and set the interval acquisition times N that determine the amount of high-speed low-precision data collected each time, and the offset constant M that controls the time offset times of the low-speed channel.

[0046] S2, downsampling operation: After the sampling clocks of the two channel ADCs are aligned for the first time, the sampling clock of the low-speed channel ADC is used as the benchmark, and the output data of multiple time dimensions of N high-speed and low-precision channel ADCs are collected each time as training data, and the output data of one time dimension of the low-speed and high-precision channel ADC is collected at the same time as the label data.

[0047] S3, offset operation: After each downsampling operation is completed, the streaming training controller will perform a time offset on the sampling clock of the low-speed and high-precision channel. The offset is the high-speed and low-precision channel clock period 1 / fa. The low-speed and high-precision channel data after the time offset will be downsampled with the new high-speed and low-precision data.

[0048] S4, batch operation: M offset operations are used as a batch cycle, each batch contains N*(M+1) label data and corresponding training data, which are input into the neural network circuit for training.

[0049] Since the data of the high-speed channel is dense but the data of the low-speed channel is sparse, through the above-mentioned offset operation, the low-speed high-precision channel and the high-speed low-precision channel form a new alignment on the time axis, generating more diverse label data and making up for the scarcity of low-speed high-precision channel data.

[0050] The present invention adopts the above-mentioned new ADC architecture, which can not only calibrate the error of the high-speed low-precision channel in the ADC, but also make the expression limit of the channel ADC exceed the expression limit of the target to be calibrated, and provide a new quantization bit number, which has pioneering value. For example, the high-speed low-precision channel in the ADC of the heterogeneous channel architecture of the present invention is a 14-bit ADC. The present invention has obtained an effective expression accuracy of more than 14.3 bits through the following verification system.

[0051] like Figure 3 and Figure 7 As shown in the figure, a verification system for the ADC based on the heterogeneous channel architecture enhanced by the neural network is built:

[0052] In order to verify the proposed heterogeneous channel architecture ADC enhanced by neural network, data acquisition and reconstruction are first required to build high-speed and low-precision and low-speed and high-precision heterogeneous channel architectures, and then the neural network is trained to obtain high-speed and high-precision quantized output.

[0053] Data acquisition uses a 14-bit, 1Gsps commercial pipeline ADC chip as a high-speed, low-precision channel to build a signal acquisition system to obtain a high-speed, low-precision quantization channel. The system includes a signal generator, a clock board, a chip test board, an FPGA development board, and a computer. Among them, the signal generator provides analog signals for the ADC, the clock board provides the working clock for the ADC, the chip test board provides a carrier and interface for the ADC, and completes the signal protocol conversion on the FPGA development board, transmits the signal to the computer's host software, and finally saves it as data set D1.

[0054] Data reconstruction uses the signal fitting method to obtain high-precision quantization results, and constructs a low-speed and high-precision quantization channel and a neural network training data set through the offset downsampling method. First, the sine fitting tool in the MATLAB fitting toolbox is used to fit the signal output by the signal acquisition system to obtain high-precision quantization results and save them as data set D2. Subsequently, the offset downsampling method is used to construct a low-speed and high-precision quantization channel and a neural network training data set. The specific process is as follows:

[0055] Parameter setting: set the downsampling factor P, the number of interval acquisitions N, the offset constant M and the number of feature dimensions T.

[0056] Split the dataset: After aligning the datasets D1 and D2 by time, split them into the training set Dtrain1 and the test set Dtest1 in a ratio of 8:2.

[0057] Reconstruct the training data set: Based on the training set data, downsample according to the sampling factor, that is, the frequency after downsampling is reduced to 1 / P of the original frequency. Based on the training set data, downsample according to the sampling factor, so that the frequency after downsampling is reduced to 1 / P of the original frequency. Each time, collect T time dimensions of data from the D1 channel as input data for neural network training, and collect one time dimension of data from the D2 channel as label data for neural network training. After collecting N times, offset a time period and downsample again to obtain a low-speed and high-precision quantization channel. Divide the offset downsampled data into batches of batch = N*(M+1), and finally obtain the neural network reconstruction training data set Dtrain2.

[0058] The neural network is trained in batch mode to output high-speed and high-precision quantization results. A three-layer BP neural network is constructed based on the MATLAB platform, in which the number of neurons in the input layer is consistent with the input data dimension T of the training data set, the number of neurons in the hidden layer is adjustable, and the number of neurons in the output layer is 1. The neural network is trained using the reconstructed training data set Dtrain2, and then tested using the unreconstructed test set Dtest1.

[0059] In the verification experiment, the pipeline ADC operating frequency is set to 1GHz, and the signal generator is adjusted to generate a 10.3MHz sine signal to ensure that the ADC works normally at -1dBFS. The host computer receives and saves the signal. After testing, its spectrum is as follows: Figure 4 As shown, the SNDR is 63.80dB, the SFDR is 83.60dB, and the ENOB is 10.30 bits.

[0060] After performing sinusoidal fitting on the above data, high-precision quantized data was obtained. After testing, the spectrum diagram is as follows: Figure 5 As shown, the SNDR is 157.40dB, the SFDR is 196.70dB, and the ENOB is 25.85 bits.

[0061] Set the sampling factor to 128, the interval acquisition times to 128, the offset constant to 127, and the feature dimension to 41. After data reconstruction, the amount of data in a batch is 128*(127+1)=16384. Use the neural network to batch train the reconstructed training data set. The training stops after 10 iterations to reach the convergence state. The neural network performs inference based on the test set, and the spectrum of the output result is as follows: Figure 6As shown, the SNDR is 88.0dB, the SFDR is 95.6dB, and the ENOB is 14.33 bits, which exceeds the effective accuracy expression limit of the 14-bit ADC.

[0062] As a result, we obtained a quantized output with an effective accuracy of up to 14.33 bits at an operating frequency of 1 GHz. In addition, its SNDR reached 88.0 dB and SFDR reached 95.6 dB, verifying the excellent performance of the ADC based on the heterogeneous channel architecture enhanced by neural network proposed in the present invention.

[0063] In summary, the present invention proposes an ADC based on a heterogeneous channel architecture enhanced by a neural network, including: two heterogeneous ADC channels, a delay module, a neural network circuit, and a streaming training controller.

[0064] The two heterogeneous ADC channels are a high-speed, low-precision channel and a low-speed, high-precision channel. The two channels are ADCs with different performances. The two channels are connected to the same signal source. The high-speed, low-precision channel has a higher sampling frequency and can quickly capture changes in high-frequency signals, but has lower accuracy. The low-speed, high-precision channel has a lower sampling frequency and can provide high-precision quantized data as a benchmark.

[0065] The delay module is connected to the output of two heterogeneous ADC channels to perform delay and alignment processing on the two output data. The multi-time dimension data of the high-speed and low-precision channel is aligned with the single time dimension data of the low-speed and high-precision channel after delay processing.

[0066] The neural network circuit consists of an input layer, a hidden layer and an output layer, wherein the number of neurons in the input layer is consistent with the characteristic dimension of the input data, the number of neurons in the hidden layer is adjustable, the number of neurons in the output layer is 1, and all nodes in the front and back layers are interconnected; the neural network circuit integrates the advantages of high-speed low-precision channels and low-speed high-precision channels through training, uses the output of the high-speed low-precision channel as training data, and the output of the low-speed high-precision channel as label data, adjusts weights and biases during the training process, and generates high-speed and high-precision quantized outputs.

[0067] The streaming training controller is used to globally control the data acquisition of two heterogeneous ADC channels, the alignment operation of the delay module, and the training data generation of the neural network circuit. It generates diversified training data through downsampling, time offset and batch processing operations.

[0068] The steps in the present invention can be adjusted in order, combined or deleted according to actual needs.

[0069] The units in the device of the present invention can be combined, divided and deleted according to actual needs.

[0070] Although the present invention is disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely exemplary and are not intended to limit the application of the present invention. The scope of protection of the present invention is defined by the appended claims and may include various modifications, alterations and equivalents made to the invention without departing from the scope and spirit of the present invention.

Claims

1. An ADC based on a heterogeneous channel architecture enhanced by a neural network, characterized in that: The ADC includes: two heterogeneous ADC channels, a delay module, a neural network circuit, and a streaming training controller; The two heterogeneous ADC channels are a high-speed low-precision channel and a low-speed high-precision channel. The two channels are ADCs with different performances and are connected to the same signal source. The high-speed low-precision channel has a higher sampling frequency than the low-speed high-precision channel and is used to quickly capture changes in high-frequency signals. The low-speed high-precision channel is used to provide high-precision quantized data as a benchmark. The delay module is connected to the output of the two heterogeneous ADC channels to perform delay and alignment processing on the two output data. The high-speed and low-precision channel forms multi-time dimension data after delay processing, which is aligned with the single time dimension data of the low-speed and high-precision channel. The neural network circuit consists of an input layer, a hidden layer, and an output layer. The number of neurons in the input layer is consistent with the characteristic dimension of the input data, the number of neurons in the hidden layer is adjustable, the number of neurons in the output layer is 1, and all nodes in the front and back layers are interconnected. The neural network circuit integrates the advantages of high-speed low-precision channels and low-speed high-precision channels through training, uses the output of the high-speed low-precision channel as training data, and the output of the low-speed high-precision channel as label data. The weights and biases are adjusted during the training process to generate high-speed and high-precision quantized outputs. The streaming training controller is used to globally control the data acquisition of two heterogeneous ADC channels, the alignment operation of the delay module, and the training data generation of the neural network circuit. It generates training data through downsampling, time offset and batch processing operations.

2. The ADC based on the neural network enhanced heterogeneous channel architecture as claimed in claim 1, characterized in that: The delay module is respectively connected to the outputs of the high-speed low-precision channel and the low-speed high-precision channel. The delay module delays the high-speed data according to the frequency of the sampling clock of the low-speed high-precision channel to ensure that the high-speed data is aligned with the low-speed data; the delay module temporarily stores the multi-time dimension data output by the high-speed low-precision channel through a register, aligns it with the single time dimension data of the low-speed high-precision channel after delay, and outputs synchronous data for use by the neural network circuit.

3. The ADC based on the neural network enhanced heterogeneous channel architecture as claimed in claim 1, characterized in that: The flow training controller workflow is as follows: S1, parameter setting: set the sampling clock frequency fa of the high-speed low-precision channel ADC and the sampling clock frequency fb of the low-speed high-precision channel ADC, and set the interval acquisition times N, the interval number is M; S2, interval downsampling operation: After the sampling clocks of the two channel ADCs are aligned for the first time, the sampling clock of the low-speed channel ADC is used as the reference for the first interval data downsampling, and a total of N data acquisitions are performed, each time the output data of multiple time dimensions is collected as training data, and the output data of one time dimension of the low-speed high-precision channel ADC is collected as label data; S3, offset operation: After each interval downsampling operation is completed, the streaming training controller performs a time offset on the sampling clock of the low-speed and high-precision channel. The offset is the high-speed and low-precision channel clock cycle 1 / fa. The low-speed and high-precision channel data after the time offset will be used with the new high-speed and low-precision data for the next interval downsampling operation; S4, batch processing operation: M interval downsampling operations are used as a batch processing cycle. Each batch contains N*(M+1) label data and corresponding multi-time dimension training data, which are input into the neural network circuit for training.

4. The ADC based on the neural network enhanced heterogeneous channel architecture as claimed in claim 1, characterized in that: The neural network circuit adapts to the quantization requirements of different signal characteristics by adjusting the number of neurons in the input layer and the hidden layer, thereby improving the generalization performance and reasoning accuracy of the model.

5. The ADC based on the neural network enhanced heterogeneous channel architecture as claimed in claim 1, characterized in that: A verification system for an ADC based on a heterogeneous channel architecture enhanced by a neural network is built. The verification system uses a signal fitting method to obtain high-precision quantization results as label data for a neural network circuit to replace the output of a low-speed and high-precision channel.

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