Decoding method, electronic device, storage medium and computer program product

Abstract

The present application relates to a decoding method, an electronic device, a storage medium and a program product. During decoding, a sequence to be decoded is first obtained, and a target decoding mode corresponding to the sequence to be decoded is determined. The common-mode decoder is reconstructed according to the target decoding mode. The reconstruction of the common-mode decoder includes determining the target operation module for performing operations in each general operation unit according to the target decoding mode, and determining the target connection mode of the general connection network according to the target decoding mode. Among them, the common-mode decoder is constructed based on a message passing algorithm, including a plurality of general operation units and a general connection network for connecting each general operation unit, and the general operation unit includes a plurality of operation modules. The sequence to be decoded is input into the reconstructed common-mode decoder for decoding to obtain a decoding result. The present application greatly improves the decoding efficiency and reduces the hardware power consumption of the decoder through the reuse of hardware resources, with low cost and high efficiency.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a decoding method, a common mode decoder, an electronic device, a storage medium and a computer program product. Background Art

[0002] In the increasingly complex communication system, there are many different communication scenarios. Different communication scenarios use different coding methods to meet the data transmission rate requirements in different communication scenarios and reduce the bit error rate through different coding methods in different communication scenarios.

[0003] In current digital baseband decoders, a single dedicated decoder architecture is generally designed for a single codeword. In complex communication scenarios, the decoder architecture of a single codeword is not compatible with multiple communication scenarios. The prior art can form a multi-mode decoder by stacking hardware resources to adapt to multiple communication scenario applications. However, the above-mentioned multi-mode decoder relies on hardware resource preset redundancy to meet multiple communication scenarios, resulting in low decoder hardware resource utilization, high cost, high power consumption, and low decoding efficiency. Summary of the invention

[0004] Based on this, it is necessary to provide an efficient decoding method, electronic device, storage medium and computer program product that can improve hardware utilization and data throughput while ensuring the reliability of polar code decoding in order to solve the above technical problems.

[0005] In a first aspect, the present disclosure provides a decoding method, the method comprising:

[0006] Obtaining a sequence to be decoded, and determining a target decoding mode corresponding to the sequence to be decoded;

[0007] Determine the target operation module for executing the operation in each general operation unit of the common mode decoder according to the target decoding mode, and determine the target connection mode of the general connection network according to the target decoding mode, so as to obtain the reconstructed common mode decoder; wherein the common mode decoder is constructed based on the message passing algorithm, including a plurality of general operation units and a general connection network for connecting the general operation units, and the general operation unit includes a plurality of operation modules;

[0008] The sequence to be decoded is input into the reconstructed common mode decoder for decoding to obtain a decoding result.

[0009] In some embodiments, the method further comprises:

[0010] Obtaining coding parameters corresponding to the sequence to be decoded, and obtaining a target decoding factor graph according to the coding parameters, and determining the node degree and node parallelism of the target decoding factor graph;

[0011] Before inputting the sequence to be decoded into the reconstructed common mode decoder for decoding, the method further includes:

[0012] The network size of the universal connection network is determined based on the node degree and node parallelism.

[0013] In some embodiments, the general operation unit includes a variable operation unit, a check operation unit and a data decompression unit connected in sequence, and inputs the sequence to be decoded into the reconstructed common mode decoder for decoding, including:

[0014] The sequence to be decoded is processed in the variable operation unit according to the target decoding mode to obtain variable update information output to the verification operation unit;

[0015] The verification operation unit performs iterative calculation according to the variable update information, and the verification update information obtained by the iterative calculation is decompressed by the data decompression unit and then cyclically input into the variable operation unit, so as to perform decoding by the cyclic iterative calculation.

[0016] In some embodiments, the method further comprises:

[0017] Obtaining decoding factor graphs corresponding to different codewords, the decoding factor graphs including check nodes and variable nodes;

[0018] In each decoding factor graph, an iterative formula for each check node is determined; a common operator for realizing minimum sum calculation is extracted from each iterative formula, and a check operation unit is constructed according to the common operator; wherein the check operation unit realizes the minimum sum calculation through a combination of a shift operation module and a symbol operation module, and updates the variable node information of the variable node according to the calculation result.

[0019] In some embodiments, the universal connection network includes a plurality of switch groups, and the target connection mode of the universal connection network is determined according to the target decoding mode, including:

[0020] In the target decoding mode, the control signals of the switch groups at each level are determined by the decoding factor graph; the switch groups of the universal connection network are selected by the control signals to obtain the target connection mode.

[0021] In some embodiments, the universal connection network includes a plurality of sub-networks, and the control signal is used to select each switch group of the universal connection network to obtain a target connection mode, including:

[0022] The sub-control signals corresponding to each sub-network are determined according to the control signal, and the switch groups in each sub-network are selected according to the sub-control signals to obtain the target connection mode; wherein, the target connection mode realizes multi-frame parallel processing through the parallel connection of each sub-network.

[0023] In some embodiments, determining the control signals of the switch groups at each level according to the decoding factor graph includes:

[0024] In the case where the sequence to be decoded is a low-density parity check code, determining a control signal according to a cyclic shift characteristic parameter of the sequence to be decoded and a decoding factor graph;

[0025] When the sequence to be decoded is a polar code, the control signal is determined according to the ordering characteristic parameter of the sequence to be decoded and the decoding factor graph.

[0026] In a second aspect, the present disclosure provides an electronic device including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method proposed in the first aspect when executing the computer program.

[0027] In a third aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the method proposed in the first aspect when the computer program is executed by a processor.

[0028] In a fourth aspect, the present disclosure provides a computer program product, including a computer program, which implements the steps of the method proposed in the first aspect when executed by a processor.

[0029] The above decoding method, electronic device, storage medium and computer program product first obtain the sequence to be decoded during decoding, and determine the target decoding mode corresponding to the sequence to be decoded. Then, the common mode decoder is reconstructed according to the target decoding mode. The reconstruction of the common mode decoder includes determining the target operation module for performing operations in each general operation unit according to the target decoding mode, and determining the target connection mode of the general connection network according to the target decoding mode. Among them, the common mode decoder is constructed based on the message passing algorithm, including a number of general operation units and a general connection network for connecting each general operation unit, and the general operation unit includes a number of operation modules. When the reconstruction of the common mode decoder is completed, the sequence to be decoded is input into the reconstructed common mode decoder for decoding to obtain a decoding result.

[0030] The present disclosure can realize unified decoding of different codewords through a common-mode decoder. During decoding, it is only necessary to determine the target decoding mode of the sequence to be decoded, and then the target operation module for calculating the target decoding mode in the general operation unit can be determined in the common-mode decoder, as well as the target connection relationship between the general operation units under the target decoding mode. The decoding method and common-mode decoder proposed in the present disclosure reconstruct the common-mode decoder according to different decoding modes during decoding by designing general operation units and general connection networks, and obtain operation units corresponding to the target decoding mode and the connection relationship between the operation units.

[0031] The present disclosure improves the utilization rate of the decoder hardware resources by reusing the hardware resources for decoding operations. Compared with the traditional decoding method by stacking hardware resources, the present disclosure greatly improves the decoding efficiency and reduces the hardware power consumption of the decoder by reusing the hardware resources while meeting the decoding requirements of multiple communication scenarios, with low cost and high efficiency. In addition, the decoding method and common mode decoder of the present disclosure have no restrictions on the code length and code rate of the decoding sequence to be decoded, and can be compatible with different communication standards. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 is a flowchart of a decoding method in some embodiments;

[0034] Figure 2 Schematic diagram of decoding factors of LDPC codes and polar codes in some embodiments, Figure 2 (a) is LDPC code, Figure 2 (b) is polarization code;

[0035] Figure 3 A schematic diagram of the structure of a general-purpose computing unit in some embodiments;

[0036] Figure 4 Schematic diagram of the hardware structure of the verification operation unit in some embodiments;

[0037] Figure 5 Schematic diagram of the hardware structure of the variable operation unit in some embodiments;

[0038] Figure 6 A connection diagram of a universal connection network in some embodiments;

[0039] Figure 7 is a schematic diagram of the structure of a common mode decoder in some other embodiments;

[0040] Figure 8 FIG. 4 is a diagram showing the internal structure of an electronic device in one embodiment. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0042] The fifth generation (5G) wireless communication system can support multiple application scenarios while maintaining good performance. In the baseband processing of wireless communication systems, channel coding effectively resists the damage of noise, interference and other factors to the signal by encoding the original data, ensuring that the information can be reliably transmitted from the transmitter to the receiver, and plays an indispensable role in information transmission. Channel coding can have different coding methods, LDPC code (Low-Density Parity-Check Code) and Polar Code are two commonly used coding methods.

[0043] In current digital baseband decoders, a single dedicated decoder architecture is generally designed for a single codeword. Although the decoder architecture will be optimized, it is still limited by a single algorithm during optimization. Although the high performance and high hardware utilization efficiency of a single codeword in a dedicated scenario are guaranteed, the dedicated architecture of a single codeword cannot be compatible with multiple communication scenarios in the face of 5G and the increasingly complex and differentiated communication application scenarios of future communications. The existing technology can design a multi-mode decoder by stacking hardware resources to adapt to multi-scenario applications. Although similar multi-mode decoders can rely on hardware resource preset redundancy to meet multiple communication scenarios, this method has the problems of low hardware utilization efficiency and increased power consumption. It is also subject to advanced semiconductor process technology and cannot obtain an efficient baseband processing architecture. In other words, although general-purpose processors based on CPUs and GPUs can take into account different baseband processing algorithms, the decoding efficiency is not high due to the high energy consumption of general-purpose processors in task scheduling.

[0044] In response to the above problems, Figure 1 As shown, in some embodiments, a decoding method is proposed, which can be used to implement decoding processing of multiple code words while improving hardware resource utilization and decoding efficiency. Figure 1 As shown, the decoding method includes the following steps 102 to 106. Among them:

[0045] Step 102: Obtain a sequence to be decoded and determine a target decoding mode corresponding to the sequence to be decoded.

[0046] In order to ensure efficient and reliable data transmission in the communication system, the transmission data can be encoded at the data sending end and the received data can be decoded at the data receiving end. The sequence to be decoded represents the sequence received by the data receiving end. By decoding the sequence to be decoded, the original data sent by the data sending end is obtained.

[0047] The target decoding mode corresponds to the encoding method of the sequence to be decoded. When decoding, the codewords of the sequence to be decoded can be mapped into a decoding factor graph, and the codewords that can be decoded by iterative calculation based on the decoding factor graph can all be decoded by the decoding method of this embodiment.

[0048] Exemplarily, when the sequence to be decoded is encoded by a low-density parity-check (LDPC) code, the target decoding mode corresponds to the LDPC decoding mode. The target decoding mode can also be a polar code decoding mode, a BCH (Bose–Chaudhuri–Hocquenghem codes) code decoding mode, a Reed Muller code decoding mode, and the like. During decoding, the target decoding mode can be determined by a mode identifier. For example, the target decoding mode when the mode identifier is "1" can be set to the LDPC decoding mode, and the target decoding mode when the mode identifier is "0" can be set to the polar code decoding mode.

[0049] Step 104, determining the target operation module for executing the operation in each general operation unit of the common mode decoder according to the target decoding mode, and determining the target connection mode of the general connection network according to the target decoding mode, to obtain a reconstructed common mode decoder; wherein the common mode decoder is constructed based on a message passing algorithm, including a plurality of general operation units and a general connection network for connecting the general operation units, and the general operation unit includes a plurality of operation modules.

[0050] The message passing (MS, MS for short) algorithm is a method of inference and statistics based on Bayesian theorem, which infers unknown information through existing information and prior information. The common mode decoder of this embodiment is constructed based on the message passing algorithm, which is an algorithm that approximates the optimal solution by passing messages between nodes. In the message passing algorithm, each node passes messages to neighboring nodes, and each node updates messages based on the messages of neighboring nodes and its own local signals. Exemplarily, the message passing algorithm may include belief propagation (BP for short), approximate message passing algorithm (AMP for short), expectation propagation algorithm (EP for short), etc.

[0051] The common mode decoder is an electronic device used in this embodiment to perform the decoding method of this embodiment. This embodiment constructs a common mode decoder based on a message passing algorithm, and the common mode decoder includes a universal connection network and a universal operation unit to adapt to the decoding operations of different codewords. Exemplarily, the common mode decoder includes a first number of universal operation units, and the universal operation unit corresponds to each computing node during iterative decoding. Each universal operation unit includes a second number of operation modules, each operation module performs different operation operations, and the first number and the second number may be equal or unequal. The operation module may be an adder, a shifter, a gate, etc.

[0052] The universal connection network is used to connect the universal operation units in the common mode decoder to adapt to the decoding requirements of different codewords. Exemplarily, the universal connection network can be a butterfly interconnection network, such as a crossbar network, a Benes network, a Banyan network, a barrel shifter architecture, a fat tree topology architecture, and the like.

[0053] After determining the target decoding mode, the universal connection network and universal operation unit of the common mode decoder are reconstructed to adapt to the target decoding mode. As mentioned above, the universal operation unit corresponds to each computing node during iterative decoding, that is, the node for message transmission. Each universal operation unit includes several operation modules, and the universal operation unit calculates through the reconstructed operation module to calculate through the reconstructed operation module to update the node information. The reconstruction of the universal operation unit indicates that the operation module for performing different decoding operations is determined according to different decoding modes. Compared with the traditional method of stacking hardware resources and determining the processing module through task scheduling, this embodiment improves hardware utilization and reduces hardware power consumption through the reuse of operation modules.

[0054] At the same time, the present embodiment also reconstructs the connection relationship between the general operation units according to the target decoding mode to meet the decoding requirements of different decoding modes. The common mode decoder of the present embodiment is constructed based on the message passing algorithm, and the message passing algorithm is mainly based on the message passing between the nodes of the graph to determine the optimal solution. In the case where the general operation unit corresponds to each computing node, the present disclosure reconstructs the connection mode of the general connection network according to the target decoding mode, and the reconstructed general connection network determines the target connection mode of each general operation unit according to the target decoding mode.

[0055] Step 106: input the sequence to be decoded into the reconstructed common mode decoder for decoding to obtain a decoding result.

[0056] This embodiment can achieve unified decoding of different codewords through the common mode decoder. When decoding, it is only necessary to determine the target decoding mode of the sequence to be decoded, and then determine the target operation module in the general operation unit for calculating the target decoding mode in the common mode decoder, and the target connection relationship between the general operation units under the target decoding mode.

[0057] This embodiment obtains a common-mode decoder based on a message passing algorithm, constructs a universal operation unit corresponding to a computing node in the message passing algorithm in the common-mode decoder, and a universal connection network connecting the universal operation units representing each computing node. When this embodiment decodes through a common-mode decoder, the operation module in the universal operation unit and the universal connection network can be reconstructed according to different decoding modes to obtain a universal operation unit corresponding to the target decoding mode and a connection relationship between each universal operation unit. Since this embodiment can perform decoding operations by reusing hardware resources, the utilization rate of the decoder hardware resources is improved. Compared with the traditional decoding method by stacking hardware resources, this embodiment can meet the application requirements of multiple general scenarios by reusing hardware resources, greatly improves the decoding efficiency, reduces the hardware power consumption of the decoder, and has low cost and high efficiency. At the same time, the common-mode decoder used in the decoding method does not limit the code length and code rate of the sequence to be decoded, can be compatible with different communication standards, and has strong scalability.

[0058] In some specific embodiments, the method further includes: obtaining coding parameters corresponding to the sequence to be decoded, and obtaining a target decoding factor graph based on the coding parameters, and determining the node degree and node parallelism of the target decoding factor graph; before inputting the sequence to be decoded into the reconstructed common mode decoder for decoding, the method further includes: determining the network scale of the universal connection network based on the node degree and node parallelism.

[0059] The coding parameters represent the parameters when encoding the sequence to be decoded. According to the coding parameters, the coding method of the sequence to be decoded, the structure of the encoded codeword, etc. can be determined. The coding parameters can be the coding method, code length or code rate of the sequence to be decoded. Among them, the coding method corresponds to the codeword type, such as LDPC code and polar code. The code length indicates the length of each codeword after encoding, and the code rate indicates the proportion of information bits in each codeword during encoding.

[0060] The target decoding factor graph is used to represent the coding structure and connection relationship of the sequence to be decoded. When the coding parameters such as the coding mode, code length and code rate are known, the decoding factor graph can be determined according to the coding parameters. Figure 2 Schematic diagram of decoding factors for LDPC codes and polar codes. Figure 2In the decoding factor graph shown in FIG. 1 , the circular node represents the variable node (VN) and the square node represents the check node (CN). The decoding based on the message passing algorithm is to iteratively pass messages between the variable node and the check node to finally obtain the decoding method that approximates the optimal decoding information.

[0061] In the decoding factor graph, the number of other nodes connected to each node is the node degree. Nodes are connected through edges, so the node degree of a node can be expressed as the number of edges connected to the node. The number of nodes in the decoding factor graph is the node parallelism. The decoding factor graph can be regarded as a factor graph obtained by extending and connecting multiple basic decoding factor graphs. The node parallelism represents the number of basic decoding factor graphs that need to be parallelized in the decoding factor graph obtained by extension.

[0062] The basic decoding factor graph is the smallest calculation unit in the decoding factor graph. In the same encoding method, the decoding factor graph can be considered to be formed by connecting several repeated basic decoding factor graphs. Figure 2 The dotted box in (a) is the basic decoding factor graph corresponding to the LDPC code, which includes five variable nodes and two check nodes. Figure 2 In (a), the basic decoding factor graph is expanded to obtain a decoding factor graph with a node parallelism of 2.

[0063] It can be understood that the connection relationship between the nodes of the basic decoding factor graphs of different codewords and the expansion mode of the basic decoding factor graph are related to the codeword type and the channel coding mode.

[0064] Figure 2 The dotted box in (b) is the basic decoding factor graph of the polar code, which includes four variable nodes and two check nodes, and is decoded by repeated iterative message passing between nodes. Figure 2 The decoding factor graph of the polar code shown in (b) is obtained by expanding the basic decoding factor graph of the polar code. The expanded decoding factor graph includes four levels of variable nodes, corresponding to four levels of messages, which correspond to the four columns of circular nodes in the figure, indicating the number of iterations during decoding.

[0065] Initially, only the first-level and last-level variable nodes input channel information and prior initial information, and the other-level messages are zero. Then, the second-level and third-level information are calculated from both ends, and the iterative calculation is repeated. Taking the second-level variable node as an example, when iterating to the left, the variable node can be understood as forming a basic decoding factor graph with the first-level variable node and the first-level check node; when iterating to the right, it can be understood as forming a basic decoding factor graph with the third-level variable node and the second-level check node. The two basic decoding factor graphs are connected through a network.

[0066] Figure 2 (a) is a schematic diagram of the decoding factor of the LDPC code. In the decoding factor diagram corresponding to the LDPC code, the maximum improvement Z of the LDPC code can be max Determine the node parallelism, at this time the node parallelism P1=Z max . Figure 2 (b) is a schematic diagram of the decoding factor of the polar code. In the decoding factor diagram corresponding to the polar code, the node parallelism can be determined by the code length N of the sequence to be decoded. At this time, the node parallelism P2=2 n-1 , n=log2N, n is used to represent the level of variable nodes.

[0067] In this embodiment, decoding is performed by passing messages between variable nodes and check nodes according to the message passing algorithm. The universal operation unit in the common mode decoder is used to implement iterative message passing operations in each node in the decoding factor graph. For different sequences to be decoded, the common mode decoder connects the universal operation units that implement the calculation of each node through a universal connection network to obtain a decoding architecture corresponding to the decoding factor graph. In addition to determining the target connection mode of the universal connection network through the target decoding mode, this embodiment also determines the scale of the universal connection network according to the decoding factor graph to ensure that each node in the decoding factor graph corresponds to a universal operation unit in the common mode decoder.

[0068] In some specific embodiments, a general computing unit such as Figure 3 As shown, it includes a variable operation unit, a check operation unit and a data decompression unit connected in sequence, and inputs the sequence to be decoded into the reconstructed common mode decoder for decoding, including: processing the sequence to be decoded in the variable operation unit according to the target decoding mode to obtain variable update information output to the check operation unit; performing iterative calculation in the check operation unit according to the variable update information, and decompressing the check update information obtained by the iterative calculation through the data decompression unit and then cyclically inputting it into the variable operation unit, so as to perform decoding by cyclic iterative calculation.

[0069] The message passing algorithm is an algorithm for implementing decoding by passing messages between nodes. The general operation unit corresponds to the node in the message passing algorithm. In combination with the aforementioned decoding factor graph, the nodes that transmit messages during decoding in this embodiment include variable nodes and check nodes. Correspondingly, the general operation unit corresponds to the node type, including a variable operation unit for performing variable node operations, a check operation unit for performing check node operations, and a data decompression unit for performing data decompression and transmission.

[0070] Please refer to Figure 3 As shown, the general operation unit includes a data decompression unit for decompressing node calculation information, a variable operation unit for updating variable node information, and a verification operation unit for calculating verification node information. Figure 3 As shown, a first data decompression unit is provided before the variable operation unit, and a second data decompression unit is provided after the verification operation unit. The operation modules in the first data decompression unit and the second data decompression unit are similar, and are both used for data decompression selection and transmission.

[0071] Taking LDPC code as an example, the check information calculated by the check operation unit is stored in the shared memory. Figure 3 As shown, the first data decompression unit decompresses the verification information of the iterative calculation of the last verification operation unit, and transmits the decompressed last verification message to the variable operation unit.

[0072] In addition to being connected to the first data decompression unit, the variable operation unit also receives channel a posteriori information. The variable operation unit is a configurable adder. The variable operation unit updates the variable information through the configurable adder according to the last verification information transmitted by the first data decompression unit and the channel a posteriori information, and transmits the updated variable information to the verification operation unit.

[0073] As shown in the decoding factor graph, the check node is connected to multiple variable nodes, so the check operation unit receives the variable information updated by multiple variable operation units, and iteratively updates the check information through the operation module in the check operation unit. The check information currently updated by the check node is also stored in the shared memory, so as to cyclically pass through the first decompression unit for data decompression and data transmission for the next iterative calculation. The second decompression unit updates the channel a posteriori message according to the check information updated by the check operation unit, and the updated channel a posteriori message is used for the next iterative calculation of the variable operation unit.

[0074] The check operation unit may include modules such as a shift operation module and a symbol operation module for executing check node and operation. The check operation module determines the connection relationship between the operation modules according to the target decoding mode to realize the operation of the check node.

[0075] For example, Figure 2As shown in (a), taking LDPC code as an example, at the tth iteration of the variable node, the variable node information It can be expressed as:

[0076] (1)

[0077] in, Represents the information passed from variable node v to check node c, Represented as the channel posterior information of variable node v, It is represented as the information passed from the check node c to the variable node v in the t-1th iteration.

[0078] At the tth iteration, check the node information It can be expressed as:

[0079] (2)

[0080] Among them, in order to facilitate hardware implementation and reduce hardware calculation complexity, The function can be simplified as:

[0081] (3)

[0082] in, is a constant cancellation factor.

[0083] At iteration t, the posterior message It can be expressed as:

[0084] (4)

[0085] When the target decoding mode of the common mode decoder is LDPC decoding, the variable operation unit is used to perform the information update calculation of the variable node of formula (1), and the information update can be realized by setting a configurable adder. The check operation unit is used to perform the information update calculation of the check node of formula (2). The first data decompression unit decompresses the data updated by the last iterative check operation unit and recirculates it to the variable operation unit for processing. The second data decompression unit updates the channel posterior information according to the calculation result of the check node. .

[0086] In other examples, such as Figure 2 As shown in (b), in polar codes, the nodes are bidirectional iterative calculations, responsible for performing left and right decoding iterative calculations respectively. The two types of iterative information are represented by L k,j and R k,j , represents the iterative information corresponding to the jth variable node of the i-th level in the decoding factor graph. The left and right iterative update calculation formula of the polar code can be expressed as:

[0087] (5)

[0088] Where N represents the code length, k represents the number of levels of variable nodes, j represents the sequence number of variable nodes at each level, corresponding to the jth variable node at that level, The function can be expressed as:

[0089] (6)

[0090] When the target decoding mode of the common mode decoder is polar code decoding, the check operation unit performs rightward and leftward decoding iterative calculations according to formula (5). The variable operation unit updates the variable node information according to the calculation result of the check operation unit and the data transmitted by other variable operation units. The data decompression unit decompresses the data iteratively updated by the check operation unit and circulates it to the variable operation unit for processing again.

[0091] Taking the left iterative calculation based on the 2j+1th variable node information of the kth level as an example, according to formula (5) In the verification operation module, based on formula (6), the information of the jth variable node of the k+1th level is iterated to the left, the information of the 2jth variable node of the kth level is iterated to the right, and the information of the j+N / 2th variable node of the k+1th level is calculated according to the information of the left iteration, and the calculation result is transmitted to the variable operation unit for calculation, so as to obtain the information of the left iteration update of the information of the 2j+1th variable node of the kth level.

[0092] In some further embodiments, the method also includes: obtaining a decoding factor graph corresponding to different codewords, the decoding factor graph including a check node and a variable node; in each decoding factor graph, determining an iterative formula for each check node; extracting a common operator for realizing minimum sum calculation in each iterative formula, and constructing a check operation unit according to the common operator; wherein the check operation unit realizes the minimum sum calculation through a combination of a shift operation module and a symbol operation module, and updates the variable node information of the variable node according to the calculation result.

[0093] In order to simplify the calculation when decoding based on the message passing algorithm, as shown in the above LDPC code and polar code, the calculation formula of the check node in the LDPC code is transformed into formula (3), and the calculation formula of the check node in the polar code is transformed into formula (6). Formula (3) and formula (6) are both deformations of the minimum sum calculation formula. In this embodiment, the variable nodes are traversed and iterated through the minimum sum calculation formula during decoding, and finally the optimal solution is approximated, reducing the complexity of hardware implementation.

[0094] Since both formula (3) and formula (6) can be regarded as variations of the minimum sum calculation formula, this embodiment constructs a check operation unit for performing minimum sum calculation based on the common operators of formula (3) and formula (6), and implements information update calculation of the check node through a shift operation module and a symbol operation module.

[0095] For example, please refer to Figure 3 The schematic diagram of the general computing unit is shown in FIG. Figure 3 As shown, the first data decompression unit, the variable operation unit, the verification operation unit and the second data decompression unit are connected in sequence according to the path of message transmission. As mentioned above, the first data decompression unit is used to decompress and store the information of the last iterative calculation, and the variable unit receives the update information output after decompression such as format conversion of the first data decompression unit, and updates the information of the variable node according to the result of the last iterative calculation. The verification operation unit includes a shift operation module, a selection operation module, a half-addition operation module and a sign operation module. The verification operation unit determines the connection relationship between the operation modules according to the target decoding mode, and the target operation module that performs the operation in the target decoding mode, so as to realize the decoding operation in the target decoding mode.

[0096] Please refer to Figure 4 Schematic diagram of the verification operation unit shown. Figure 4 (a) The corresponding target coding mode is LDPC code, Figure 4 (b) The corresponding target coding mode is polar code. It can be seen from the above formulas (3) and (6) that this embodiment simplifies the check node calculation formulas of LDPC code and polar code respectively to obtain different minimum and minimum calculation formulas. Among them, the check node of LDPC code needs to perform symbol value operation on the input parameter and calculate the minimum value and the second minimum value according to formula (3). The check node of polar code needs to perform symbol value operation and minimum value calculation on the input parameter according to formula (6). Therefore, this embodiment uses symbol operation and minimum value calculation as common operators of formula (3) and formula (6) to construct a check operation unit.

[0097] like Figure 4 As shown in (a), when the target coding mode is LDPC code, the target operation module of the check operation unit includes four selection operation modules, two shift operation modules, one symbol operation module symbol 1 and one half-addition operation module. When the check operation unit performs the check node update of the LDPC code, the a posteriori message and the information updated by the last verification node iteration Input the adder of the variable operation unit respectively and output the variable node information As shown in formula (3), for variable node information The first symbol operation module performs symbol operation, and outputs the symbol operation result xor_sign through the fourth register; the variable node information is shifted through the shift operation module Subtract the constant offset factor, and output the minimum value min_1st in the second register and the second minimum value min_2nd in the third register. The first register outputs the serial number of the variable node, which is used to determine the Vn to which the currently calculated minimum value min_1st belongs. As shown in formula (3), when the serial number min_id of the calculated minimum value min_1st is itself, the second minimum value min_2nd is output to the next variable node.

[0098] like Figure 4 As shown in (b), when the target coding mode is polar code, the target operation module of the check operation unit performing the operation operation includes two selection operation modules, two shift operation modules, three symbol operation modules of symbol 1, symbol 2 and symbol 3, and two half addition operation modules. Figure 4 When the check operation unit in (b) performs iterative update of the check node of the polar code, the messages iterated to the left and right are respectively passed through the adder of the input variable operation unit. As shown in formula (6), the shift operation module is used to make a difference with the constant factor, and the iterative calculation values ​​are output respectively.

[0099] By Figure 4 (b) The check operation unit performs the calculation in formula (5) The configurable adder of the variable operation unit will and Add and The symbol operation is performed in the first symbol operation module, the minimum sum operation is performed through the shift calculation module and the gating calculation module, and the iteration is output in the third calculator. The iterative calculation result of Perform a sign operation, output a first sign operation result sign1 through the fourth register, and output a second sign operation result sign2 through the fifth register.

[0100] In some other embodiments, such as Figure 5 Schematic diagram of the variable operation unit shown. Figure 5 (a) The corresponding target coding mode is LDPC code, Figure 5 (b) The corresponding target coding mode is polar code. In the calculation of LDPC code, the adder can be configured to receive the data output by the data decompression unit, and update the variable node information according to the iterative calculation value of the last check node and the posterior message. In the calculation of polar code, the adder can be configured to receive the data output by the data decompression unit, and update the variable node information according to the left and right bidirectional iterative data.

[0101] In some embodiments, the universal connection network includes several levels of switch groups, and the target connection mode of the universal connection network is determined according to the target decoding mode, including: under the target decoding mode, determining the control signal of each level of switch group through the decoding factor graph; and selecting each switch group of the universal connection network through the control signal to obtain the target connection mode.

[0102] The universal connection network determines the target connection mode between the universal operation units according to the target decoding mode. Different decoding modes and different encoding parameters correspond to different decoding factor graphs. Accordingly, the universal connection network has different connection modes.

[0103] The switch group is the control unit of the universal connection network. It can be understood that the universal connection network selects whether the networks are connected or not according to the control signal of the switch group, and then determines the connection state between the universal operation units. When constructing a common mode decoder, the control signal of the universal connection network can be preset according to the decoding mode. When the common mode decoder is reconstructed according to the sequence to be decoded, the control signal of the switch group in the universal connection network can be obtained after the target decoding mode is determined, so as to determine the target connection mode of the universal connection network according to the control signal.

[0104] This embodiment determines the target connection mode of the universal connection network through the control signal, and can flexibly control the universal connection network. Exemplarily, the control signal of the switch group is related to the node connection relationship between the decoding factor graphs. When the target decoding mode is determined, the decoding factor graph is obtained according to the sequence to be decoded, and then the target connection mode of the universal connection network is determined according to the decoding factor graph to meet the connection of each node in the decoding factor graph.

[0105] In some specific embodiments, the universal connection network includes multiple sub-networks, and the target connection mode is obtained by selecting each switch group of the universal connection network through the control signal, including: determining the sub-control signal corresponding to each sub-network according to the control signal, and selecting the switch group in each sub-network according to the sub-control signal to obtain the target connection mode; wherein, the target connection mode realizes multi-frame parallel processing through parallel connection of each sub-network.

[0106] The subnetwork represents a network unit obtained by splitting the general connection network. For large-scale decoding requirements, this embodiment can divide the general connection network into several subnetworks, and distribute the decoding data to each subnetwork for parallel processing to improve the decoding efficiency and decoding speed. Each subnetwork works independently and in parallel, and the control signal can control the connection relationship between each subnetwork while ensuring the load balance of each subnetwork.

[0107] by Figure 6The universal connection network shown in FIG. 1 is taken as an example. The universal connection network generates a control signal according to the target decoding mode and the network parallelism. The conversion unit represents a variable connection mode in the universal connection network, that is, in different decoding modes, the conversion unit corresponds to different connection modes. The conversion unit determines the connection mode according to the control signal of the conversion unit. Figure 4 In the schematic diagram of the check operation unit shown in FIG. 1 , when the target decoding mode is LDPC code, the control signal of the conversion unit received by the universal connection network is represented as 0, and the input signal IN1 is parallel to the input signal IN2, that is, the input signal IN1 is connected to the output signal OUT1, and the input signal IN2 is connected to the output signal OUT2; when the target decoding mode is polar code, the control signal of the conversion unit received by the universal connection network is represented as 1, and the input signal IN3 is crossed with the input signal IN4, that is, the input signal IN3 is connected to the output signal OUT4, and the input signal IN4 is connected to the output signal OUT3.

[0108] When the size of the decoding factor graph is smaller than the size of the general connection network, the general connection network can be split to achieve multi-frame parallel processing through parallel connection of multiple sub-networks. Figure 6 The network size of the universal connection network is 512, that is, the universal connection network can be used to implement 512 If the number of nodes in the decoding factor graph is 512, the universal operation unit can be directly connected through the universal connection network. If the number of nodes in the decoding factor graph is 256, the network can be split into two sub-networks with a network size of 256, and the universal operation unit is connected based on each sub-network, and then the current decoding factor graph is iteratively decoded in parallel according to the parallelism of the two sub-networks.

[0109] In some specific embodiments, the control signals of the gating switch groups at each level are determined according to the decoding factor graph, including: when the sequence to be decoded is an LDPC code, the control signal is determined according to the cyclic shift characteristic parameter of the sequence to be decoded and the decoding factor graph; when the sequence to be decoded is a polar code, the control signal is determined according to the sorting characteristic parameter of the sequence to be decoded and the decoding factor graph.

[0110] Taking the Banyan network in the butterfly interconnection network as a universal connection network as an example, the control signal generation method is specifically described. The Banyan network is a butterfly interconnection network. Each level in the Banyan network includes N / 2 switching units. The switching unit can be understood as a switch group in the above network. The target connection mode in the Banyan network is determined by generating a control signal of the switching unit. Different decoding modes correspond to different control signals.

[0111] The Banyan network has the flexibility of self-selected routing characteristics, that is, it can select the optimal path according to the control signal, making it an ideal choice for constructing the universal connection network in the common mode decoder of this embodiment. In particular, the Banyan network can be flexibly split when parallel processing is required, and parallel decoding processing can be achieved through the split sub-networks, thereby improving the hardware throughput of decoding.

[0112] The universal connection network of this embodiment has an input and output scale P N The combined Banyan network includes two upper and lower Banyan networks. Each Banyan network includes log2P N +1 level.

[0113] For ease of understanding, this embodiment also takes LDPC code and polar code as examples to illustrate the control signal generation method under different target decoding modes.

[0114] When the target decoding mode is LDPC code

[0115] The Banyan network is used to determine the control signal for the cyclic shift parameter between the decoding factor graphs of the LDPC code. The cyclic shift parameter usually refers to the shift operation used when constructing the check matrix of the LDPC code, which is used to generate a sparse matrix of a specific structure. When generating the control signal of the general connection network, it is necessary to determine p n +1 level universal connection network control signal, p n Represents log2P N . n +1 level control signals are generated separately, that is, the universal connection network is determined separately before p n The control signal of the first level, and then the control signal of the last level general connection network.

[0116] The Banyan network's p n +1 level control signal is defined as C k , where 0≤k < p n , its control scheme can be expressed as:

[0117] (7)

[0118] The functions zeros(a, 1) and ones(a, 1) represent zero vectors and all-one vectors of size 1×a, respectively. The operator is a concatenation operation, for example, a a = [aa]. In formula (7), the control signal C of the k+1th level is k By intercepting the parameter s k and shift parameter l k Calculation. Parameters kand shift l k By decoding the cyclic shift parameter SV of the factor graph and the network size P N Calculation, expressed as:

[0119] (8)

[0120] Among them, the operator and The least significant k bits of the binary form bin(a) of the variable a are truncated and shifted right by k bits. When calculating the control signal, the truncation and shift operations are adopted in formula (8) to significantly simplify the calculation amount, so that the previous p n The control signals of the two stages can be generated simultaneously, which not only shortens the critical path during decoding, but also reduces the complexity of hardware implementation.

[0121] As described in the above embodiment, the universal connection network can be split into multiple parallel sub-networks according to the scale of the decoding factor graph to improve the computational efficiency. Assume that the parallelism of the combined Banyan network is defined as M P =log2(P N / P M ). M represents the required size of the Banyan sub-network after splitting. It can be seen that the control signal C k It is determined by formula (7) that when P M =P N In contrast, when the degree of parallelism is equal to k', k' > 0, the control signals of the first k' stages are set to zero. For example, C k =zeros(P N / 2, 1), where 0≤k < k'. For the last level of selection signal control, the pth n +1 level control signal C pn for:

[0122] (9)

[0123] Among them, the operator Represents multiple concatenation operations, for example, .

[0124] Formulas (7) and (9) are based on the network size P of the general connection network N , the required size of the sub-network P M The cyclic shift parameter SV in the target decoding mode determines the control signal of each level of the Banyan network. In addition, it is worth noting that for the above network parallelization method, the shift value configuration of the top and bottom Banyan networks depends on the parallelism P of the Banyan network and the boost value Z of the LDPC code. Combined with the required scale parameter P of the sub-network Mand the lifting value Z of the LDPC code, the top Banyan network is assigned a shift value SV1, where SV1 = SV, and the bottom Banyan network is assigned a shift value SV2, where SV2 must satisfy the condition At this time, it can be achieved in scale P N = Any shift value and input data size within 512.

[0125] When the target decoding mode is polar code

[0126] The control signal of the polar code is related to the sorting characteristic parameters of the sequence to be decoded. For the polar code, the network connections for message propagation to the left and right between nodes at all levels in the decoding factor graph are fixed, and the indexes before and after the left and right connections respectively satisfy the following connection relationship:

[0127] ,

[0128] In polar codes, the control signal is determined according to the connection relationship to the left and right of the decoding factor graph. For leftward propagation, the front p of the upper Banyan network in the combined Banyan network n The level signal control scheme can be expressed as:

[0129] (10)

[0130] in,

[0131] For the bottom Banyan network n The level signal control scheme can be expressed as:

[0132] (11)

[0133] In formula (11), the operator ~ is a bitwise inversion operation. The control signal C of the last stage is pn It can be expressed as:

[0134] (12)

[0135] According to formulas (10) and (11), the control signal of each stage can be determined for L propagation. P is equal to k', where k' > 0, the control signal C k top / bot , where 0≤k < k', is set to zero, and the control signal for stage k' + 1 should be reconfigured as:

[0136] (13)

[0137] The above control signal scheme can realize L propagation of polar codes and parallelism of multiple degrees of parallelism. For R propagation, the following control scheme is proposed through a recursive process:

[0138] , (14)

[0139] in,

[0140] Similar to the parallelism configuration of L propagation, when the parallelism M P When k' is equal to k', where k' > 0, the control signals of the first k' stages of R propagation are set to zero. Then, the control signals of the other stages should be reconfigured as:

[0141] (15)

[0142] Among them, p m = log2 P M In addition, the control signal of the last level is also affected by the parallelism of the Banyan network. n The control signal of the +1 stage is expressed as:

[0143] (16)

[0144] It is worth noting that when the parallelism M P When set to 0, the parameter p m and p n same.

[0145] It can be seen that the decoding method disclosed in the present invention has no restrictions on parameters such as the code length and code rate of the sequence to be decoded, can take into account sequences of different sizes to be decoded, meet different communication standards, flexibly take into account the decoding of short codes and long codes, and is suitable for multiple communication scenarios under the 5G standard. The setting of the universal connection network further improves hardware efficiency, and the parallel control of the universal network can realize multi-frame parallel processing during decoding, improving the architecture throughput and hardware utilization efficiency.

[0146] In some other embodiments, a common mode decoder is provided, which is used to perform the decoding method of the above embodiment. The common mode decoder includes a plurality of general operation units and a general connection network for connecting the general operation units, and the general operation unit includes a plurality of operation modules for performing decoding operations. The general connection network determines the target connection mode of the general connection network according to the target decoding mode configured by the parameters, and the general operation unit determines the target operation module for performing the operation in each general operation unit according to the target decoding mode.

[0147] The general operation unit is a unit in the common mode decoder for performing decoding operations. The general operation unit includes several operation modules, each of which is used to perform different operation operations. Exemplarily, the operation module can be an addition operation module, a shift operation module, a selection operation module, a symbol operation module, etc. The general operation unit reconstructs different operation modules according to the target decoding mode and determines the target decoding module to perform the operation.

[0148] The universal connection network represents the connection relationship between the universal operation units in the common mode decoder, so that the universal operation units can pass messages to realize the decoding operation. Exemplarily, the universal connection network can be an interconnection network, such as the crossbar network in the butterfly switching network, the Benes shift network, the Banyan network, the barrel shifter architecture, the fat tree topology architecture, and the like.

[0149] Figure 7 The figure shows a schematic diagram of the structure of a common-mode decoder. In addition to the above-mentioned universal connection network and universal operation unit, the common-mode decoder also includes an input cache, an output cache, a storage module and a parameter configuration module. The sequence to be decoded is input into the common-mode decoder through the input cache. The common-mode decoder includes two universal connection networks, which correspond to the first pn level and the last level of the decoding factor graph of the sequence to be decoded. The universal connection network determines the target connection mode according to the sequence to be decoded, so as to iteratively calculate the input data in the universal operation unit corresponding to the target connection mode. The universal operation unit is connected to the memory to store the intermediate data of the iterative operation in the shared memory and the result of the symbolic operation in the symbolic memory. After the universal operation unit connected to the last level of the universal connection network calculates, the decoding result is transmitted to the output cache through the pipeline register. The output cache includes a decoding decision unit and an iteration calculator. The decoding decision unit makes a decoding decision on the calculation result of the common-mode decoder according to the iteration of the iteration calculator, and outputs the decoding result. As shown in Figure 7 As shown, the general operation unit includes a plurality of verification operation units and a plurality of variable operation units, and a decompression operation unit for performing data decompression and message transmission between the verification operation unit and the variable operation unit.

[0150] The parameter configuration module includes channel matrix feature management, channel matrix row weight management and parameter configuration register group. Among them, the channel matrix feature management is used to determine the channel matrix features under different decoding modes, and the signal matrix row weight management is used to determine the channel matrix row weight under different decoding modes. Among them, the matrix characteristics include the index of the participating variable nodes in each row, the corresponding cyclic shift value, and whether there is a read-write conflict with the previous row. The channel matrix row weight management mainly stores the number of participating variable nodes in each row, which is used to switch between rows during the row update process. The parameter configuration register group mainly records the configuration parameters under the two decoding modes, such as decoding mode, parallelism, number of matrix rows, number of columns, etc.

[0151] In some embodiments, still taking LDPC code and polar code as an example, parameter configuration can be performed in the parameter configuration module through Table 1.

[0152] Table 1

[0153]

[0154] The base matrix in Table 1 is the basic decoding factor graph when constructing the decoding factor graph, and the number and requirements of the base matrix in the table match the 5G NR standard. The decoding method of this embodiment can perform parameter configuration in the parameter configuration module according to the decoding requirements and decoding standards, and determine the decoding matrix of the sequence to be decoded according to the configured parameters to obtain the decoding factor graph, which can be compatible with the decoding processing of different channel matrices and meet the configurability design of the 5G NR standard.

[0155] The common mode decoder determines the target decoding mode according to the parameters configured by the parameter configuration module, and reconstructs the common mode decoder's universal connection network and universal operation unit to match the reconstructed common mode decoder with the target decoding mode. Compared with the traditional method of stacking hardware resources and determining the processing module through task scheduling, the common mode decoder of this embodiment improves hardware utilization and reduces hardware power consumption through the reuse of operation modules.

[0156] Each module in the polar code decoding device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in an electronic device in the form of hardware, or can be stored in a memory in the electronic device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0157] In an exemplary embodiment, an electronic device is provided. The electronic device may be a receiving end, and its internal structure diagram may be as shown in FIG. Figure 8As shown. The electronic device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the electronic device is used to exchange information between the processor and an external device. The communication interface of the electronic device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a polarization code decoding method is implemented. The display unit of the electronic device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the electronic device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the electronic device casing, or an external keyboard, touchpad or mouse.

[0158] Those skilled in the art will understand that Figure 8 The structure shown in the figure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the electronic device to which the scheme of the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0159] In an exemplary embodiment, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0160] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0161] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0162] It should be noted that the received signals and data involved in this application (including but not limited to data used for analysis, stored data, displayed data, etc.) are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0163] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0164] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0165] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A decoding method, characterized in that: The method comprises: Acquire a sequence to be decoded, and determine a target decoding mode corresponding to the sequence to be decoded; Determine the target operation module for executing the operation in each general operation unit of the common mode decoder according to the target decoding mode, and determine the target connection mode of the general connection network according to the target decoding mode, so as to obtain the reconstructed common mode decoder; wherein the common mode decoder is constructed based on the message passing algorithm, including a plurality of general operation units and a general connection network for connecting the general operation units, and the general operation unit includes a plurality of operation modules; The sequence to be decoded is input into the reconstructed common mode decoder for decoding to obtain a decoding result.

2. The method according to claim 1, characterized in that: The method further comprises: Obtaining coding parameters corresponding to the sequence to be decoded, and obtaining a target decoding factor graph according to the coding parameters, and determining a node degree and a node parallelism of the target decoding factor graph; Before inputting the sequence to be decoded into the reconstructed common mode decoder for decoding, the method further includes: The network scale of the universal connection network is determined according to the node degree and the node parallelism.

3. The method according to claim 1, characterized in that The general operation unit includes a variable operation unit, a check operation unit and a data decompression unit connected in sequence, and the inputting the sequence to be decoded into the reconstructed common mode decoder for decoding includes: Processing the sequence to be decoded according to the target decoding mode in the variable operation unit to obtain variable update information output to the verification operation unit; The verification operation unit performs iterative calculation according to the variable update information, and the verification update information obtained by the iterative calculation is decompressed by the data decompression unit and then cyclically input into the variable operation unit, so as to perform decoding by cyclic iterative calculation.

4. The method according to claim 3, characterized in that The method further comprises: Obtaining a decoding factor graph corresponding to different codewords, wherein the decoding factor graph includes a check node and a variable node; In each of the decoding factor graphs, an iterative formula for each of the check nodes is determined; a common operator for implementing minimum sum calculation is extracted from each of the iterative formulas, and a check operation unit is constructed according to the common operator; wherein the check operation unit implements minimum sum calculation through a combination of a shift operation module and a symbol operation module, and updates the variable node information of the variable node according to the calculation result.

5. The method according to claim 2, characterized in that: The universal connection network includes a plurality of switch groups, and the target connection mode of the universal connection network is determined according to the target decoding mode, including: In the target decoding mode, control signals of the switch groups at each level are determined by the decoding factor graph; the switch groups of the universal connection network are switched on by the control signals to obtain the target connection mode.

6. The method according to claim 5, characterized in that The universal connection network includes a plurality of sub-networks, and the control signal is used to select each switch group of the universal connection network to obtain the target connection mode, including: The sub-control signals corresponding to each of the sub-networks are determined according to the control signal, and the switch groups in each of the sub-networks are selected according to the sub-control signals to obtain the target connection mode; wherein the target connection mode realizes multi-frame parallel processing through the parallel connection of each of the sub-networks.

7. The method according to claim 5, characterized in that The step of determining the control signals of the switch groups at each level according to the decoding factor graph comprises: In the case where the sequence to be decoded is a low-density parity-check code, determining the control signal according to a cyclic shift characteristic parameter of the sequence to be decoded and the decoding factor graph; In a case where the sequence to be decoded is a polar code, the control signal is determined according to an ordering characteristic parameter of the sequence to be decoded and the decoding factor graph.

8. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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