RZI code to NRZ code conversion method and decoding circuit and chip

Abstract

The present invention discloses a conversion method for converting RZI coding to NRZ coding, a decoding circuit and a chip. The conversion method comprises the following steps: calculating the bit width of the first received signal according to the baud rate of the transmitting end; dividing each bit width into N sampling points; when the first received signal has a falling edge of a low-level pulse, the sampling point counter is cleared and starts counting, and at the same time, the second received signal and the shielding signal are pulled down to a low-level state; the first sampling point signal is generated at the end position of the middle sampling point of each bit, and the shielding signal is pulled up to a high-level state; the second sampling point signal is generated at the end position of the last sampling point of each bit, the sampling point counter is cleared and restarts counting; at the same time, the level state of the second received signal is adjusted after logical judgment is made on the first received signal and the shielding signal. The conversion method uses a digital circuit to realize the real-time conversion of two codes, and has the beneficial effect of high baud rate tolerance.

Description

Technical Field

[0001] The invention relates to a method for converting RZI coding to NRZ coding, and also relates to a corresponding decoding circuit and an integrated circuit chip, belonging to the technical field of digital communication. Background Art

[0002] The information primitives that digital circuits can process are digital 0 and 1. Digital communication is to use a specific communication protocol and corresponding encoding to convert digital information into a string of bit streams for transmission. Among them, NRZ (Not-Return-to-Zero) encoding is abbreviated as non-return-to-zero code. Communication protocols that use NRZ encoding usually include UART protocol, SPI protocol, etc. Figure 1 and Figure 2 As shown in the figure, the characteristic of NRZ coding is that a high level is used to send digital 1 and a low level is used to send digital 0. Since the energy of the transmitted pulse is relatively dense, NRZ coding is widely used in application scenarios that require high information density, such as terminal equipment and digital modulation equipment. RZI (Return-to-Zero-Inverted) coding is referred to as return-to-zero code. Communication protocols that use RZI coding usually include infrared communication protocols. The characteristic of RZI coding is that a low level is used to send digital 1 and a high level pulse is used to send digital 0, and the final transmission pulse level returns to the zero state; in addition, RZI coding can also use a level inversion transmission mode, that is, a high level is used to send digital 1 and a low level pulse is used to send digital 0. RZI coding in infrared communication protocols is usually widely used in wireless remote control, infrared temperature measurement, infrared photography, and short-distance communication. Compared with NRZ coding, RZI coding consumes less energy in communication because the effective level time is shorter.

[0003] In some application scenarios of the prior art, it is usually necessary to convert RZI encoding into NRZ encoding to achieve digital communication. For example, in the field of intelligent control of home appliances, infrared remote controls usually use RZI-encoded digital signals, while microcontrollers usually have UART interfaces, and digital signals use NRZ encoding. The method of converting RZI encoding to NRZ encoding is usually to use software to read the infrared signal status on the microcontroller GPIO and perform software programming decoding; when other programs are running at the same time or high-priority interrupts are allowed, the real-time decoding cannot be guaranteed, and the conversion method has the problems of poor real-time performance and poor compatibility. Therefore, it is necessary to design a conversion method and a corresponding decoding circuit that can perform real-time conversion from RZI encoding to NRZ encoding, and can be compatible with the requirements of infrared protocols for different pulse widths, and has the advantages of high tolerance to baud rates, to meet the requirements of digital communication systems.

[0004] In the Chinese invention patent with patent number ZL 202011566437.3, a method for processing coded data is disclosed. After determining that the acquired non-return-to-zero NRZ coded data is a valid signal, the method parses the first leading data and the valid coded data from the non-return-to-zero NRZ coded data, and converts the valid coded data into differential Mann code data based on the first leading data and the preset data conversion rule; and then realizes the acquisition of differential Mann code data through the serial port, so that the data acquisition process can directly compare the coded data for easy application. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide a method for converting RZI coding to NRZ coding.

[0006] Another technical problem to be solved by the present invention is to provide a decoding circuit for converting RZI encoding to NRZ encoding.

[0007] Another technical problem to be solved by the present invention is to provide an integrated circuit chip including the above decoding circuit.

[0008] In order to achieve the above object, the present invention adopts the following technical solutions:

[0009] According to a first aspect of an embodiment of the present invention, a method for converting RZI encoding to NRZ encoding is provided, comprising the following steps:

[0010] (1) calculating the bit width of the first received signal according to the baud rate of the signal sent by the transmitting end;

[0011] (2) dividing each bit width of the first received signal into N sampling points, where N is a positive integer;

[0012] (3) When the first receiving signal has a falling edge of a low-level pulse, the sampling point counter is cleared and starts counting, and at the same time, the second receiving signal is pulled down to a low-level state, and the shielding signal is pulled down to a low-level state;

[0013] (4) when the first received signal ends at the middle sampling point of each bit, the sampling point counter generates a first sampling point signal to control the shielding signal to be pulled high to a high level state;

[0014] (5) when the first received signal is at the end position of the last sampling point of each bit, the sampling point counter generates a second sampling point signal;

[0015] (6) according to the second sampling point signal, control the sampling point counter to be cleared and restart counting; at the same time, at the first sampling point start bit of the next bit, perform a logical judgment on the level states of the first received signal and the shielding signal, and adjust the level state of the second received signal according to the judgment result; specifically, the following three situations are included:

[0016] When the first receiving signal is at a high level and the shielding signal is at a high level at the same time, maintaining or pulling up the second receiving signal to a high level state;

[0017] When the first receiving signal is at a high level and the shielding signal is at a low level, maintaining or pulling down the second receiving signal to a low level state;

[0018] When the first receiving signal is at a low level and the shielding signal is at a low level, maintaining or pulling down the second receiving signal to a low level state;

[0019] (7) After receiving the second sampling point signal, within the period from the first sampling point to the last sampling point of the next bit, if the first received signal has a falling edge of a low level pulse, pull the shielding signal to a low level state and pull the second received signal to a low level state; otherwise, proceed to the next step;

[0020] (8) Go to step (4), and execute steps (4) to (7) in a loop until a data frame decoding conversion is completed;

[0021] (9) Go to step (3) and execute steps (3) to (8) in a loop until the decoding and conversion of the received data is completed.

[0022] Preferably, in step (3), in each data frame conversion of the first received signal, frame synchronization is performed using the falling edge of the low-level pulse of the frame start bit as the starting position of the first sampling point.

[0023] Preferably, in step (3), the input signal of the sampling point counter is a sampling pulse of each sampling point, and the sampling pulse is provided by a baud rate counter.

[0024] Preferably, the maximum baud rate tolerance of the conversion method is ±5.55%.

[0025] According to a second aspect of an embodiment of the present invention, a decoding circuit for converting RZI code to NRZ code is provided, which is implemented based on the above-mentioned conversion method for converting RZI code to NRZ code. The decoding circuit includes an edge detection module, a register module, a counter module, and a first AND gate, a second AND gate, a third AND gate, a fourth AND gate and a fifth AND gate, as well as a first OR gate, a second OR gate, a first inverter and a second inverter; wherein,

[0026] The edge detection module is used to detect the falling edge of the input first receiving signal. When the first receiving signal has a falling edge of a low level pulse, the edge detection module outputs a high level pulse signal to provide to the relevant logic circuit;

[0027] The register module is used to generate and output a shielding signal and a second receiving signal according to a control signal provided by a related logic circuit;

[0028] The counter module includes a baud rate counter and a sampling point counter. The baud rate counter is used to generate a sampling pulse and provide it to the sampling point counter. The sampling point counter is used to count each sampling point in each bit of the first received signal, and generate and output a first sampling point signal and a second sampling point signal in each bit and provide them to a related logic circuit.

[0029] Preferably, the first input end of the first AND gate is connected to the input end of the two sampling point signals, and the second input end is connected to the input end of the first receiving signal; the output end of the first AND gate is connected to the first input end of the second AND gate, and the second input end of the second AND gate is connected to the output end of the shielding signal of the register module.

[0030] Preferably, the first input end of the first OR gate is connected to the output end of the second AND gate, the second input end is connected to the output end of the second receiving signal of the register module, the output end of the first OR gate is connected to the second input end of the fifth AND gate; the output end of the edge detection module is connected to the first input end of the fifth AND gate through the second inverter; the output end of the fifth AND gate is connected to the first input end of the register module.

[0031] Preferably, the input end of the first inverter is connected to the output end of the shielding signal of the register module, and the output end is connected to the first input end of the third AND gate; the second input end of the third AND gate is connected to the input end of the first sampling point signal, and the output end of the third AND gate is connected to the first input end of the second OR gate; the output end of the edge detection module is connected to the first input end of the fourth AND gate through the second inverter, the output end of the shielding signal of the register module is connected to the second input end of the fourth AND gate, and the output end of the fourth AND gate is connected to the second input end of the second OR gate; the output end of the second OR gate is connected to the second input end of the register module.

[0032] Preferably, the decoding circuit also includes a start bit synchronization module for detecting the data frame of the first received signal. When a low-level signal of the start bit of the data frame is detected, a reset signal is output to reset the D flip-flops in each module to an initial value, so that each data frame is resynchronized from the start bit.

[0033] According to a third aspect of an embodiment of the present invention, there is provided an integrated circuit chip, comprising the above-mentioned RZI encoding to NRZ encoding decoding circuit.

[0034] Compared with the prior art, the present invention provides a RZI coding to NRZ coding conversion method and decoding circuit, which realizes the real-time conversion of RZI coded signals to NRZ coded signals by adopting a digital circuit and introducing a shielding signal to participate in logic judgment. At the same time, the conversion method can be compatible with the requirements of infrared protocols for different pulse widths, has a beneficial effect of high baud rate tolerance, is suitable for application scenarios where RZI coding needs to be converted to NRZ coding, and the decoding circuit is conveniently integrated in any UART circuit of the application system to meet the requirements of the digital communication system. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The level diagram of RZI coding and NRZ coding in the prior art Figure 1 ;

[0036] Figure 2 The level diagram of RZI coding and NRZ coding in the prior art Figure 2 ;

[0037] Figure 3 A flow chart of a method for converting RZI encoding to NRZ encoding provided by the present invention;

[0038] Figure 4 This is a schematic diagram of the level change of the RZI encoding of the start bit of the data frame to the NRZ encoding in an embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of the structure of a counter module in an embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram of level changes of RZI encoding to NRZ encoding when the sending end sends a faster clock frequency in an embodiment of the present invention;

[0041] Figure 7 This is a schematic diagram of the level change of RZI encoding to NRZ encoding when the sending clock frequency of the sending end is too fast in an embodiment of the present invention;

[0042] Figure 8This is a schematic diagram of level changes of RZI encoding to NRZ encoding when the sending clock frequency of the sending end is slow in an embodiment of the present invention;

[0043] Fig. 9 This is a schematic diagram of the level change of RZI encoding to NRZ encoding when the sending clock frequency of the sending end is too slow in an embodiment of the present invention;

[0044] Fig.10 This is a schematic diagram of the structure of a decoding circuit and a UART interface module in an embodiment of the present invention;

[0045] Fig.11 The schematic diagram of a circuit for converting RZI encoding to NRZ encoding in an embodiment of the present invention is shown in FIG. DETAILED DESCRIPTION

[0046] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] like Figure 3 As shown, a method for converting RZI encoding to NRZ encoding provided by the present invention comprises the following steps:

[0048] S1: Calculate the bit width of the first receiving signal IrDA according to the baud rate of the signal sent by the transmitting end.

[0049] Since the infrared communication protocol using RZI encoding and the UART protocol using NRZ encoding are both asynchronous communication protocols, there is no synchronous clock or synchronization signal between the two. Therefore, both parties need to inform each other of the baud rate, i.e., the communication rate, in order to correctly receive the transmitted data. Among them, the first receiving signal IrDA indicates that the receiving end has collected the RZI-encoded infrared signal, which is converted to NRZ encoding and is hereinafter referred to as the second receiving signal RXD.

[0050] S2: Divide each bit width of the first received signal IrDA into N sampling points.

[0051] Wherein, N is a positive integer. Usually, signal sampling mostly adopts sixteen-fold oversampling or eight-fold oversampling. In this embodiment, signal sampling adopts sixteen-fold oversampling, so N=16.

[0052] Usually, RZI encoding uses 1 bit of low level to send the digital 1, and uses a high level pulse within 1 bit to send the digital 0. After dividing the 1 bit width into 16 sampling points (i.e., sampling point 0 to sampling point 15), the high level pulse is located in the middle of the 16 sampling points according to the different pulse widths. At the same time, in order to better detect the valid signal and ensure that the receiver can be more sensitive when detecting signal changes, the receiver usually uses a reverse signal to indicate the presence of infrared light, that is, the output of the receiver is high when there is no infrared light, and the output of the receiver is low when there is infrared light. Therefore, at the receiving end, the format of RZI encoding becomes that the digital 1 is represented by 1 bit of high level, and the digital 0 is represented by a low level pulse within 1 bit. Based on this, if Figure 4 As shown, in the process of converting RZI encoding to NRZ encoding, the first receiving signal IrDA is calculated from the falling edge of the low-level pulse of the frame start bit (i.e., digital 0) as the 0 sampling point start bit, that is, the width before the falling edge within 1 bit of the frame start bit is successively extended. This method facilitates the design of the decoding circuit and has no effect on the correctness of the decoding result.

[0053] S3: When the first receiving signal IrDA has a falling edge of a low level pulse, the sampling point counter is cleared and starts counting, and at the same time, the second receiving signal RXD is pulled down to a low level state, and the shielding signal SM is pulled down to a low level state.

[0054] In each data frame of the first receiving signal IrDA, the first bit is a low-level pulse of the frame start bit (i.e., digital 0). When the first receiving signal IrDA first has a falling edge of a low-level pulse, this position is the starting position of the 0 sampling point of the first bit. At this time, Figure 4 As shown, the system pulls down the second receiving signal RXD to a low level state, indicating that the second receiving signal RXD is at a low level in the first bit, that is, decoded as a digital 0.

[0055] The shielding signal SM is a reference signal set in this embodiment, which is used for logical judgment during subsequent signal conversion. At the same time, another function of the shielding signal SM is to maximize the baud rate tolerance and tolerance balance of the decoding conversion.

[0056] The sampling point counter is used to count each sampling point of 1 bit, so that the control system can control the width of 1 bit and send corresponding control signals at the corresponding sampling point position of 1 bit. Figure 5As shown, the sampling pulse of each sampling point needs to be provided by the baud rate counter. The baud rate counter divides the system clock clk according to the required baud rate to generate a sampling pulse and provides it to the sampling point counter. The baud rate counter acts as a pre-divider. Assuming that the system clock clk is 48MHz and the required baud rate is 1M, then the 48MHz needs to be pre-divided into 16MHz. Since one bit has 16 sampling points, 16MHz can be counted 16 times to get a 1M baud rate. Figure 5 In the above, the input signal rzi_in of the decoding circuit is the first receiving signal IrDA in the above steps, the first sampling point signal cnt7 is the end position signal of the 7 sampling points of each bit (that is, the starting position signal of the 8 sampling points), and the second sampling point signal cnt15 is the end position signal of the 15 sampling points of each bit (that is, the starting position signal of the 0 sampling point of the next bit); brp[7:0] is the frequency division configuration signal, and rst_n is the reset signal.

[0057] S4: When the first receiving signal IrDA ends at the middle sampling point of each bit, the sampling point counter generates a first sampling point signal cnt7 to control the shielding signal SM to be pulled high to a high level state.

[0058] In this embodiment, the middle sampling point is sampling point 7. Selecting the middle position of 1 bit, that is, the end of sampling point 7 and the start position of sampling point 8 to change the state of the shielding signal SM can not only be used for logical judgment of subsequent signals, but also maximize the baud rate tolerance and tolerance balance, as described below for details.

[0059] S5: When the first received signal IrDA is at the end position of the last sampling point of each bit, the sampling point counter generates a second sampling point signal cnt15.

[0060] In this embodiment, the last sampling point is sampling point 15. When the sampling point counter generates the second sampling point signal cnt15 at the end position of sampling point 15, it indicates that one bit conversion is completed and the next bit conversion starts. At this time, it is necessary to perform a logic judgment on the level states of the first receiving signal IrDA and the shielding signal SM at the starting position of sampling point 0 to determine the level change of the second receiving signal RXD at the next bit.

[0061] S6: according to the second sampling point signal cnt15, the sampling point counter is controlled to be cleared and restart counting; at the same time, at the first sampling point start bit of the next bit, the level state of the first receiving signal IrDA and the shielding signal SM is logically judged, and the level state of the second receiving signal RXD is adjusted according to the judgment result; specifically, the following three situations are included:

[0062] In the first case, when the first receiving signal IrDA is at a high level and the shielding signal SM is at a high level at the same time, the system pulls up the second receiving signal RXD to a high level state.

[0063] This situation belongs to the normal baud rate state, and the second receiving signal RXD is at a high level in the next bit, that is, decoded as digital 1.

[0064] In the second case, when the first receiving signal IrDA is at a high level and the shielding signal SM is at a low level, the system maintains or pulls down the second receiving signal RXD to a low level state.

[0065] This situation belongs to the transmission baud rate is fast, resulting in the 1-bit low pulse of the first receiving signal IrDA being sent in advance, making the shielding signal SM become a low level. Therefore, the second receiving signal RXD needs to be kept at a low level, that is, decoded as a digital 0.

[0066] In the third case, when the first receiving signal IrDA is at a low level and the shielding signal SM is at a low level, the system maintains or pulls down the second receiving signal RXD to a low level state.

[0067] This situation belongs to the slow transmission baud rate, which causes the 1-bit low pulse of the first receiving signal IrDA to be delayed, causing the shielding signal SM to become a low level. Therefore, the second receiving signal RXD needs to be kept at a low level, that is, decoded as a digital 0.

[0068] It should be noted that the first sampling point is the 0 sampling point. The above three situations are all for the state adjustment of the second receiving signal RXD. In the adjustment process of the above 0 sampling point start bit, except for the first receiving signal IrDA having a falling edge of a low level pulse, the shielding signal SM maintains the original level state. That is to say, in the data frame encoding conversion process of this embodiment, within the 0 sampling point to the 15 sampling points of each bit (including the frame start bit and the subsequent data bit), the shielding signal SM is pulled low only when the first receiving signal IrDA has a falling edge of a low level pulse, and at the end position of the 7 sampling points of each bit, the shielding signal SM is pulled high; at the end position of the 15 sampling points (i.e. the 0 sampling point position of the next bit), it is still necessary to determine the change of the shielding signal SM according to whether the first receiving signal IrDA has a falling edge of a low level pulse. If the falling edge of the low level pulse appears at this time, the shielding signal SM is pulled low, otherwise, the shielding signal SM maintains the original level state.

[0069] S7: After the system receives the second sampling point signal cnt15, within the first sampling point to the last sampling point of the next bit, if the first receiving signal IrDA has a falling edge of a low-level pulse, the system pulls down the shielding signal SM to a low-level state and pulls down the second receiving signal RXD to a low-level state; otherwise, proceed to the next step.

[0070] If the first receiving signal IrDA has a falling edge of a low level pulse at these two positions within the range of sampling point 0 to sampling point 15 of the next bit, including the starting position of sampling point 0 and the ending position of sampling point 15, it is a normal situation. The design of step S7 is also to deal with the situation that when the sending end sends a clock frequency that is fast or slow, in addition to the falling edge of the frame start bit of a data frame that will appear at sampling point 0, the falling edge of the subsequent data bits may appear at a non-0 sampling point in advance or lag. Therefore, the conversion of the subsequent data bits of a data frame does not adopt step S3, but adopts step S7. If the first receiving signal IrDA does not have a falling edge of a low level pulse at these two positions within the range of sampling point 0 to sampling point 15 of the next bit, step S7 is not processed and the next step is directly transferred.

[0071] S8: Go to step S4, and execute steps S4 to S7 in a loop until a data frame decoding conversion is completed.

[0072] S9: Go to step S3, and execute steps S3 to S8 in a loop until the decoding and conversion of the received data is completed.

[0073] In each data frame conversion of the first receiving signal IrDA, frame synchronization is performed with the falling edge of the low level pulse of the frame start bit as the 0 sampling point (ie the first sampling point) as the starting position, which is step S3.

[0074] The above is a detailed description of the conversion method of RZI encoding to NRZ encoding provided by the embodiment of the present invention, wherein steps S1 to S2 are to calculate and divide each bit width of the received signal; step S3 is to convert the frame start bit of a data frame of the received data signal, and S4 to S8 are to convert each bit data subsequent to the frame start bit of a data frame of the received data signal; steps S3 to S9 are to convert all data frames of the received data signal. Below, this embodiment analyzes the four situations of fast, too fast, slow and too slow sending clock frequencies at the transmitting end during the encoding conversion process using the above conversion method, and explains the baud rate tolerance and tolerance balance of the conversion method.

[0075] First, when the sending end sends a faster clock frequency, such as Figure 6As shown in the figure, the starting position of the next bit of the first receiving signal IrDA does not appear at the ideal position, i.e., the 0 sampling point of the next bit, but appears in advance after the 8 sampling points of the previous bit, i.e., a small amount of leftward deviation occurs. In this case, when the first receiving signal IrDA has a falling edge between the 8th and 15th sampling points of the previous bit, the shielding signal SM is pulled low, and the second receiving signal RXD is pulled low or maintained at a low level until the end position of the 15th sampling point of the previous bit. The system adjusts the level state of the second receiving signal RXD based on the logical judgment of the level state of the first receiving signal IrDA and the shielding signal SM; Figure 6 In the example, the first receiving signal IrDA is at a high level and the shielding signal SM is at a low level. Therefore, the system keeps the second receiving signal RXD at a low level, so that the next bit can be decoded normally as a digital 0, ensuring the correctness of the decoding conversion. In this embodiment, the shielding signal SM is used as a reference signal for logical judgment of subsequent signal conversion. While ensuring the correctness of decoding, the baud rate tolerance and tolerance balance of the decoding conversion can be maximized. At this time, the maximum baud rate tolerance is (8 / 16) / 9=5.55%, which is significantly higher than the tolerance requirements of the infrared protocol at different baud rates shown in the third column of Table 1.

[0076] Table 1

[0077]

[0078] Secondly, when the sending clock frequency is too fast, such as Figure 7 As shown, the start bit of the next bit of the first receiving signal IrDA does not appear at the ideal position, i.e., the 0 sampling point of the next bit, but appears in advance before the 8 sampling points of the previous bit, i.e., a large amount of leftward deviation occurs. In this case, if the shielding signal SM is in a low level state before the 8 sampling points of the previous bit, when the first receiving signal IrDA has a falling edge of a low level pulse before the 8 sampling points of the previous bit, it still maintains a low level state until the start bit of the 8 sampling points is pulled up to a high level; therefore, at the end position of the 15 sampling points of the previous bit, the system makes a logical judgment on the level states of the first receiving signal IrDA and the shielding signal SM to adjust the level state of the second receiving signal RXD, and an error will occur. For example, in Figure 7In the example, the shielding signal SM is at a high level, and the first receiving signal IrDA is also at a high level, so that the second receiving signal RXD is pulled high (that is, the 0 sampling point of the next bit is at a high level), which causes the original digital 0 of the next bit to be incorrectly decoded as digital 1. It can be seen that when the sending clock frequency of the transmitter is too fast, the start position of the next bit cannot exceed the 8 sampling point position of the previous bit, that is, the maximum baud rate tolerance cannot exceed 5.55%.

[0079] Third, when the sending end sends a slow clock frequency, such as Figure 8 As shown, the start position of the next bit of the first receiving signal IrDA does not appear at the ideal position, i.e., the 0 sampling point of the bit, but appears lagging before the 8 sampling points of the bit, i.e., a small amount of deviation to the right occurs. In this case, when the first receiving signal IrDA has a falling edge before the 8 sampling points of the bit, the shielding signal SM is pulled low, and the second receiving signal RXD is pulled low or maintained at a low level state (at this time, the digital 0 of the bit can be correctly converted because RXD samples the correct signal of more than 8 sampling points), and the shielding signal SM is pulled high at the start position of the 8 sampling points; until the end position of the 15 sampling points of the bit, the system adjusts the level state of the second receiving signal RXD according to the logical judgment of the level state of the first receiving signal IrDA and the shielding signal SM; Figure 8 In the example, the first receiving signal IrDA is at a high level and the shielding signal SM is at a high level. Therefore, the system pulls up the second receiving signal RXD to a high level state, so that the next bit of the bit can be decoded normally as a digital 1, ensuring the correctness of the decoding conversion. At this time, the maximum baud rate tolerance is still (8 / 16) / 9=5.55%.

[0080] Fourth, when the sending clock frequency is too slow, such as Fig. 9 As shown, the start bit of the next bit of the first receiving signal IrDA does not appear at the ideal position, i.e., the 0 sampling point of the bit, but appears after the 8 sampling points of the bit, i.e., a large amount of deviation to the right occurs. In this case, when the first receiving signal IrDA has a falling edge after the 8 sampling points of the bit, the shielding signal SM is pulled low, and the second receiving signal RXD is pulled low at the same time (at this time, the digital 0 of the bit cannot be correctly converted because RXD samples the correct signal of less than 8 sampling points). Until the end position of the 15 sampling points of the bit, the system adjusts the level state of the second receiving signal RXD according to the logical judgment of the level state of the first receiving signal IrDA and the shielding signal SM, and an error will occur. For example, in Fig. 9In the example, the shielding signal SM is at a low level, and the first receiving signal IrDA is at a high level, so that the second receiving signal RXD is pulled down to a low level (that is, the 0 sampling point of the next bit of the bit is at a low level), which causes the original digital 1 of the next bit of the bit to be incorrectly decoded as a digital 0. It can be seen that when the sending clock frequency of the transmitting end is too slow, the start position of a bit cannot exceed the 8 sampling point position of the bit, that is, the maximum baud rate tolerance cannot exceed 5.55%.

[0081] From the above analysis, it can be seen that the RZI encoding to NRZ encoding conversion method provided in this embodiment can achieve a maximum baud rate tolerance of ±5.55%, and since the falling edge of the first receiving signal IrDA is used to change the level state of the shielding signal SM and the second receiving signal RXD, when the low-level pulse used by the first receiving signal IrDA becomes narrower, the consistency of the baud rate deviation tolerance can also be achieved, and there is no effect on data reception.

[0082] Based on the above RZI code to NRZ code conversion method, this embodiment correspondingly provides a RZI code to NRZ code decoding circuit, such as Fig.10 As shown, the decoding circuit RZI2NRZ and the corresponding encoding circuit NRZ2RZI are used together as the front module of the controller UART interface module, which can be integrated in any UART circuit of the application system, and cooperate with the infrared receiver and the infrared transmitter to realize the decoding function of RZI encoding to NRZ encoding in the application system. Among them, the input signal of the decoding circuit RZI2NRZ is the first receiving signal IrDA_IN encoded by the infrared protocol RZI, and after conversion by the decoding circuit RZI2NRZ, the second receiving signal RXD encoded by the UART protocol NRZ is output, which is provided to the controller UART interface module for digital communication. It should be noted that the expression of the input signal (i.e., the first receiving signal IrDA_IN) of the decoding circuit RZI2NRZ is that the infrared receiver at the receiving end uses the reverse level opposite to the transmitting end to represent the infrared signal and decode it. For example, the transmitting end uses a high-level pulse to represent the number 0, while the receiving end uses a low-level pulse to represent the number 0. In addition, since the encoding circuit NRZ2RZI is relatively easy to implement, this patent does not describe the circuit in detail.

[0083] In one embodiment of the present invention, Fig.11 As shown, a decoding circuit for converting RZI encoding to NRZ encoding includes an edge detection module M1, a register module M2, and a counter module ( Fig.11 Not shown, see Figure 5), and a first AND gate A1, a second AND gate A2, a third AND gate A3, a fourth AND gate A4 and a fifth AND gate A5, and a first OR gate OR1, a second OR gate OR2, a first inverter N1 and a second inverter N2.

[0084] The edge detection module M1 is used to detect the falling edge of the input first receiving signal IrDA_IN. When the first receiving signal IrDA_IN has a falling edge of a low level pulse, the edge detection module M1 outputs a high level pulse (pulse width is one clock cycle) signal to the relevant logic circuit.

[0085] The register module M2 is used to generate and output a shielding signal SM and a second receiving signal RXD according to a control signal output by a related logic circuit;

[0086] The counter module includes a baud rate counter and a sampling point counter. The baud rate counter divides the system clock clk according to the baud rate of the transmitted signal to generate a sampling pulse and provide it to the sampling point counter; the sampling point counter is used to count each sampling point in each bit of the first received signal IrDA_IN, and generate a first sampling point signal cnt7 and a second sampling point signal cnt15 in each bit to provide them to the relevant logic circuit.

[0087] The first input terminal in1 of the first AND gate A1 is connected to the input terminal of the second sampling point signal cnt15, and the second input terminal in2 is connected to the input terminal of the first receiving signal IrDA_IN; the output terminal of the first AND gate A1 is connected to the first input terminal in1 of the second AND gate A2, and the second input terminal in2 of the second AND gate A2 is connected to the output terminal (sir_mask) of the shielding signal SM of the register module M2. The logic circuit composed of the first AND gate A1 and the second AND gate A2 and the subsequent first OR gate OR1 and the fifth AND gate A5 is used to control the input of the second sampling point signal cnt15. Only when the first receiving signal IrDA_IN is at a high level and the shielding signal SM is also at a high level at the same time, the second receiving signal RXD output by the register module M2 becomes a high level state, thereby realizing the relevant logic functions of step S6 in the conversion method.

[0088] The first input terminal in1 of the first OR gate OR1 is connected to the output terminal of the second AND gate A2, the second input terminal in2 is connected to the second receiving signal RXD output terminal (nrz_out) of the register module M2, and the output terminal of the first OR gate OR1 is connected to the second input terminal in2 of the fifth AND gate A5; the output terminal of the edge detection module M1 is connected to the first input terminal in1 of the fifth AND gate A5 through the second inverter N2; the output terminal of the fifth AND gate A5 is connected to the first input terminal (nrz_out_pre) of the register module M2. The logic circuit composed of the first OR gate OR1, the fifth AND gate A5 and the register module M2 is used to store the falling edge signal of the first receiving signal IrDA_IN and maintain the second receiving signal RXD in a low level state; when the edge detection module M1 outputs a high level pulse signal, the second receiving signal RXD output by the register module M2 is changed to a low level state through the logic circuit composed of the second inverter N2, the fifth AND gate A5 and the register module M2. At the same time, the second receiving signal RXD is fed back to the second input terminal in2 of the first OR gate OR1, and then passes through the second input terminal in2 of the fifth AND gate A5 and the register module M2, so that the second receiving signal RXD maintains a low level state.

[0089] The input end of the first inverter N1 is connected to the output end (sir_mask) of the shielding signal SM of the register module M2, and the output end is connected to the first input end in1 of the third AND gate A3; the second input end in2 of the third AND gate A3 is connected to the input end of the first sampling point signal cnt7, and the output end of the third AND gate A3 is connected to the first input end in1 of the second OR gate OR2; the output end of the edge detection module M1 is connected to the first input end in1 of the fourth AND gate A4 through the second inverter N2, the output end of the shielding signal SM of the register module M2 (sir_mask) is connected to the second input end in2 of the fourth AND gate A4, and the output end of the fourth AND gate A4 is connected to the second input end in2 of the second OR gate OR2; the output end of the second OR gate OR2 is connected to the second input end (sir_mask_pre) of the register module M2. The logic circuit composed of the first inverter N1, the second AND gate A2, the third AND gate A3, the fourth AND gate A4 and the second OR gate OR2 is used to control the level state of the shielding signal SM output by the register module M2. When the edge detection module M1 outputs a high level pulse signal, the shielding signal SM output by the register module M2 becomes low level through the fourth AND gate A4 and the second OR gate OR2. At the same time, the shielding signal SM is fed back to the second input terminal in2 of the fourth AND gate A4, and then through the second input terminal in2 of the second OR gate OR2 and the register module M2, so that the shielding signal SM remains in a low level state. Until the first sampling point signal cnt7 appears, the shielding signal SM becomes high level through the third AND gate A3 and the first input terminal in1 of the second OR gate OR2 and the register module M2.

[0090] In one embodiment of the present invention, the decoding circuit also includes a start bit synchronization module for detecting the data frame of the first received signal IrDA_IN. When a low-level signal of the start bit of a frame of data signal is detected, a reset signal rst_n is output to reset the D flip-flops in each module to an initial value, so that each frame of data is resynchronized and sampled starting from the start bit, thereby realizing the relevant logical functions of steps S3, S8 and S9 in the conversion method.

[0091] Based on the above RZI encoding to NRZ encoding decoding circuit, this embodiment further provides an integrated circuit chip, which includes the above RZI encoding to NRZ encoding decoding circuit. In one embodiment of the present invention, the decoding circuit can be integrated with the corresponding encoding circuit and the UART interface module to provide the application system with real-time conversion between RZI encoding signals and NRZ encoding signals, and realize the digital communication function of different encoding signals in the application system. The specific structure of the RZI encoding to NRZ encoding decoding circuit in the integrated circuit chip will not be described in detail here.

[0092] To sum up, compared with the prior art, the conversion method and decoding circuit of RZI encoding to NRZ encoding provided by the present invention realizes the real-time conversion of RZI encoded signals to NRZ encoded signals by adopting digital circuits and introducing a technical solution of shielding signals participating in logical judgment. At the same time, the conversion method can be compatible with the requirements of infrared protocols for different pulse widths, and has the beneficial effect of high tolerance for baud rate. It is suitable for application scenarios that need to convert RZI encoding to NRZ encoding, and the decoding circuit can be easily integrated in any UART circuit of the application system to meet the requirements of digital communication systems.

[0093] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0094] The above is a detailed description of a RZI coding to NRZ coding conversion method, decoding circuit, and chip provided by the present invention. For a person skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A method for converting RZI coding to NRZ coding, characterized in that The steps include: (1) calculating the bit width of the first received signal according to the baud rate of the signal sent by the transmitting end; (2) dividing each bit width of the first received signal into N sampling points, where N is a positive integer; (3) When the first receiving signal has a falling edge of a low-level pulse, the sampling point counter is cleared and starts counting, and at the same time, the second receiving signal is pulled down to a low-level state, and the shielding signal is pulled down to a low-level state; (4) when the first received signal ends at the middle sampling point of each bit, the sampling point counter generates a first sampling point signal to control the shielding signal to be pulled high to a high level state; (5) when the first received signal is at the end position of the last sampling point of each bit, the sampling point counter generates a second sampling point signal; (6) according to the second sampling point signal, control the sampling point counter to be cleared and restart counting; at the same time, at the first sampling point start bit of the next bit, perform a logical judgment on the level states of the first received signal and the shielding signal, and adjust the level state of the second received signal according to the judgment result; specifically, the following three situations are included: When the first receiving signal is at a high level and the shielding signal is at a high level at the same time, maintaining or pulling up the second receiving signal to a high level state; When the first receiving signal is at a high level and the shielding signal is at a low level, maintaining or pulling down the second receiving signal to a low level state; When the first receiving signal is at a low level and the shielding signal is at a low level, maintaining or pulling down the second receiving signal to a low level state; (7) After receiving the second sampling point signal, within the period from the first sampling point to the last sampling point of the next bit, if the first received signal has a falling edge of a low level pulse, pull the shielding signal to a low level state and pull the second received signal to a low level state; otherwise, proceed to the next step; (8) Go to step (4), and execute steps (4) to (7) in a loop until a data frame decoding conversion is completed; (9) Go to step (3) and execute steps (3) to (8) in a loop until the decoding and conversion of the received data is completed.

2. The method for converting RZI encoding to NRZ encoding as claimed in claim 1, characterized in that In step (3), In each data frame conversion of the first received signal, frame synchronization is performed with the falling edge of the low-level pulse of the frame start bit as the starting position of the first sampling point.

3. The method for converting RZI encoding to NRZ encoding as claimed in claim 1, characterized in that In step (3), The input signal of the sampling point counter is a sampling pulse of each sampling point, and the sampling pulse is provided by a baud rate counter.

4. The method for converting RZI encoding to NRZ encoding as claimed in claim 1, characterized in that: The maximum baud rate tolerance of the conversion method is ±5.55%.

5. A decoding circuit for converting RZI code to NRZ code, implemented based on the conversion method for converting RZI code to NRZ code as claimed in any one of claims 1 to 4, characterized in that It includes an edge detection module, a register module, a counter module, and a first AND gate, a second AND gate, a third AND gate, a fourth AND gate and a fifth AND gate, and a first OR gate, a second OR gate, a first inverter and a second inverter; wherein, The edge detection module is used to detect the falling edge of the input first receiving signal. When the first receiving signal has a falling edge of a low level pulse, the edge detection module outputs a high level pulse signal to provide to the relevant logic circuit; The register module is used to generate and output a shielding signal and a second receiving signal according to a control signal provided by a related logic circuit; The counter module includes a baud rate counter and a sampling point counter. The baud rate counter is used to generate a sampling pulse and provide it to the sampling point counter. The sampling point counter is used to count each sampling point in each bit of the first received signal, and generate and output a first sampling point signal and a second sampling point signal in each bit and provide them to a related logic circuit.

6. The RZI encoding to NRZ encoding decoding circuit as claimed in claim 5, characterized in that: The first input end of the first AND gate is connected to the input end of the two sampling point signals, and the second input end is connected to the input end of the first receiving signal; the output end of the first AND gate is connected to the first input end of the second AND gate, and the second input end of the second AND gate is connected to the output end of the shielding signal of the register module.

7. The RZI-to-NRZ decoding circuit according to claim 5, characterized in that: The first input end of the first OR gate is connected to the output end of the second AND gate, the second input end is connected to the output end of the second receiving signal of the register module, the output end of the first OR gate is connected to the second input end of the fifth AND gate; the output end of the edge detection module is connected to the first input end of the fifth AND gate through the second inverter; the output end of the fifth AND gate is connected to the first input end of the register module.

8. The RZI encoding to NRZ encoding decoding circuit as claimed in claim 5, characterized in that: The input end of the first inverter is connected to the output end of the shielding signal of the register module, and the output end is connected to the first input end of the third AND gate; the second input end of the third AND gate is connected to the input end of the first sampling point signal, and the output end of the third AND gate is connected to the first input end of the second OR gate; the output end of the edge detection module is connected to the first input end of the fourth AND gate through the second inverter, the output end of the shielding signal of the register module is connected to the second input end of the fourth AND gate, and the output end of the fourth AND gate is connected to the second input end of the second OR gate; the output end of the second OR gate is connected to the second input end of the register module.

9. The RZI encoding to NRZ encoding decoding circuit as claimed in claim 5, characterized in that: The decoding circuit also includes a start bit synchronization module, which is used to detect the data frame of the first received signal. When a low-level signal of the start bit of the data frame is detected, a reset signal is output to reset the D flip-flops in each module to an initial value, so that each data frame is resynchronized from the start bit.

10. An integrated circuit chip, characterized in that A decoding circuit for converting RZI encoding to NRZ encoding comprising any one of claims 5 to 9.

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