Delay control system and method for radio frequency signal sampling conversion optical transmission equipment

Abstract

The invention relates to the technical field of optical fiber communication, in particular to a delay control system and method for radio frequency signal sampling conversion optical transmission equipment, and the system comprises a transmitter and a receiver, the transmitter comprises a first switch, an ADC module, a first FPGA module, a first optical module, a first frequency synthesizer synchronization module, a first wavelength division multiplexer and a first delay measurement module, the receiver comprises a second wavelength division multiplexer, a second optical module, a second FPGA module, a DAC module, a power divider, a second switch, a synchronous detection module, a second frequency synthesizer synchronization module and a second delay measurement module. The FIFO data storage position of the second FPGA module is adjusted through the second FPGA module according to the measured delay value by taking the system delay value set by the receiver as the reference, so that the relationship between the transmission delay of all channels and the time of the transmitter is kept unchanged, and after the adjustment is finished, the first FPGA module and the second FPGA module control the first switch and the second switch to switch on the radio frequency input and output, so that the transmission delay of all the channels can be controlled to be switched on. And transmitting the radio frequency signal.

Description

Technical Field

[0001] The present invention relates to the field of optical fiber communication technology, and in particular to a delay control system and method for optical transmission equipment used for sampling and converting radio frequency signals. Background Art

[0002] Optical fiber transmission can be divided into two modes: analog transmission and data transmission. The types of signals transmitted in the optical fiber are different. The analog transmission mode transmits analog modulated optical signals, while the data transmission mode transmits optical signals modulated by "0" and "1".

[0003] For analog transmission, the RF signal is converted into an optical signal by directly modulating the intensity of the laser at the transmitting end, and then transmitted to the receiver through the optical fiber. The photoelectric detector of the receiver then converts the input optical signal into an analog electrical signal for output. Signal processing and transmission are both implemented by hardware, and no software is used to process the signal. The transmission delay of the signal is determined by the physical characteristics of the hardware, and the transmission delay stability of the analog signal can reach the ps level.

[0004] For data transmission, the analog signal is first converted into a digital signal at the transmitter, and then converted into a "0" or "1" data signal. After multiplexing, the optical module converts the analog signal into a data optical signal for transmission. The receiver converts the input data optical signal into a data electrical signal, and restores the analog signal through data demultiplexing and digital / analog conversion.

[0005] The signal transmission process goes through analog / digital conversion, data multiplexing / demultiplexing, digital / analog conversion and other processing processes, including digital up / down conversion, interpolation filtering, JESD204B encoding / decoding, time stamp data insertion, multi-channel high-speed data multiplexing / demultiplexing, data line encoding / decoding and other operations. If no corrective measures are taken, the transmission delay stability is tens of ns, which is insufficient. If Beidou satellite navigation signals are used for synchronization, the transmission delay stability is about 3ns, which is equivalent to a distance accuracy of about 1 meter in a vacuum. In applications such as positioning, the higher the accuracy requirement, the better. Summary of the invention

[0006] The purpose of the present invention is to provide a delay control system and method for radio frequency signal sampling and conversion optical transmission equipment, aiming to solve the problem of insufficient transmission delay stability of existing radio frequency signals during data optical transmission.

[0007] To achieve the above-mentioned purpose, in a first aspect, the present invention provides a delay control system for radio frequency signal sampling and conversion optical transmission equipment, comprising a transmitter and a receiver, wherein the transmitter comprises a first switch, an ADC module, a first FPGA module, a first optical module, a first frequency synthesis synchronization module, a first wavelength division multiplexer and a first delay measurement module, and the receiver comprises a second wavelength division multiplexer, a second optical module, a second FPGA module, a DAC module, a power divider, a second switch, a synchronization detection module, a second frequency synthesis synchronization module and a second delay measurement module;

[0008] The first switch is respectively connected to the first frequency synthesis synchronization module, the ADC module and the first FPGA module, the ADC module is respectively connected to the first FPGA module and the first frequency synthesis synchronization module, the first FPGA module is respectively connected to the first optical module, the first frequency synthesis synchronization module and the first delay measurement module, the first wavelength division multiplexer is respectively connected to the first optical module, the first delay measurement module and the second wavelength division multiplexer, the first frequency synthesis synchronization module and the first delay measurement module are connected, the second wavelength division multiplexer is respectively connected to the second optical module and the second delay measurement module, the second FPGA module is respectively connected to the second optical module, the DAC module, the second switch, the synchronization detection module, the second frequency synthesis synchronization module and the second delay measurement module, the DAC module is respectively connected to the power divider and the second frequency synthesis synchronization module, the power divider is respectively connected to the second switch and the synchronization detection module, and the second frequency synthesis synchronization module is connected to the second delay measurement module.

[0009] In a second aspect, the present invention further provides a method for delay control of radio frequency signal sampling conversion optical transmission equipment, which is applied to the delay control system for radio frequency signal sampling conversion optical transmission equipment as described in the first aspect above, comprising the following steps:

[0010] Measure the optical cable transmission time to obtain the optical cable delay;

[0011] Measure transmitter trigger delay time;

[0012] Measure the receiver synchronization modulation pulse delay;

[0013] Calculate the delay difference between the trigger delay time and the synchronous modulation pulse delay;

[0014] adjusting a FIFO data storage location based on the delay difference;

[0015] Switching the first switch and the second switch connects the RF input and output to transmit the RF signal.

[0016] The specific method of measuring the optical cable transmission time to obtain the optical cable delay is as follows:

[0017] The external input synchronization signal is shaped and processed by the second FPGA module to obtain a synchronization pulse, and is output to the second delay measurement module;

[0018] The second delay measurement module synchronously multiplexes the synchronization pulses to convert them into optical signals, which are transmitted to the transmitter via the first wavelength division multiplexer, the second wavelength division multiplexer and the optical cable;

[0019] The optical signal is restored to a synchronization pulse through the first delay measurement module and is transmitted back to the receiver. The second delay measurement module calculates the synchronization pulse and the transmission time of the restored synchronization pulse to obtain the optical cable delay.

[0020] The specific method of measuring the synchronous modulation pulse delay of the receiver is as follows:

[0021] The synchronous modulation signal is sampled and processed at high speed by the ADC module, and then transmitted by the first FPGA module, the first optical module, the first wavelength division multiplexer, the second wavelength division multiplexer, the second optical module, and the second FPGA module and processed by the DAC module. The restored synchronous modulation signal is recovered by the second synchronization detection module to restore the synchronization pulse, and the second FPGA module calculates the delay time between the synchronization pulse and the synchronization signal.

[0022] The optical cable delay includes the optical cable transmission time and the processing time of the first delay measurement module and the second delay measurement module. The processing time of the first delay measurement module and the second delay measurement module is 200ns, and the optical cable transmission time is about 5us / km.

[0023] The present invention is a delay control system for radio frequency signal sampling and conversion optical transmission equipment, wherein the ADCLK of the ADC module is connected to the sampling clock output of the first frequency synthesis synchronization module, CH1 is connected to the external radio frequency input CH1, CH2 is connected to the output of the first switch C, the JESD data is connected to the first FPGA module, the CLK4 clock of the first FPGA module is connected to the output of the first frequency synthesis synchronization module, ctrl1 is connected to the control input of the first switch C, GTX1 is connected to the high-speed serial data electrical signal input of the first optical module, JESD is connected to the data output of the ADC module, SYN2R is connected to the output of the first delay measurement module, TRIG1 is connected to the external main trigger input, and TRIG2 is connected to the first The trigger signal input of the delay measurement module and the first frequency synthesis synchronization module, the GTX1 of the first optical module is connected to the high-speed serial data output of the first FPGA module, the optical output is connected to the λ3 and λ4 inputs of the first wavelength division multiplexer, the λ1 and λ2 interfaces of the first wavelength division multiplexer are connected to the optical interface of the first delay measurement module, the λ3 and λ4 interfaces are connected to the optical output of the first optical module, the COM port is connected to the transmission optical cable, the optical interface of the first delay measurement module is connected to the λ1 and λ2 interfaces of the first wavelength division multiplexer, RCLK is connected to the recovered clock input of the first frequency synthesis synchronization module, the SYNA pulse is connected to the output of the first frequency synthesis synchronization module, and the SYN2R synchronization signal is locally looped back and connected to the first FPGA module and the first frequency synthesis synchronization module input, the ADCLK of the first frequency synthesis synchronization module is connected to the ADC module sampling clock input, CLK4 is connected to the first FPGA module clock input, TRIG2 trigger input is connected to the first FPGA trigger output, RCLK is connected to the first delay measurement module recovery clock output, SYN2R is connected to the first delay measurement module output, SYNA synchronous modulation signal output is connected to the first switch B input, SYNA pulse is connected to the delay measurement input, the A interface of the first switch is connected to the external RF input CH2, the B interface is connected to the first frequency synthesis synchronization module SYNA synchronous modulation signal output, the ctrl1 interface is connected to the first FPGA module control output, and the first The COM interface of the second wavelength division multiplexer is connected to the transmission optical cable, the λ3 and λ4 interfaces are connected to the optical port of the second optical module, the λ1 and λ2 interfaces are connected to the optical port of the second delay measurement module, the optical port of the second optical module is connected to the λ3 and λ4 interfaces of the wavelength division multiplexer, GTX2 is connected to the high-speed serial data input of the second FPGA module, the CLK3 of the second FPGA module is connected to the clock input and output of the second frequency synthesis synchronization module, ctrl2 is connected to the second switch control input, GTX2 is connected to the electrical signal of the second optical module, JESD is connected to the sampling data input of the DAC module, SYN1 is connected to the external synchronization signal input, SYN2 and SYN2R are connected to the synchronization signal input and output of the second delay measurement module,The SYNAR pulse is connected to the synchronous modulation signal output of the synchronous detection module, TRIG2R is connected to the output of the second delay measurement module, the CH1 of the DAC module is connected to the external user RF signal output, CH2 is connected to the power divider input, DACclk is connected to the second frequency synthesis synchronization module conversion clock output, JESD is connected to the second FPGA module sampling data output, the power divider input is connected to the DAC module CH2 output, and the two outputs are respectively connected to the second switch A input and the synchronous detection module input, the switch input input is connected to the power divider output, and the output is connected to the external CH2 RF signal output, ctrl2 is connected to the second FPGA module control output, and the synchronous The input of the step detection module is connected to the output of the power divider, and the output is connected to the SYNAR pulse input of the second FPGA module. The CLK1 of the second frequency synthesis synchronization module is connected to the external reference clock input, CLK2 is connected to the clock input of the second delay measurement module, CLK3 is connected to the clock input and output of the second FPGA module, DACclk is connected to the DAC conversion clock input, CLK2 of the second delay measurement module is connected to the synchronization clock output of the second frequency synthesis synchronization module, SYN2 and SYN2R are connected to the synchronization signal output and input of the second FPGA module, TRIG2R output is connected to the trigger signal input of the second FPGA module, and the optical interface is connected to the λ1 and λ2 interfaces of the second wavelength division multiplexer;

[0024] The ADC module is a dual-channel TXADC with a resolution of 14 bits, a maximum sampling frequency of 1.25 GHz, an analog input full power bandwidth of 2 GHz, and a JESD204B (subtype) encoded serial digital output. The main chips of the first FPGA module and the second FPGA module are XC7K325T-2FFG900. The first optical module is a dual-light emitting module with a wavelength of DWDM CH32, CH33 (1551.72 nm, 1550.92 nm), an output optical power of 0 dBm to 2 dBm, a transmission data rate of 10 Gbit / s, and a maximum transmission distance of 100 km. The second optical module is a dual-receiving optical module with a wavelength of DWDM CH32, CH33 (1551.72nm, 1550.92nm), receiving sensitivity ≤-24dBm, saturated receiving power ≥0dBm, transmission data rate 10Gbit / s, maximum transmission distance 100km, the first wavelength division multiplexer and the second wavelength division multiplexer are 4-channel DWDM wavelength division multiplexers, the wavelengths are CH32\CH33\CH34\CH35, the insertion loss ≤1dB, the first delay measurement module and the second delay measurement module The block is a 16-bit multiplexing / demultiplexing low-jitter transmission delay measurement module with a measurement accuracy of 200ps, a wavelength of DWDM CH34, CH35 (1550.12nm, 1549.32nm), an output optical power of 0dBm~2dBm, a transmission rate of 1.25Gbit / s, a receiving sensitivity ≤-36dBm, a saturated receiving power ≥0dBm, a maximum transmission distance of 120km, and the first frequency synthesis synchronization module and the second frequency synthesis synchronization module are ZERO DELAY phase-locked module, reference frequency input range is DC ~ 250MHHz, input level is CMOS, LVDS or LVPECL level, output is CMOS or LVPECL level, output frequency range is 0 ~ 2.4GHz, output channel number is 12, output additional jitter ≤ 225fs, output delay error between channels ≤ 16ps, the DAC module is a dual-channel TxDAC, resolution 16bit, conversion rate 1.6Gbit / s, digital interpolation filter none / 2X / 4X / 8X / 16V optional, TxDAC conversion inherent delay difference ≤ 2 DACCLK cycles, the synchronous detection module is a microwave detector, the input frequency range is 0.01-4GHz, the in-band fluctuation is ≤±0.3dB, the low-level sensitivity (at -30dBm) is ≥0.5mV, the power divider operates in a frequency range of 0-6GHz, the insertion loss is 3.5dB, the first switch and the second switch are single-pole double-throw non-reflective microwave switch circuits, the on / off rate is 5n, the operating frequency is DC-12GHz, the insertion loss is 1.4dB, the isolation is 57dB, the 1dB compression point is +30dBm, and the control interface level is TTL / PLECL;

[0025] The system adjusts the FIFO data storage position of the second FPGA module based on the measured delay value and the system delay value set by the receiver through the second FPGA module, so that the transmission delay of all channels remains unchanged with the time relationship of the transmitter, that is, after the delay is adjusted, the mutual time relationship of the TRIG signals of each channel remains unchanged with the time relationship of the TRIG signal of the transmitting station. After the adjustment, the first FPGA module and the second FPGA module control the first switch and the second switch to connect the RF input and output to transmit the RF signal. The system uses the synchronous modulation signal sent during the main trigger period to measure and adjust the RF transmission delay, which does not affect the transmission of the echo RF signal, and solves the problem of insufficient transmission delay stability of the existing RF signal during data optical transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 It is a connection diagram of a delay control system of an optical transmission device for sampling and converting radio frequency signals provided by the present invention.

[0028] Figure 2 This is a schematic diagram of the timing of SYNA pulse generation.

[0029] Figure 3 This is a schematic diagram of delay measurement and adjustment.

[0030] Figure 4 The present invention provides a flow chart of a delay control method for radio frequency signal sampling and conversion optical transmission equipment.

[0031] Figure 5 This is a schematic diagram of instance delay measurement adjustment.

[0032] In the figure: 1-transmitter, 2-receiver, 3-first switch, 4-ADC module, 5-first FPGA module, 6-first optical module, 7-first frequency synthesis synchronization module, 8-first wavelength division multiplexer, 9-first delay measurement module, 10-second wavelength division multiplexer, 11-second optical module, 12-second FPGA module, 13-DAC module, 14-power divider, 15-second switch, 16-synchronization detection module, 17-second frequency synthesis synchronization module, 18-second delay measurement module. DETAILED DESCRIPTION

[0033] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0034] See also Figure 1 In a first aspect, the present invention provides a delay control system for radio frequency signal sampling and conversion optical transmission equipment, comprising a transmitter 1 and a receiver 2, wherein the transmitter 1 comprises a first switch 3 (switch 1), an ADC module 4, a first FPGA module 5 (FPGA module 1), a first optical module 6 (optical module 1), a first frequency synthesis synchronization module 7 (frequency synthesis synchronization module 1), a first wavelength division multiplexer 8 (wavelength division multiplexer 1) and a first delay measurement module 9 (delay measurement module 1), and the receiver 2 comprises a second wavelength division multiplexer 10 (wavelength division multiplexer 2), a second optical module 11 (optical module 2), a second FPGA module 12 (FPGA module 2), a DAC module 13, a power divider 14, a second switch 15 (switch 2), a synchronization detection module 16, a second frequency synthesis synchronization module 17 (frequency synthesis synchronization module 2) and a second delay measurement module 18 (delay measurement module 2); the first switch 3 is respectively connected to the first frequency synthesis synchronization module 7, the ADC module 4 and the first FPGA module 5, and the ADC module 4 is respectively connected to the first FPGA Module 5 is connected to the first frequency synthesis synchronization module 7, the first FPGA module 5 is respectively connected to the first optical module 6, the first frequency synthesis synchronization module 7 and the first delay measurement module 9, the first wavelength division multiplexer 8 is respectively connected to the first optical module 6, the first delay measurement module 9 and the second wavelength division multiplexer 10, the first frequency synthesis synchronization module 7 is connected to the first delay measurement module 9, the second wavelength division multiplexer 10 is respectively connected to the second optical module 11 and the second delay measurement module 18, the second FPGA module 12 is respectively connected to the second optical module 11, the DAC module 13, the second switch 15, the synchronization detection module 16, the second frequency synthesis synchronization module 17 and the second delay measurement module 18, the DAC module 13 is respectively connected to the power divider 14 and the second frequency synthesis synchronization module 17, the power divider 14 is respectively connected to the second switch 15 and the synchronization detection module 16, the second frequency synthesis synchronization module 17 and the second delay measurement module 18 are connected.

[0035] In an embodiment of the present invention, ADCLK of the ADC module 4 is connected to the sampling clock output of the first frequency synthesis synchronization module 7, CH1 is connected to the external RF input CH1, CH2 is connected to the output of the first switch 3C, JESD data is connected to the first FPGA module 5, the CLK4 clock of the first FPGA module 5 is connected to the output of the first frequency synthesis synchronization module 7, ctrl1 is connected to the control input of the first switch 3C, GTX1 is connected to the high-speed serial data electrical signal input of the first optical module 6, JESD is connected to the data output of the ADC module 4, SYN2R is connected to the output of the first delay measurement module 9 and the input of the first frequency synthesis synchronization module 7, TRIG1 is connected to the external main trigger input, TRIG 2 is connected to the trigger signal input of the first delay measurement module 9 and the first frequency synthesis synchronization module 7, the GTX1 of the first optical module 6 is connected to the high-speed serial data output of the first FPGA module 5, the optical output is connected to the λ3 and λ4 inputs of the first wavelength division multiplexer 8, the λ1 and λ2 interfaces of the first wavelength division multiplexer 8 are connected to the optical interface of the first delay measurement module 9, the λ3 and λ4 interfaces are connected to the optical output of the first optical module 6, the COM port is connected to the transmission optical cable, the optical interface of the first delay measurement module 9 is connected to the λ1 and λ2 interfaces of the first wavelength division multiplexer 8, RCLK is connected to the recovered clock input of the first frequency synthesis synchronization module 7, the STNA pulse is connected to the output of the first frequency synthesis synchronization module 7, and the SY The N2R synchronization signal is locally looped back and connected to the first FPGA module 5 and the first frequency synthesis synchronization module 7 input, the ADCLK of the first frequency synthesis synchronization module 7 is connected to the ADC module 4 sampling clock input, CLK4 is connected to the first FPGA module 5 clock input, TRIG2 trigger input is connected to the first FPGA module 5 trigger output, RCLK is connected to the first delay measurement module 9 recovery clock output, SYN2R is connected to the first delay measurement module 9 output, SYNA synchronization modulation signal output is connected to the first switch 3B input, SYNA pulse is connected to the delay measurement input, the A interface of the first switch 3 is connected to the external RF input CH2, and the B interface is connected to the first frequency synthesis synchronization module Block 7SYNAM1 synchronous modulation signal output, ctrl1 interface connected to the first FPGA module 5 control output, the COM interface of the second wavelength division multiplexer 10 is connected to the transmission optical cable, λ3, λ4 interface connected to the second optical module 11 optical port, λ1, λ2 interface connected to the second delay measurement module 18 optical port, the optical port of the second optical module 11 is connected to the wavelength division multiplexer λ3, λ4 interface, GTX2 connected to the second FPGA module 12 high-speed serial data input, the second FPGA module 12 CLK3 connected to the second frequency synthesis synchronization module 17 clock input and output, ctrl2 connected to the second switch 15 control input, GTX2 connection interface second optical module 11 electrical signal,JESD is connected to the sampling data input of the DAC module 13, SYN1 is connected to the external synchronization signal input, SYN2 and SYN2R are connected to the synchronization signal input and output of the second delay measurement module 18, SYNAR pulse is connected to the synchronization modulation signal output of the synchronization detection module 16, TRIG2R is connected to the output of the second delay measurement module 18, CH1 of the DAC module 13 is connected to the external user RF signal output, CH2 is connected to the input of the power divider 14, DACclk is connected to the conversion clock output of the second frequency synthesis synchronization module 17, JESD is connected to the sampling data output of the second FPGA module 12, the input of the power divider 14 is connected to the CH2 output of the DAC module 13, and the two outputs are respectively connected to the second switch 15A input and the synchronization detection module 16 input, the input of the switch input is connected to the output of the power divider 14, and the output is connected to the external CH2 RF signal output, ctrl2 connected to the control output of the second FPGA module 12, the input of the synchronization detection module 16 connected to the output of the power divider 14, the output connected to the SYNAR pulse input of the second FPGA module 13, the CLK1 of the second frequency synthesis synchronization module 17 connected to the external reference clock input, CLK2 connected to the clock input of the second delay measurement module 18, CLK3 connected to the clock input and output of the second FPGA module 12, DACclk connected to the DAC conversion clock input, CLK2 of the second delay measurement module 18 connected to the synchronization clock output of the second frequency synthesis synchronization module 17, SYN2, SYN2RR connected to the synchronization signal output and input of the second FPGA module, TRIG2R output connected to the trigger signal input of the second FPGA module 12, and the optical interface connected to the λ1 and λ2 interfaces of the second wavelength division multiplexer 10;

[0036] The ADC module 4 is a dual-channel TXADC with a resolution of 14 bits, a maximum sampling frequency of 1.25 GHz, an analog input full power bandwidth of 2 GHz, and a JESD204B (subtype) encoded serial digital output. The main chips of the first FPGA module 5 and the second FPGA module 12 are XC7K325T-2FFG900. The first optical module 6 is a dual light-emitting module with a wavelength of DWDM CH32, CH33 (1551.72 nm, 1550.92 nm), an output optical power of 0 dBm to 2 dBm, a transmission data rate of 10 Gbit / s, and a maximum transmission distance of 100 km. The second optical module 11 is a dual light-receiving module with a wavelength of DWDM CH32, CH33 (1551.72nm, 1550.92nm), receiving sensitivity ≤-24dBm, saturated receiving power ≥0dBm, transmission data rate 10Gbit / s, maximum transmission distance 100km, the first wavelength division multiplexer 8 and the second wavelength division multiplexer 10 are 4-channel DWDM wavelength division multiplexers, the wavelengths are CH32\CH33\CH34\CH35, the insertion loss ≤1dB, the first delay measurement module 9 and the second delay measurement module Block 18 is a 16-bit multiplexing / demultiplexing low-jitter transmission delay measurement module with a measurement accuracy of 200ps, a wavelength of CH34 and CH35 (1550.12nm and 1549.32nm) of DWDM, an output optical power of 0dBm to 2dBm, a transmission rate of 1.25Gbit / s, a receiving sensitivity of ≤-36dBm, a saturated receiving power of ≥0dBm, a maximum transmission distance of 120km, and the first frequency synthesis synchronization module 7 and the second frequency synthesis synchronization module 17 are ZERO DELAY phase-locked module, reference frequency input range is DC ~ 250MHHz, input level is CMOS, LVDS or LVPECL level, output is CMOS or LVPECL level, output frequency range is 0 ~ 2.4GHz, output channel number is 12, output additional jitter ≤ 225fs, output delay error between channels ≤ 16ps, the DAC module 13 is a dual-channel TxDAC, resolution 16bit, conversion rate 1.6Gbit / s, digital interpolation filter none / 2X / 4X / 8X / 16 V is optional, the inherent delay difference of TxDAC conversion is ≤2 DACCLK cycles, the synchronous detection module 16 is a microwave detector, the input frequency range is 0.01~4GHz, the in-band fluctuation is ≤±0.3dB, the low-level sensitivity (at -30dBm) is ≥0.5mV, the power divider 14 operates in the frequency range of 0~6GHz, the insertion loss is 3.5dB, the first switch 3 and the second switch 15 are single-pole double-throw non-reflective microwave switch circuits, the on / off rate is 5n, the operating frequency is DC~12GHz, and the insertion loss is 1.4dB, isolation 57dB, 1dB compression point +30dBm, control interface level TTL / PLECL;.

[0037] The system adjusts the FIFO data storage position of the second FPGA module 13 according to the measured delay value and the system delay value set by the receiver 2, so that the transmission delay of all channels remains unchanged with the time relationship of the transmitter 1, that is, after the delay is adjusted, the mutual time relationship of the TRIG signals of each channel remains unchanged with the time relationship of the TRIG signal of the transmitting station. After the adjustment, the first FPGA module 5 and the second FPGA module 13 control the first switch 3 and the second switch 15 to connect the RF input and output to transmit the RF signal. The system uses the synchronous modulation signal sent during the main trigger period to measure and adjust the RF transmission delay, which does not affect the transmission of the echo RF signal, and solves the problem of insufficient transmission delay stability of the existing RF signal during data optical transmission.

[0038] See also Figure 2-Figure 4 In a second aspect, the present invention further provides a method for controlling delay of a radio frequency signal sampling conversion optical transmission device, which is applied to the control system for delay of a radio frequency signal sampling conversion optical transmission device as described in the first aspect above, and comprises the following steps:

[0039] S1 measures the optical cable transmission time and obtains the optical cable delay;

[0040] In the embodiment of the present invention, when the power is turned on, the second frequency synthesis synchronization module 17 of the receiver 2 performs zero-delay phase-locking on the externally input 10MH reference clock to generate the CLK2 (40MHz), CLK3 (250MHz) and DACCLK conversion clock (1GHz) required by the second delay measurement module 18, the second FPGA module 13 and the DAC module 13. The external input synchronization signal SYN1 is shaped by the second FPGA module 13 to obtain the SYN2 synchronization pulse output to the second delay measurement module 18. The second delay measurement module 18 performs synchronization The optical signal is multiplexed in steps, and then converted into an optical signal, which is transmitted to the transmitter 1 through the first wavelength division multiplexer 8, the second wavelength division multiplexer 10 and the optical cable. The transmitter 1 receives the optical signal, and recovers the synchronization pulse SYN2R through the optical / electrical conversion inside the first delay measurement module 9. The SYN2R is locally looped back and transmitted back to the receiver 2. The second delay measurement module 18 calculates the transmission time of SYN2 and SYN2R. Since the circuits of the two delay measurement modules and the transmission optical cables are the same, the time required for transmission in both directions is the same. Therefore, the round-trip transmission time (SYN2R-SYN2) divided by 2 is the unidirectional optical cable transmission time t 光缆 Then the second delay measurement module 18 sets t 光缆are transmitted to the receiver 2 and the transmitter 1 respectively. 光缆 Including the optical cable transmission time and the processing time of the second delay measurement module 18 and the first delay measurement module 9, the processing time of the second delay measurement module 18 and the first delay measurement module 9 is about 200ns, and the optical cable transmission time is about 5us / km. After the optical cable of the transmitter 1 and the receiver 2 is laid, t 光缆 The ambient temperature change has a slight impact on the optical cable transmission delay, and the impact of G.652 optical fiber is about 30ps to 50ps / km.°C. The SYN2R signal of the first delay measurement module 9 is also sent to the first FPGA module 5 and the first frequency synthesis synchronization module 7 for signal synchronization.

[0041] The clock recovered by the first delay measurement module 9 is de-jittered, phase-locked and divided, and then outputs a 10MHz low-jitter clock (RCLK) to the first frequency synthesis synchronization module 7, which generates the clock CLK4 (250MHz) of the first FPGA module 5 and the required sampling clock ADCCLK (1GHz) of the ADC module 4. The clocks used by each module of the transmitter 1 and the receiver 2 are the same source clocks obtained from CLK1.

[0042] Specific method:

[0043] S11: The external input synchronization signal is shaped and processed by the second FPGA module 13 to obtain a synchronization pulse, and output it to the second delay measurement module 18;

[0044] S12: the second delay measurement module 18 synchronously multiplexes the synchronization pulses to convert them into optical signals, which are transmitted to the transmitter 1 via the first wavelength division multiplexer 8, the second wavelength division multiplexer 10 and the optical cable;

[0045] S13 The optical signal recovers the synchronization pulse through the first delay measurement module 9 and transmits it back to the receiver 2.

[0046] S2 measures the trigger delay time of transmitter 1;

[0047] In the embodiment of the present invention, the TRIG1 trigger delay time (denoted as t TRIG) The delay time of the rising edge of the first TRIG1 pulse based on the rising edge of SYN2R, TRIG1 is shaped into TRIG2 by the first FPGA module 5 and is also transmitted to the receiver 2 through the first delay measurement module 9. The first FPGA module 5 generates a ctrl1 control signal based on the rising edge of the first pulse of TRIG1 to control the first switch 3B interface to connect the synchronous modulation signal. The time for the ctrl1 control signal to open the first switch 3B interface should be slightly longer than the duration of the SYNA synchronous modulation signal to ensure that the synchronous modulation signal can pass completely. Figure 2 shown.

[0048] S3 measures the synchronous modulation pulse delay of receiver 2;

[0049] In the embodiment of the present invention, the SYNA synchronous modulation signal is sampled and processed at high speed by the ADC module 4, transmitted by the first FPGA module 5, the first optical module 6, the first wavelength division multiplexer 8, the second wavelength division multiplexer 10, the second optical module 12, and the second FPGA module 13, and processed by the DAC module 13, and the restored synchronous modulation signal is restored by the synchronous detection module 16 to obtain the SYNAR synchronization pulse.

[0050] S4 calculates the delay difference between the trigger delay time and the synchronous modulation pulse delay;

[0051] In the embodiment of the present invention, the second FPGA module 12 calculates the delay time between the SYNAR pulse and SYN1, which is subtracted from t 光缆 That is, the time t taken for the RF input of the transmitter 1 to be transmitted to the receiver 2 through the RF transmission channel error .

[0052] S5 adjusts the FIFO data storage location based on the delay difference;

[0053] In the embodiment of the present invention, since the transmission delay of the signal processing transmission link from the ADC module 4 to the DAC module 13 changes each time the device is turned on and off, the delay time between the SYNAR pulse and SYN1 changes each time the device is turned on and off. The second FPGA module 12 needs to adjust the FIFO data storage position of the second FPGA module 12 based on the measured delay value and the system delay value set by the receiver 2 (denoted as t1) so that the transmission delay of all channels remains unchanged with the time relationship of the transmitter 1, that is, after the delay is adjusted, the mutual time relationship of the TRIG signals of each channel (station) remains unchanged with the time relationship of the TRIG signal of the transmitting station, such as Figure 3 shown.

[0054] S6 switches the first switch 3 and the second switch 15 to connect the RF input and output to transmit the RF signal.

[0055] In order to better understand the present technical solution, the following embodiments are provided for further explanation:

[0056] Assume that the optical cable transmission distances from the receiver 2 to the transmitter 1A and the transmitter 1B are 80km and 90km respectively, the optical fiber transmission delay is calculated as 5us / km, the processing time of the first delay measurement module 9 and the second delay measurement module 18 is 0.2us, the time required for the synchronization signal SYN2 to be transmitted from the receiver 2 to the transmitting station is 400.2us and 450.2us respectively, and the delay time t between the trigger TRIG input from the transmitter 1A and SYN2 TRIGa The delay time t between the trigger TRIG and SYN2 of the external input of the transmitter 1B is 10us. TRIGb Assuming that the time for the synchronous SYNA modulation signal generated by the trigger TRIG signal to be transmitted from the transmitter 1 to the receiver 2 through the RF transmission channel and detected with SYN1 is 840.2us and 940.2us respectively, and the system delay value is set to 800us, the FIFO adjustment time should be 800us-840.2us+400.2us+t TRIGa =370us and 800us-940.2us+450.2us+t TRIGb =340us. Figure 5 As shown. At the transmitter t TRIG1A and t TRIG1B The time difference is 70us. After being transmitted to the receiver 2 and before adjustment, the time difference is 98us. After FIFO adjustment, the time difference is 70us, which is the same as the time relationship at the transmitting end.

[0057] What is disclosed above is only a preferred embodiment of the delay control system and method for RF signal sampling and conversion optical transmission equipment of the present invention. Of course, this cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiments and equivalent changes made according to the claims of the present invention still fall within the scope of the invention.

Claims

1. A delay control system for radio frequency signal sampling and conversion optical transmission equipment, characterized in that ； The invention comprises a transmitter and a receiver, wherein the transmitter comprises a first switch, an ADC module, a first FPGA module, a first optical module, a first frequency synthesis synchronization module, a first wavelength division multiplexer and a first delay measurement module, and the receiver comprises a second wavelength division multiplexer, a second optical module, a second FPGA module, a DAC module, a power divider, a second switch, a synchronization detection module, a second frequency synthesis synchronization module and a second delay measurement module; The first switch is respectively connected to the first frequency synthesis synchronization module, the ADC module and the first FPGA module, the ADC module is respectively connected to the first FPGA module and the first frequency synthesis synchronization module, the first FPGA module is respectively connected to the first optical module, the first frequency synthesis synchronization module and the first delay measurement module, the first wavelength division multiplexer is respectively connected to the first optical module, the first delay measurement module and the second wavelength division multiplexer, the first frequency synthesis synchronization module and the first delay measurement module are connected, the second wavelength division multiplexer is respectively connected to the second optical module and the second delay measurement module, the second FPGA module is respectively connected to the second optical module, the DAC module, the second switch, the synchronization detection module, the second frequency synthesis synchronization module and the second delay measurement module, the DAC module is respectively connected to the power divider and the second frequency synthesis synchronization module, the power divider is respectively connected to the second switch and the synchronization detection module, and the second frequency synthesis synchronization module is connected to the second delay measurement module.

2. A method for delay control of radio frequency signal sampling conversion optical transmission equipment, applied to the delay control system for radio frequency signal sampling conversion optical transmission equipment as claimed in claim 1, characterized in that: The steps include: Measure the optical cable transmission time to obtain the optical cable delay; Measure transmitter trigger delay time; Measure the receiver synchronization modulation pulse delay; Calculate the delay difference between the trigger delay time and the synchronous modulation pulse delay; adjusting a FIFO data storage location based on the delay difference; Switching the first switch and the second switch connects the RF input and output to transmit the RF signal.

3. The delay control method for radio frequency signal sampling conversion optical transmission equipment according to claim 2, characterized in that ； The specific method of measuring the optical cable transmission time and obtaining the optical cable delay is as follows: The external input synchronization signal is shaped and processed by the second FPGA module to obtain a synchronization pulse, and is output to the second delay measurement module; The second delay measurement module synchronously multiplexes the synchronization pulses to convert them into optical signals, which are transmitted to the transmitter via the first wavelength division multiplexer, the second wavelength division multiplexer and the optical cable; The optical signal is restored to a synchronization pulse through the first delay measurement module and is transmitted back to the receiver. The second delay measurement module calculates the synchronization pulse and the transmission time of the restored synchronization pulse to obtain the optical cable delay.

4. The delay control method for radio frequency signal sampling conversion optical transmission equipment according to claim 2, characterized in that ； The specific method of measuring the synchronous modulation pulse delay of the receiver is as follows: The synchronous modulation signal is sampled and processed at high speed by the ADC module, and then transmitted by the first FPGA module, the first optical module, the first wavelength division multiplexer, the second wavelength division multiplexer, the second optical module, and the second FPGA module and processed by the DAC module. The restored synchronous modulation signal is recovered by the second synchronization detection module to restore the synchronization pulse, and the second FPGA module calculates the delay time between the synchronization pulse and the synchronization signal.

5. The delay control method for radio frequency signal sampling conversion optical transmission equipment according to claim 2, characterized in that ； The optical cable delay includes the optical cable transmission time and the processing time of the first delay measurement module and the second delay measurement module. The processing time of the first delay measurement module and the second delay measurement module is 200ns, and the optical cable transmission time is about 5us / km.

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