Method and electronic equipment for calibration compensation of synchronous clock of inertial measurement unit product
Through clock calibration between external control equipment and inertial product and software-implemented clock compensation, the problem of synchronous clock frequency drift caused by temperature-compensated crystal oscillator aging is solved, and the clock accuracy and reliability of inertial product are improved.
Patent Information
- Application Number
- CN202411726180.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-04-08
AI Technical Summary
The aging of temperature-compensated crystal oscillator in inertia products causes the frequency drift of the synchronous clock, reducing the accuracy and performance of the product.
Through the clock calibration between the external control device and the inertial product, the clock calibration error is calculated and sent, and the inertial product is implemented with software to ensure the accuracy of the synchronous clock.
It effectively improves the synchronous clock accuracy of inertia product output, avoids the impact of crystal oscillator aging on clock accuracy, and improves the accuracy and reliability of the product.
Smart Images
Figure CN119788227A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a method for calibration and compensation of synchronous clock of an inertial group product and electronic equipment, belonging to the technical field of time service. Background Art
[0002] There is a need for data synchronization between inertial group products and external control devices, and the inertial group products provide synchronous clock output for external control devices to use. The inertial group product uses a temperature-compensated crystal oscillator to provide a clock source for the processor. As the performance of the temperature-compensated crystal oscillator components changes over time and the components age, the output frequency of the temperature-compensated crystal oscillator ages and drifts, resulting in a decrease in the accuracy of the temperature-compensated crystal oscillator. After the inertial group product has been in service for several years, due to the aging of the temperature-compensated crystal oscillator, the output synchronous clock cannot meet the technical index requirements of the overall unit, reducing the accuracy and performance indicators of the inertial group product. Therefore, in order to ensure that the accuracy of the synchronous clock output by the inertial group product is not affected by the aging and attenuation of the crystal oscillator, thereby improving the accuracy and reliability of the inertial group product, it is urgent to propose an effective technical solution to solve the above problems. Summary of the invention
[0003] The present invention aims to provide a method for calibrating and compensating the synchronous clock of an inertial group product, thereby improving the accuracy of the synchronous clock output by the inertial group product, solving the problem of the annual aging rate of the crystal oscillator, and improving the accuracy and reliability of the inertial group product.
[0004] In order to achieve the above object, the technical solution adopted by the present invention is: a method for calibrating and compensating the synchronous clock of an inertial group product, the method comprising the following steps:
[0005] Step 1, clock calibration: within the clock calibration reference, the external control device calculates the difference between the output time of its timing device and the synchronization time output by the inertial group product within the clock calibration reference, obtains the clock calibration error, and sends it to the inertial group product;
[0006] Step 2, clock compensation: based on the received clock calibration error, the inertial group product calculates the number of FPGA system clock pulses that need to be compensated in 1s; the number of FPGA system clock pulses that need to be compensated in 1s is maximized and evenly compensated within the internal sampling period of the inertial group in 1s to complete the clock calibration compensation.
[0007] The clock calibration and compensation performed by the method is implemented by software and does not involve changes in hardware status. The clock calibration in step 1 is completed by the external control device, and the clock compensation in step 2 is completed by the inertial group product. The method does not compensate for the clock output by the crystal oscillator, but compensates for the synchronous clock output by the inertial group product to the external control device. The clock accuracy of the timing device of the external control device is relatively high, which can reach the order of 1*e-12s. The external control device calibrates the synchronous clock output by the inertial group product and calculates the difference between its timing device and the synchronous clock of the inertial group product; after the clock calibration is completed, the external control device sends the clock difference to the inertial group product, and the clock compensation work is completed inside the inertial group product to ensure that the accuracy of the synchronous clock output by the inertial group product is not affected by the aging and attenuation of the crystal oscillator, thereby improving the accuracy and reliability of the inertial group product.
[0008] According to the embodiments of the present invention, the present invention can be further optimized. The following is the technical solution formed after optimization:
[0009] In one preferred embodiment, step 2 specifically includes:
[0010] Calculate the number of FPGA system clock pulses that need to be compensated in 1s: N = Δt*X*1000000; wherein, Δt = ΔT / Q, Δt is the 1s clock calibration error, Q is the clock calibration reference, ΔT is the clock calibration error sent by the external control device received by the inertial group product, and X is the FPGA system clock cycle, in MHz;
[0011] Calculate P = 1000 / t; where t is the inertial group synchronization clock period, in ms, and P is the number of inertial group synchronization clock periods required to evenly compensate N clock pulses within 1 second;
[0012] If N is divisible by P, the number of FPGA system clock pulses that need to be compensated for each of the P inertial group synchronous clock periods t ms is N / P, and 1s clock compensation is completed;
[0013] If N is not divisible by P, 1s is divided into the first N1 t ms and the last (P-N1) t ms. The number of FPGA system clock pulses that need to be compensated in the first N1 synchronous clock cycles t ms is N / P+1, and the number of FPGA system clock pulses that need to be compensated in the last (P-N1) synchronous clock cycles t ms is N / P, where N1=N% / P.
[0014] Each of the first N1 synchronous clock cycles t ms is divided into the first N2 inertial group internal sampling cycles f ms and the last (q-N2) inertial group internal sampling cycles f ms, the first N2 inertial group internal sampling cycles f ms are compensated for N21 FPGA system clock pulses, and the last (q-N2) inertial group internal sampling cycles f ms are compensated for N22 FPGA system clock pulses, wherein q is the number of inertial group internal sampling cycles in each synchronous clock cycle t ms, q=t / f, N2=(N / P+1)%q, N21=(N / P+1) / q+1, N22=(N / P+1) / q;
[0015] Divide each of the last (P-N1) synchronous clock cycles t ms into the first N3 internal sampling cycles f ms of the inertial group and the last (q-N3) internal sampling cycles f ms of the inertial group, the first N3 internal sampling cycles f ms of the inertial group each compensate for N31 clock pulses of the FPGA system, and the last (q-N3) internal sampling cycles f ms of the inertial group each compensate for N32 clock pulses of the FPGA system, wherein N3 = (N / P)% q, N21 = (N / P) / q+1, N22 = (N / P) / q; and complete 1s clock compensation.
[0016] The synchronization clock period of inertial products is usually 5ms, 10ms or other periods.
[0017] In one preferred embodiment, the clock calibration reference is 100s. Different clock calibration references can be selected according to actual use requirements and clock compensation accuracy, such as 50s, 100s, 200s, and 300s. Selecting 100s as the clock calibration reference meets the actual use requirements of the external control device and maximizes the clock compensation accuracy.
[0018] Based on the same concept, the present invention also provides an electronic device, which includes a memory and one or more processors; one or more programs are stored in the memory, and when the one or more programs are executed by the one or more processors, the one or more processors implement the steps of the above method.
[0019] Compared with the prior art, the beneficial effects of the present invention are as follows: the clock calibration compensation method for synchronous clock calibration of inertial group products provided by the present invention is implemented by software and does not involve hardware state changes. Because the clock accuracy of the timing device of the external control device is relatively high, the external control device calibrates the synchronous clock output by the inertial group product and calculates the difference between its timing device and the synchronous clock of the inertial group product; after the clock calibration is completed, the external control device sends the clock difference to the inertial group product, and the clock compensation is completed inside the inertial group product, ensuring that the accuracy of the synchronous clock output by the inertial group product is not affected by the aging and attenuation of the crystal oscillator, thereby improving the accuracy and reliability of the inertial group product. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 This is a block diagram of the calibration and compensation connection of an inertial group synchronous clock according to an embodiment of the present invention;
[0021] Figure 2 This is a schematic diagram of dividing 1s into the first N1 5ms and the last (200-N1) 5ms in one embodiment of the present invention;
[0022] Figure 3 Schematic diagram of dividing each of the first N1 5ms into N2 0.5ms and (10-N2) 0.5ms according to an embodiment of the present invention;
[0023] Figure 4 This is a schematic diagram of dividing each of the last (200-N1) 5 ms into N3 0.5 ms and (10-N3) 0.5 ms according to an embodiment of the present invention. DETAILED DESCRIPTION
[0024] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.
[0025] Example 1
[0026] This embodiment 1 provides a method for calibrating and compensating the synchronous clock of an inertial group product, which performs calibration and compensation on the synchronous clock output by the inertial group product to ensure that the accuracy of the synchronous clock output by the inertial group product is not affected by the aging and attenuation of the crystal oscillator, thereby improving the accuracy and reliability of the inertial group product. The method includes the following steps:
[0027] Step 1: Clock calibration
[0028] After the external control device enters the clock calibration mode, a 100s clock calibration is performed on the 5ms synchronous clock output by the inertial group product (the synchronous clock of the inertial group product usually has a period of 5ms, 10ms or other periods, and the 5ms synchronous clock is selected as an example in this embodiment 1); the external control device obtains the 100s clock calibration error of the inertial group through the timing device (the timing device has a high accuracy, on the order of 1*e-12s) and the inertial group 5ms synchronous clock pulse test.
[0029] Specific method for clock calibration: By testing the difference between the 100s clock of the external timing device and the time when the inertial group product outputs the synchronous clock during this time, the clock error (deviation) of the inertial group product within 100s is obtained. After the clock calibration is completed, the external control device sends the 100s clock calibration error to the inertial group product through a command message, and the inertial group product completes the clock calibration compensation. In this embodiment 1, 100s is selected as the clock calibration benchmark, taking into account the actual use requirements of the external control device and maximizing the clock compensation accuracy. In actual application, different clock calibration benchmarks can be selected according to the use requirements and the clock compensation accuracy, such as 50s, 100s, 200s, and 300s.
[0030] Step 2: Clock Compensation
[0031] 1. The inertial group receives the 100s clock calibration error ΔT sent by the external control device, and divides ΔT by 100 to obtain the 1s clock calibration error Δt. The FPGA system clock cycle is X MHz, that is, X*1000000Hz, and the system clock cycle can be set according to actual needs. Calculate the number of FPGA system clock pulses N=Δt*X*1000000 that need to be compensated for the 1s clock calibration error. There are 200 5ms in 1s, so it is necessary to evenly compensate N clock pulses in 200 5ms to complete the 1s clock compensation. The purpose of clock compensation in this embodiment is to maximize the uniform compensation of the clock error within the 200 5ms in 1s. If the number of clocks N that need to be compensated for the 1s clock cannot be divided by 200, the remainder is N1=N%200, then the first N1 5ms of 1s are compensated for one more FPGA system clock pulse.
[0032] 2. If Figure 2As shown, the 1s clock is divided into the first N1 5ms and the last (200-N1) 5ms. Among them, N1=N%200, ΔN1=N / 200+1, Δ(200-N1)=N / 200. Among them, N is the number of FPGA system clock pulses that need to be compensated in 1s, Δ(200-N1) is the number of FPGA system clock pulses that need to be compensated in 200 5ms in 1s, and the first N1 5ms of 1s need to compensate one more FPGA system clock pulse each, that is, the number of FPGA system clock pulses that need to be compensated in the first N1 5ms is ΔN1=N / 200+1, and the number of FPGA system clock pulses that need to be compensated in the last 200-N1 5ms is Δ(200-N1)=N / 200.
[0033] 3. If Figure 3 As shown, each of the first N1 5ms is divided into N2 0.5ms and (10-N2) 0.5ms, where N2 = ΔN1%10, N21 = ΔN1 / 10+1, and N22 = ΔN1 / 10. 0.5ms is the internal sampling period of the inertial group.
[0034] 4. If Figure 4 As shown, each of the last (200-N1) 5ms is divided into N3 0.5ms and (10-N3) 0.5ms, where N3=Δ(200-N1)%10, N31=Δ(200-N1) / 10+1, and N32=Δ(200-N1) / 10.
[0035] In summary, the 1s clock calibration compensation specifically includes: calculating the number N of FPGA system clock pulses that need to be compensated for 1s, and maximizing the compensation of the N FPGA system clock pulses to the first N1 5ms and the last (200-N1) 5ms. In the first N1 5ms, each 5ms is divided into the first N2 0.5ms and the last (10-N2) 0.5ms, where N21 clock pulses are compensated in the first N2 0.5ms and N22 clock pulses are compensated in the last (10-N2) 0.5ms. In the last (200-N1) 5ms, each 5ms is divided into the first N3 0.5ms and the last (10-N3) 0.5ms, where N31 clock pulses are compensated in the first N3 0.5ms and N32 clock pulses are compensated in the last (10-N3) 0.5ms.
[0036] Example 2
[0037] Before the synchronous clock calibration compensation was performed in this embodiment 2, the synchronous clock aging drift was 5.1ppm (1s deviation was 5.1us) through the external timing device calibration test. The actual usage requirement in this embodiment 2 is 1000s, that is, the 1000s clock deviation is 5.1ms, which seriously affects the output data accuracy and reliability of the inertial group product. The synchronous clock calibration compensation was performed on it, and it was calculated that 245 FPGA system clock pulses need to be compensated for 1s. After compensation, the 1s deviation is 0.00417us, and the 1000s clock deviation is 4.17us, which greatly improves the accuracy of the synchronous clock of the inertial group product, while ensuring the accuracy and reliability of the inertial group output data.
[0038] Example 3
[0039] This embodiment 3 provides an electronic device, which includes a memory and one or more processors; one or more programs are stored in the memory, and when the one or more programs are executed by the one or more processors, the one or more processors implement the steps of the method described in embodiment 1.
[0040] The contents explained in the above embodiments should be understood as these embodiments are only used to more clearly illustrate the present invention, and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the embodiments made by those skilled in the art fall within the scope defined by the claims attached to the present invention.
Claims
1. A method for calibrating and compensating synchronous clocks of inertial group products, characterized in that: The method comprises the following steps: Step 1: Clock calibration: Within the clock calibration reference, the external control device calculates the difference between the output time of its timing device and the synchronization time output by the inertial group product within the clock calibration reference, obtains the clock calibration error, and sends it to the inertial group product; Step 2: Clock compensation: According to the received clock calibration error, the inertial group product calculates the number of FPGA system clock pulses that need to be compensated in 1s; The number of FPGA system clock pulses that need to be compensated in the 1s is maximized and evenly compensated within the internal sampling period of the inertial group in 1s to complete the clock calibration compensation.
2. The method for calibrating and compensating synchronous clocks of inertial group products according to claim 1, characterized in that: The step 2 specifically includes: Calculate the number of FPGA system clock pulses that need to be compensated in 1s: N = Δt*X*1000000; wherein, Δt = ΔT / Q, Δt is the 1s clock calibration error, Q is the clock calibration reference, ΔT is the clock calibration error sent by the external control device received by the inertial group product, and X is the FPGA system clock cycle, in MHz; Calculate P = 1000 / t, where t is the inertial group synchronization clock period, in milliseconds, and P is the number of inertial group synchronization clock periods required to evenly compensate N clock pulses within 1 second; If N is divisible by P, the number of FPGA system clock pulses that need to be compensated for each of the P inertial group synchronous clock periods t ms is N / P, and 1s clock compensation is completed; If N is not divisible by P, 1s is divided into the first N1 t ms and the last (P-N1) t ms. The number of FPGA system clock pulses that need to be compensated in the first N1 synchronous clock cycles t ms is N / P+1, and the number of FPGA system clock pulses that need to be compensated in the last (P-N1) synchronous clock cycles t ms is N / P, where N1=N% / P. Each of the first N1 synchronous clock cycles t ms is divided into the first N2 inertial group internal sampling cycles f ms and the last (q-N2) inertial group internal sampling cycles f ms. The first N2 inertial group internal sampling cycles f ms are compensated by N21 FPGA system clock pulses, and the last (q-N2) inertial group internal sampling cycles f ms are compensated by N22 FPGA system clock pulses, wherein q is the number of inertial group internal sampling cycles in each synchronous clock cycle t ms, q=t / f, N2=(N / P+1)%q, N21=(N / P+1) / q+1, N22=(N / P+1) / q; Divide each of the last (P-N1) synchronous clock cycles t ms into the first N3 internal sampling cycles f ms of the inertial group and the last (q-N3) internal sampling cycles f ms of the inertial group, the first N3 internal sampling cycles f ms of the inertial group each compensate for N31 clock pulses of the FPGA system, and the last (q-N3) internal sampling cycles f ms of the inertial group each compensate for N32 clock pulses of the FPGA system, wherein N3 = (N / P)%q, N21 = (N / P) / q+1, N22 = (N / P) / q; and complete 1s clock compensation.
3. The method for calibrating and compensating synchronous clocks of inertial group products according to claim 1 or 2, characterized in that: The clock calibration reference is 100s.
4. An electronic device, characterized in that: The electronic device includes a memory and one or more processors; one or more programs are stored in the memory, and when the one or more programs are executed by the one or more processors, the one or more processors implement the steps of the method described in any one of claims 1 to 3.