A 1t1r array encryption method based on benes network

Abstract

The application discloses a 1T1R array encryption method based on Benes networks and belongs to the technical field of semiconductor memories. The application connects a plurality of Benes networks 1 on the row of the 1T1R array and connects a plurality of Benes networks 2 on the column of the 1T1R array, and the control signals of the Benes network 1 and the Benes network 2 are secret keys, which are separately stored and transmitted. The specific steps include the following: firstly, performing arbitrary row and column transformation on the 1T1R array to disturb the internal data of the memory-computing integrated chip, and then using the Benes network 1 and the Benes network 2 to perform permutation on the input and output thereof. The encryption method does not change the weight distribution, has the advantages of small occupied area and low power consumption compared with the traditional encryption permutation mode. In addition, the Benes network is adopted to avoid introducing new calculation errors, and the accuracy and integrity can be maintained in the encryption process.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor memory, and particularly relates to an encryption method of a 1T1R array. BACKGROUND

[0002] The memory-computing integrated technology is regarded as an important way to change the traditional von Neumann computing architecture and break through the chip computing power and energy efficiency bottleneck. Resistive memory (ReRAM, MRAM, FeRAM, PCRAM, etc.) is a device with memory and resistance characteristics, which can maintain its resistance state without power supply and change its resistance level by applying voltage. Resistive memory can store neural network weights and realize in-memory computing. A common storage array of resistive memory is 1T1R type, that is, an array composed of a unit connected by one transistor and one resistive device.

[0003] In the resistive memory based on the 1T1R array, voltage is used as input and current is used as output. The conductance between the input voltage and the fixed resistance is multiplied to generate current, thereby realizing the multiplication and accumulation operation of the neural network. In this architecture, the resistance value of each storage unit corresponds to a specific weight in the neural network. However, since these weights usually exist in physical form, that is, resistance value, they may face the risk of being read and copied by physical or other means.

[0004] The permutation operation on the neural network weights stored in the 1T1R array is an effective way to achieve encryption. This permutation operation aims to encrypt the weight data, prevent potential theft, and ensure the security of the stored information. However, a simple permutation of the weights in the memory will change the order of input and output, resulting in incorrect calculation results after permutation. Therefore, special read-in and read-out circuits are needed to adjust them to ensure that the correct in-memory computing results are read out. SUMMARY

[0005] The purpose of the present application is to provide a 1T1R array encryption method based on Benes network, which can effectively encrypt the internal data of the in-memory computing chip.

[0006] The technical solution provided by the present application is as follows:

[0007] A 1T1R array encryption method based on Benes network, characterized in that a plurality of Benes network 1 is added on the row of the 1T1R array, and a plurality of Benes network 2 is added on the column of the 1T1R array, the control signals of the Benes network 1 and the Benes network 2 are secret keys, which are stored and transmitted separately, and the specific steps include the following:

[0008] 1) Perform permutation operation on the neural network weights stored in the 1T1R array, and perform column transformation on the basis of row transformation of the 1T1R array, to realize encryption;

[0009] 2) The original input sequence is permuted by Benes network 1 into the row sequence of the 1T1R array for input;

[0010] 3) The 1T1R array completes the matrix-vector multiplication operation and outputs the calculation result sequence;

[0011] 4) Benes network 2 permutes the calculation result sequence output by the 1T1R array into the calculation result sequence of the original input, so as to obtain the correct calculation result of the original input, and complete decryption.

[0012] Further, an 8-bit Benes network is provided for every 8 rows and every 8 columns of the 1T1R array.

[0013] Further, the same control signal is used for every three adjacent Benes networks.

[0014] The beneficial effects of the present application are as follows:

[0015] The encryption method designed by the Benes network does not change the weight distribution, but can effectively realize information encryption. Compared with the traditional encryption permutation method, the encryption circuit designed by the Benes network has the advantages of small area occupation and low power consumption. In addition, the encryption circuit designed by the Benes network avoids introducing new calculation errors, which means that the data can maintain accuracy and integrity during the encryption process. These advantages not only guarantee the privacy of data, but also have important significance for the development of current and future information security technology, and bring a new exploration direction to the field of information security. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a schematic diagram of a 1T1R array;

[0017] Figure 2 is a schematic diagram of a circuit structure for completing multiplication and addition operation of a 1T1R array;

[0018] Figure 3 is a schematic diagram of a chip internal circuit structure that has not been permuted;

[0019] Figure 4 is a schematic diagram of a chip internal circuit structure permuted by row;

[0020] Figure 5 is a schematic diagram of a chip internal circuit structure permuted by row and column;

[0021] Figure 6 is a schematic diagram of a Benes network structure;

[0022] Figure 7 Benes network structure diagram containing 8-bit input;

[0023] Figure 8 Schematic diagram of the encryption method of the present application. DETAILED DESCRIPTION

[0024] As Figure 1 shown, the 1T1R array is used to complete the matrix vector multiplication, that is, when the values of the resistances in the array are set, the multiplication and addition operation can be performed using this circuit structure, as Figure 2 shown. Taking BL1 as an example to illustrate this operation. First, ground BL1, for BL1, its output current is equal to the sum of the branch currents. According to the relationship between current and voltage and the concept of conductance, the current is equal to the voltage multiplied by the conductance. Let the input voltages be V1, V2, V3…Vn, and the conductances between BL1 and WL1, WL2, WL3…WLn be G1, G2, G3…Gn respectively. Therefore, the output current I1 at the end of BL1 is equal to V1*G1+V2*G2+V3*G3+…+Vn*Gn, that is, a multiplication and addition operation is realized.

[0025] The internal data of the 1T1R-based memory-compute integrated chip is at risk of unauthorized access or theft. The neural network weights stored in the chip are easy to be read, so a method is needed to encrypt and protect these data. However, simply replacing the weights inside the chip to encrypt will cause confusion of the input and output, and thus the result of in-memory computation will be wrong. Therefore, the way to encrypt the 1T1R array is to perform arbitrary row and column transformation to disrupt the internal data of the memory-compute integrated chip. Figure 3 Schematic diagram of the 1T1R array structure before permutation. As can be seen, when the input is abcd, the output obtained is 1*a+1*b+1*c+1*d, 1*a+1*b+1*c+0*d, 0*a+1*b+0*c+0*d and 1*a+0*b+0*c+0*d, that is, a+b+c+d, a+b+c, b and a respectively. Figure 4 Schematic diagram of the 1T1R array structure after row permutation. As can be seen, the row transformation is performed, and the order of the input signal is changed from abcd to cdba. Figure 5 Schematic diagram of the 1T1R array structure after row and column permutation. It performs column transformation on the basis of row transformation, and the order of the output signal is changed from a+b+c+d, a+b+c, b and a to b, a+b+c+d, a+b+c and a. Obviously, through these row and column transformations, the internal weights have been completely changed compared to the original array. Since the 1T1R array has been completely rearranged, the order of the input and output of the chip becomes chaotic.

[0026] The application adds several Benes networks 1 on the row of the 1T1R array, adds several Benes networks 2 on the column of the 1T1R array, and performs permutation on the 1T1R array by using the two Benes networks. The Benes network is a rearrangeable network based on the Banyan network, which is linked by the Butterfly and Inverse Butterfly structures. The structure enables it to complete various permutation operations from the input end to the output end, and has flexibility and high efficiency. Figure 6 The Benes network structure diagram is shown in FIG. 8. In the Benes network, a permutation operation of n bits requires log2n levels of Butterfly transformation and log2n levels of Inverse Butterfly transformation. This means that for a 64-bit permutation operation, 12 levels of transformation are required to implement. In this transformation, the amount of configuration information required by each level is 8 bits. This design enables the Benes network to efficiently perform data routing and transformation. Generally, in a processor, a permutation operation requires a Butterfly instruction and an Inverse Butterfly instruction, and log2n n-bit configuration information, which work together to complete the entire permutation operation.

[0027] In the implementation of the permutation function of the Benes network, the MUX (data selector) is a logic element, which mainly selects a specific signal from multiple input signals and directs it to a single output port. It is a multiple-input, single-output combinational logic circuit. For the Butterfly structure in the Benes network, when the control signal is 0, the MUX performs permutation operation; when the control signal is 1, the MUX directly connects the input signal to the output port. In the Inverse Butterfly, the corresponding logic is just the opposite, when the control signal is 1, the MUX performs permutation operation; when the control signal is 0, the MUX directly transmits the input signal. The MUX in the Benes network correctly transmits the input signal to the specified output port by configuration instruction, thereby realizing the permutation of input and output. As one of the key components of the Benes network, the MUX provides necessary support and guarantee for the effective transmission of data in complex network structure. The Benes network can realize arbitrary order exchange of signals. Taking 8-bit data input and 8-bit Benes network as an example, Figure 7 The circuit structure diagram of an 8-bit Benes network is shown in FIG. 8. Under the action of specific control signals 11010010, 01100010 and 01000010, the input signal can be permuted from ABCDEFGH to CFGHBDEA. The control signals of the Benes network 1 and the Benes network 2 are secret keys, which are stored and transmitted separately.​

[0028] The application provides a specific embodiment, as shown in the figure, the specific steps include the following: Figure 8

[0029] 1) The permutation operation is performed on the neural network weight stored in the 1T1R array, and the column transformation is performed on the basis of the row transformation of the 1T1R array, and the encryption is realized;

[0030] 2) The original input sequence abcd is permuted by the Benes network 1. In this example, the input sequence is permuted into cdba. Through the Benes network 1, the input signal can be one-to-one corresponding to the row sequence of the encrypted 1T1R array, and the row transformation is realized.

[0031] 3) The 1T1R array completes the corresponding matrix vector multiplication operation, and the corresponding output result is obtained.

[0032] 4) The processing is performed through the Benes network 2, the Benes network 2 permutes the calculation result sequence of the output of the 1T1R array into the calculation result sequence of the original input, and the decryption is completed. That is, the chaotic calculation result sequence c'a'b'd' is restored to the correct calculation result sequence a'b'c'd' of the original input, and the results a+b+c+d, a+b+c, b and a are obtained.

[0033] The application uses the Benes network 1 and the Benes network 2 for auxiliary encryption, which ensures that the order of the input and the output is unchanged, and effectively encrypts the data of the internal circuit of the chip.

[0034] The application can use the Benes network supporting 8 bits for the 1T1R array, and encrypts every 8 rows and 8 columns in the array, so as to further improve the data security. That is, an 8-bit Benes network is added to every 8 rows and 8 columns of the 1T1R array, and every three adjacent Benes networks use the same encryption mode (that is, have the same control signal), so that the storage and bandwidth demand of the control signal are greatly reduced. Only under the action of the corresponding control signal (that is, the key), the correct memory calculation result can be read out, so as to realize the data encryption of the memory calculation chip. The application ensures that the order of the data stream is not affected by the encryption operation, and also ensures the security and confidentiality of the weight data in the chip. Since the power consumption and area of the Benes network itself are very small, this method can realize more efficient and flexible data encryption and permutation protection at the chip level.

[0035] ​The above examples are only used to illustrate the technical solutions of the present application but not to limit the present application, and the ordinary skilled in the art can modify or equivalently replace the technical solutions of the present application without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the claims.

Claims

1. A 1T1R array encryption method based on Benes networks, characterized in that, Several Benes networks 1 are connected to the rows of the 1T1R array, and several Benes networks 2 are connected to the columns of the 1T1R array. The control signals of Benes network 1 and Benes network 2 are used as keys. The control signals of Benes network 1 and Benes network 2 are stored and transmitted separately. The specific steps include the following: 1) Perform a permutation operation on the neural network weights stored in the 1T1R array. Based on the row transformation of the 1T1R array, perform column transformation to achieve encryption. 2) The original input sequence is transformed into a row sequence of a 1T1R array through a Benes network 1 and then input; 3) The 1T1R array performs matrix-vector multiplication and outputs a sequence of calculation results; 4) Replace the calculation result sequence output by the 1T1R array with the calculation result sequence of the original input through the Benes network 2, so as to obtain the correct calculation result of the original input and complete the decryption.

2. The 1T1R array encryption method based on Benes network as described in claim 1, characterized in that, An 8-bit Benes network is connected to every 8 rows of the 1T1R array.

3. The 1T1R array encryption method based on Benes network as described in claim 1, characterized in that, An 8-bit Benes network is connected to every 8 columns of the 1T1R array.

4. The 1T1R array encryption method based on Benes network as described in claim 1, characterized in that, Every three adjacent Benes network 1 or Benes network 2 use the same control signal.

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