A frame synchronization control method and device for display device

Abstract

The embodiment of the present application provides a frame synchronization control method and device for a display device, which is used to realize frame synchronization display. The method includes: obtaining an image signal of a first image frame in a video stream; outputting the image signal of the first image frame to a display device after a delay; determining a first total time length for reading the first image frame according to the image signal of the first image frame and a reference clock; adjusting the multiplication frequency of the phase-locked loop of the control device according to the first total time length and the frequency of the reference clock to obtain the output frequency of the phase-locked loop at the multiplication frequency; adjusting the clock control signal used to output a second image frame to the display device according to the output frequency; the second image frame is the next image frame to be displayed adjacent to the first image frame of the video stream.

Description

Technical Field

[0001] The present application relates to the field of frame synchronization display technology, and in particular to a frame synchronization control method and device for a display device. Background Art

[0002] For frame synchronization display, the output frame rate needs to be consistent with the input frame rate, that is, the development area of ​​each frame of the output image and the development area of ​​the input image need to maintain a relatively fixed delay in time. For a display device, in the process of parsing the input image, the local clock is generally used to generate pixel_clock, which can ensure that H_active, V_active and frame_rate are stable. However, since the pixel_clock of the signal source end of the input image is not homologous, and the frame_rate and the position of the development area must be consistent, the H_total and V_total of the output image will have a certain jitter to meet the difference between the source end and the local pixel_clock. In addition, for some non-standard signal sources, the H total and V total of the image it emits will jitter.

[0003] Therefore, in the prior art, it is difficult to achieve frame synchronization display while keeping the output H Total and V Total absolutely stable. Summary of the invention

[0004] The embodiments of the present application provide a frame synchronization control method and apparatus for a display device, so as to realize frame synchronization display.

[0005] In a first aspect, an embodiment of the present application provides a frame synchronization control method of a display device, which is applied to a control device, comprising:

[0006] Acquire an image signal of a first image frame in a video stream; and output the image signal of the first image frame to a display device after a delay;

[0007] determining a first total duration for reading the first image frame according to an image signal of the first image frame and a reference clock;

[0008] adjusting the frequency multiplication of the phase-locked loop of the control device according to the first total duration and the frequency of the reference clock to obtain an output frequency of the phase-locked loop at the frequency multiplication;

[0009] The clock control signal used to output a second image frame to the display device is adjusted according to the output frequency; the second image frame is an image frame to be displayed next to the first image frame of the video stream.

[0010] Through the above scheme, the output frequency of the phase-locked loop is determined by the image signal of the image, and then the clock signal is adjusted by the output frequency, so that the ratio of the development area of ​​the output image and the development area of ​​the input image is consistent, that is, the frame rate of the output image and the input image is consistent, and at the same time, the output H_total and V_total can be kept absolutely stable.

[0011] In a possible implementation, adjusting the frequency multiplication of the phase-locked loop of the control device according to the first total duration and the frequency of the reference clock includes:

[0012] Determine the total number of pixel rows in columns when the display device outputs the first image frame;

[0013] Determine a clock period of a crystal oscillator clock of a phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock;

[0014] The frequency multiplication of the phase-locked loop is determined according to the clock period and the frequency of the crystal oscillator clock.

[0015] In a possible implementation manner, determining the total number of column pixel rows when the display device outputs the first image frame includes:

[0016] Determine the number of column effective pixels, the first duration of row effective pixels, and the second duration of a field blanking signal of the first image frame according to the image signal of the first image frame, wherein the first duration and the second duration are represented by the number of clock cycles of the reference clock;

[0017] The total number of column pixel rows of the display device when outputting the first image frame is determined according to the number of effective pixels in the column, the first duration, the second duration, and the number of effective pixels in the row displaying the first image frame.

[0018] In a possible implementation, determining a clock period of a crystal oscillator clock of a phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock includes:

[0019] Determine a first delay time length corresponding to the delay, wherein the first delay time length is characterized by the number of clock cycles of the crystal oscillator clock;

[0020] Determine a second total duration of the first image frame, wherein the second duration is represented by the number of clock cycles of a crystal oscillator clock;

[0021] The clock period of the crystal oscillator clock of the phase-locked loop is determined according to the first delay time, the total number of pixel rows in the column, the first total time, and the second total time.

[0022] In a possible implementation manner, before determining a clock period of a crystal oscillator clock of a phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock, the method further includes:

[0023] Determine a time difference between a time length of the first image frame and a time length of a third image frame; the third image frame is a previous image frame adjacent to the first image frame;

[0024] Determining a clock period of a crystal oscillator clock of a phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock includes:

[0025] Determine a third total duration for outputting the first image frame according to the first total duration and the duration difference;

[0026] The clock period of the crystal oscillator clock is determined according to the third total time length and the frequency of the reference clock.

[0027] In a second aspect, an embodiment of the present application provides a frame synchronization control device for a display device, comprising:

[0028] An acquisition module, configured to acquire an image signal of a first image frame in a video stream; and output the image signal of the first image frame to a display device after a delay;

[0029] a determination module, configured to determine a first total duration for reading the first image frame according to an image signal of the first image frame and a reference clock;

[0030] adjusting the frequency multiplication of the phase-locked loop of the control device according to the first total duration and the frequency of the reference clock to obtain an output frequency of the phase-locked loop at the frequency multiplication;

[0031] An adjustment module is used to adjust the clock control signal used to output a second image frame to the display device according to the output frequency; the second image frame is the next image frame to be displayed adjacent to the first image frame of the video stream.

[0032] In a possible implementation manner, when the adjustment module adjusts the frequency multiplication of the phase-locked loop of the control device according to the first total duration and the frequency of the reference clock, it is specifically configured to:

[0033] Determine the total number of pixel rows in columns when the display device outputs the first image frame;

[0034] Determine a clock period of a crystal oscillator clock of a phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock;

[0035] The frequency multiplication of the phase-locked loop is determined according to the clock period and the frequency of the crystal oscillator clock.

[0036] In a possible implementation manner, the adjustment module, when determining the total number of column pixel rows when the display device outputs the first image frame, is specifically configured to:

[0037] Determine the number of column effective pixels, the first duration of row effective pixels, and the second duration of a field blanking signal of the first image frame according to the image signal of the first image frame, wherein the first duration and the second duration are represented by the number of clock cycles of the reference clock;

[0038] The total number of column pixel rows of the display device when outputting the first image frame is determined according to the number of effective pixels in the column, the first duration, the second duration, and the number of effective pixels in the row displaying the first image frame.

[0039] In a third aspect, an embodiment of the present application provides an execution device, including:

[0040] A memory for storing program instructions;

[0041] The processor is used to call the program instructions stored in the memory, and execute the method described in the first aspect and different implementation methods of the first aspect according to the obtained program instructions.

[0042] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium includes computer instructions, and when the computer program instructions are executed by a computer, the computer executes the method described in the first aspect and different implementation methods of the first aspect.

[0043] In addition, the beneficial effects brought about by the second to fourth aspects and different implementation methods can be found in the first aspect and the different implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0045] Figure 1 A schematic diagram of a business system provided in an embodiment of the present application;

[0046] Figure 2 A schematic diagram of a frame synchronization display provided by an embodiment of the present application;

[0047] Figure 3A control flow chart of frame synchronization display of a display device provided in an embodiment of the present application;

[0048] Figure 4 A schematic diagram of the structure of a control device provided in an embodiment of the present application;

[0049] Figure 5 A schematic diagram of input timing detection provided in an embodiment of the present application;

[0050] Figure 6 A schematic diagram of a mapping relationship between an input domain and an output image provided in an embodiment of the present application;

[0051] Figure 7 A schematic diagram of a frame synchronization calculation principle provided in an embodiment of the present application;

[0052] Figure 8 A schematic diagram of inter-frame calculation compensation provided in an embodiment of the present application;

[0053] Fig. 9 A schematic diagram of a control device for frame synchronization display of a display device provided in an embodiment of the present application;

[0054] Fig.10 A schematic diagram of an execution device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0056] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0057] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0058] For the Scaler chip, frame synchronization display is a necessary condition for achieving low-latency display mode. To achieve frame synchronization display, the output frame rate needs to be consistent with the input frame rate. In order to use less data storage space during image processing, it is necessary to keep the development area of ​​each frame of the output image and the development area of ​​the input image with a relatively fixed delay in time. Figure 1 As shown, the delay between the development area of ​​the input image and the development area of ​​the output image is kept constant, ensuring frame synchronization display.

[0059] For a display device, the source of the input image can be an image signal from different interfaces such as HDMI or DP. In the process of parsing the input image, the local clock is generally used to generate pixel_clock. This method can ensure that H_active, V_active and frame_rate are stable. However, since the pixel_clock at the signal source end of the input image is not homologous, and the frame_rate and the position of the developing area must be consistent, the H_total and V_total of the output image will have a certain jitter to meet the difference between the source end and the local pixel_clock. For some non-standard signal sources, the image H total and V total it emits will jitter. However, for the screen end, the jitter of Htotal or V total that it can tolerate is limited, and it may even require H Total and V Total to be absolutely stable. Therefore, the existing technical solutions, based on frame synchronization display, are difficult to ensure that the output H Total and V Total remain absolutely stable.

[0060] Based on the above problems, an embodiment of the present application provides a frame synchronization control method and device for a display device. After acquiring the image signal of the image frame, the duration of the image frame is determined based on the reference clock, and the frequency multiplication factor of the phase-locked loop is determined according to the duration of the image frame, the frequency and clock period of the reference clock, and the frequency of the crystal oscillator clock of the phase-locked loop. Further, the output frequency of the phase-locked loop under the frequency multiplication factor is determined, and the clock control signal used to output the image frame to the display device is adjusted according to the output frequency. Through the above scheme, the output frequency of the phase-locked loop is determined by the image signal of the image, and then the clock signal is adjusted by the output frequency, so that the ratio of the development area of ​​the output image and the development area of ​​the input image remains consistent, that is, the frame rate of the output image and the input image is consistent, and at the same time, the output H_total and V_total can be kept absolutely stable.

[0061] In order to better understand the solution of the present application, the usage scenarios of the present application are introduced below.

[0062] Reference Figure 2 FIG. 2 is a schematic diagram of a frame synchronization display service system 200 provided in an embodiment of the present application. The service system 200 includes a collection device 300 , a control device 400 and a display device 500 .

[0063] The acquisition device 300 is used to acquire image data and input the image data into the control device 400 .

[0064] In some embodiments, the image data in the same video stream may be acquired by different acquisition devices 300 , so the pixel clocks of the image data received by the control device 400 are from different sources, and thus the frame rates between different image frames may be different.

[0065] The control device 400 is used to receive a video stream, determine the corresponding output frequency for each image frame in the received video stream, and adjust the clock control signal used to output the image frame to the display device 500 based on the output frequency, so that the corresponding area of ​​the input image and the corresponding area of ​​the output image maintain a relatively fixed delay in time.

[0066] The display device 500 is used to display image data.

[0067] It should be understood that Figure 2 The structure shown is only a schematic diagram of the structure of the business system 200. The business system 200 may also include Figure 2 More or fewer components as shown, or with Figure 2 Different configurations are shown. Figure 2 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0068] The solution provided by the embodiments of the present application is described below in conjunction with the accompanying drawings.

[0069] This embodiment provides an image processing method. Figure 3 The flow of a frame synchronization control method for a display device is exemplarily shown. The method can be implemented by a control device 400. For the convenience of description, the identification of each device will not be exemplified in the following.

[0070] 301 , obtaining an image signal of a first image frame in a video stream, and outputting the image signal of the first image frame to a display device after delay.

[0071] 302 : Determine a first total duration for reading the first image frame according to an image signal of the first image frame and a reference clock.

[0072] In some embodiments, the image signal of the first image frame may be counted by a reference clock to determine a first total duration of reading the first image frame, wherein the first total duration is represented by the number of clock cycles of the reference clock.

[0073] 303 , adjusting the frequency multiplication of a phase-locked loop of a control device according to the first total duration and the frequency of a reference clock to obtain an output frequency of the phase-locked loop at the multiplication.

[0074] In some embodiments, when the frequency multiplication of the phase-locked loop of the control device is adjusted according to the first total duration and the frequency of the reference clock, it can be achieved in the following manner: determine the total number of columns and rows of pixels when the display device outputs the first image frame. Specifically, the number of effective pixels in the columns of the first image frame, the first duration of effective pixels in the rows, and the second duration of the field blanking signal can be determined according to the image signal of the first image frame, and the first duration and the second duration are represented by the number of clock cycles of the reference clock;

[0075] The total number of column pixel rows of the display device when outputting the first image frame is determined according to the number of column valid pixels, the first duration, the second duration, and the number of row valid pixels displaying the first image frame.

[0076] Further, the clock period of the crystal oscillator clock of the phase-locked loop can be determined according to the total number of pixel rows in the column, the first total duration, and the frequency of the reference clock. Specifically, the first moment of reading the video stream and the second moment of outputting the first image frame to the display device can be obtained, and the difference between the first moment and the second moment is used as the delay. The first delay duration corresponding to the delay is determined, and the first delay duration is characterized by the number of clock cycles of the crystal oscillator clock. Further, the second total duration of the first image frame can be determined, and the second duration is characterized by the number of clock cycles of the crystal oscillator clock; and the clock period of the crystal oscillator clock of the phase-locked loop is determined according to the first delay duration, the total number of pixel rows in the column, the first total duration, and the second total duration.

[0077] In some embodiments, after the clock cycle is determined, the frequency multiplication of the phase-locked loop can be determined according to the clock cycle and the frequency of the crystal oscillator clock, and the output frequency of the phase-locked loop can be determined according to the corresponding relationship between the frequency multiplication and the output frequency.

[0078] 304 , adjusting a clock control signal used to output a second image frame to a display device according to the output frequency; the second image frame is an image frame to be displayed next to the first image frame of the video stream.

[0079] In some embodiments, before determining the clock period of the crystal oscillator clock of the phase-locked loop according to the total number of column pixel rows, the first total time length, and the frequency of the reference clock, the time length difference between the time length of the first image frame and the time length of the third image frame may also be determined; the third image frame is a previous image frame adjacent to the first image frame;

[0080] Determining the clock period of the crystal oscillator clock of the phase-locked loop based on the total number of column pixel rows, the first total duration and the frequency of the reference clock can be achieved in the following way: determining the third total duration for outputting the first image frame based on the first total duration and the duration difference; determining the clock period of the crystal oscillator clock based on the third total duration and the frequency of the reference clock.

[0081] The frame synchronization control method of the display device proposed in the present application is described in detail below in conjunction with specific embodiments.

[0082] In the present application, the control device 400 may include an input timing detection module 401, a parameter calculation module 402, an output timing generation module 403, a control state machine module 404 and a data cache module 405. Figure 4 shown.

[0083] The input timing detection module 401 is used to output the sequence information and calculate the total number of pixel rows (V_total) of the output image. In this application, the total number of pixel rows (V_total) is the sum of the total number of rows in the developing area and the total number of rows in the field blanking.

[0084] The parameter calculation module 402 is used to calculate the frequency multiplication and adjust the output frequency of the phase-locked loop according to the frequency multiplication.

[0085] The output timing generation module 403 is used to generate timing information of the output signal according to the output frequency of the phase-locked loop.

[0086] The control state machine module 404 is used to determine whether frame synchronization is achieved.

[0087] The data cache module 405 is used for data cache of input data and output data.

[0088] The following describes the principle of the frame synchronization control method of the display device in the present application in modules. For the convenience of description, the serial numbers of the modules are no longer identified.

[0089] In some embodiments, the input timing detection module detects the timing information of the input signal through a reference clock ref_clk, where ref_clk is a clock with a known frequency.

[0090] The input detection module can determine multiple measurement values ​​based on the frame synchronization signal (rx_vs) and the row data valid signal (rx_de) of the input signal, such as Figure 5 As shown, specifically:

[0091] rx_vact: The number of column valid pixels V_active of the signal of the input image, that is, the number of de between two vs in rx_vs.

[0092] Cycle_refclk_hact: The duration of the H_act signal of the last row of valid pixels in each frame of the input image is counted by ref_clk, starting from the rising edge of the last row of the first frame and ending at the falling edge of the last row of the first frame.

[0093] Cycle_refclk_vblank: The field blanking V_blank duration of the input image is counted by ref_clk, starting from the falling edge of the last line of the first frame and ending at the rising edge of the first line of the second frame.

[0094] Cycle_refclk_vtotal: V_total duration of the input image, counted by ref_clk, starting from the rising edge of the first line of the first frame and ending at the rising edge of the first line of the second frame.

[0095] Further, the total number of columns of pixels (tx_vtotal) of the output image is determined according to the above measurement values. Specifically, the total number of columns of pixel rows (rx_vtotal) of the input image can be determined first, and the total number of columns of pixel rows (tx_vtotal) of the output image can be determined according to the proportional relationship between the input image and the output image.

[0096] As an example, the total number of pixel rows in the columns of the input image satisfies the conditions described in the following formula:

[0097]

[0098] Furthermore, the total number of pixel rows in the output image, i.e., tx_vtotal, can be obtained according to the proportional relationship between the input image V_active and the output image V_active. Figure 6In some embodiments, the total number of pixel rows in the columns of the output image satisfies the condition shown in the following formula:

[0099]

[0100] By using the above method, V_total of the output image displayed by the display device can be determined so that the ratio of the development area of ​​the image and the development area of ​​the input image can be kept consistent.

[0101] The parameter calculation module needs to count the difference between the actual number of pixel clock cycles output and the ideal number of pixel clock cycles in the detection time window, and calculate the number of pixel clock cycles actually required in the frequency compensation time window, so as to calculate the target value of the pixel clock pix clock frequency, and then derive the value of the frequency multiplier fbdiv, such as Figure 7 shown.

[0102] In some embodiments, the frequency multiplication factor fbdiv can be accurate to the maximum decimal range supported by the phase-locked loop PLL, and the PLL output frequency can be adjusted in real time.

[0103] As an example, the rising edge of the first line of the input image to the rising edge of the first line of the second frame of the input image is used as the detection time window. The rising edge of the first line of the second frame of the input image to the predicted rising edge of the first line of the third frame of the output image is used as the frequency compensation time window. Among them, the frequency compensation time window is determined based on the detection time window of the first frame and the time delay between the image input moment and the output moment. In the present application, the total duration of the current frame can be used to predict the total duration of the previous frame, and after reading the current frame, the difference between the actual total duration of the current frame and the total duration of the previous frame is compensated in the next frame, and the current frame is predicted as the predicted duration of the next frame. In the present application, each frame is calculated once and adjusted once.

[0104] In some embodiments, the following parameters are stored in the register: tx_htotal: H_total of the output image, the pre divider value of the PLL, the post divider value of the PLL, the frequency of ref_clk (freq_refclk), the frequency of the reference clock of the PLL freq_oscclk (in this embodiment, the crystal oscillator clock osc_clk is used as the reference clock of the PLL), and the set ideal target delay from rx_de to tx_de (Cycle_refclk_delay).

[0105] In some embodiments, the length of one frame of the input image may be determined directly by the crystal oscillator clock, starting from the rising edge of the first line of the first frame to the rising edge of the first line of the second frame, which is recorded as Cycle_txclk_vtotal.

[0106] The delay between the output image and the input image is determined by the crystal clock, starting from the rising edge of the first line of the input image and ending at the rising edge of the first line of the output image, denoted as Cycle_txclk_delay.

[0107] In the specific calculation, the following formula is satisfied:

[0108] At the beginning of the calculation:

[0109] Cycle_refclk_vtotal*T_refclk=TX_htotal*TX_vtotal*T_txclk

[0110] T_txclk=Cycle_refclk_vtotal*T_refclk / (TX_htotal*TX_vtotal)

[0111] Fbdiv=T_oscclk*predic*postdiv / T_txclk=T_oscclk*predic*postdiv / (Cycle_ref clk_vtotal*T_refclk / (TX_htotal*TX_vtotal))

[0112] =Freq_refclk*predic*postdiv*(TX_htotal*TX_vtotal) / (Freq_oscclk*Cycle_refclk_vtotal)

[0113] Starting from the second frame:

[0114] The estimated duration from vclr of the second frame (the rising edge of the first row of de in the second frame) to vclr_delay of the third frame (plus the rising edge of the first row of de in the third frame after the delay), the total number of cycles of the reference clock is Cycle_refclk_vtotal+Cycle_refclk_delay.

[0115] The total number of output image clock cycles is 2TX_htotal*TX_vtotal-(Cycle_txclk_vtotal-Cycle_txclk_delay).

[0116] (Cycle_refclk_vtotal+Cycle_refclk_delay)*T_refclk=(2TX_htotal*TX_vtotal+Cycle_txclk_delay-Cycle_txclk_vtotal)

[0117] T_txclk=(2TX_htotal*TX_vtotal+Cycle_txclk_delay-Cycle_txclk_vtotal) / (Cycle_refclk_vtotal+Cycle_refclk_delay)

[0118] Fbdiv=T_oscclk*predic*postdiv / T_txclk

[0119] =T_oscclk*predic*postdiv*(2TX_htotal*TX_vtotal+Cycle_txclk_delay-Cycle_txclk_vtotal) / (T_refclk*(Cycle_refclk_vtotal+Cycle_refclk_delay))

[0120] =Freq_refclk*predic*postdiv*(2TX_htotal*TX_vtotal+Cycle_txclk_delay-Cyc le_txclk_vtotal) / (Freq_oscclk*(Cycle_refclk_vtotal+Cycle_refclk_delay))

[0121] After determining the frequency multiplication, the output frequency can be determined by the following formula:

[0122] The output frequency of PLL = the input frequency of PLL * Fbdiv / postdiv.

[0123] As an example, Figure 8 As shown, the window where Frame0 is located is used as the detection time window 1, the duration of Frame0 is determined, and the duration of Frame0 is used as the predicted duration of Frame1, where the duration of the calculated compensation time window 1 is the duration of Frame0 plus the duration of the delay. After the real Frame1 arrives, the window where Frame1 is located is used as the detection time window 2 to determine the duration of Frame1. According to the difference between the duration of Frame0 and the duration of Frame1, the position of the predicted Frame2 is corrected in the calculated compensation time window.

[0124] For example, the duration of Frame0 is 0.10 seconds, and the delay between the input image and the output image is 0.03 seconds. Then the duration of the compensation time window 1 is calculated to be Frame0+delay=0.13 seconds. At this time, the output frequency is adjusted. And it is predicted that Frame2 will be output at 0.23 seconds. However, after Frame1 arrives, it is detected that the duration of Frame1 is 0.12 seconds, which is 0.02 seconds more than the predicted 0.10 seconds. The length of the compensation time window is calculated to be Frame1+delay+0.02=0.17 seconds. At this time, the extra 0.02 seconds is output first, and then Frame2 is output to correct the position of Frame2. Then the start time of the corrected Frame2 is 0.25 seconds.

[0125] Therefore, in this application, if the frame rate of the input image changes, the detection time window will change, and the predicted position of the next frame will be corrected. Therefore, if the input frame rate changes slightly, the pixel frequency can be corrected immediately to ensure the stability of the output timing.

[0126] In some embodiments, the output timing generation module is used to generate an output timing signal. The generation of the first frame and the first line is generated according to the rising edge delay Cycle_refclk_delay of the first frame and the first line of the input image. Then, the timing of each frame and each line is continuously generated according to the set tx_hactive, tx_vactive, tx_htotal, and the calculated tx_vtotal.

[0127] The data cache module is used to store the delayed data between the input image and the output image, so that the image data can be continuously and stably output even when the frame rate of the input image changes slightly.

[0128] The control state machine module is used to monitor whether the input timing is normal, whether the time delay between the output image and the input image changes, and whether the number of data caches is within the normal range. If any of the above items is detected to be abnormal, it means that the frame synchronization has failed. It is necessary to confirm whether the frame rate of the input image is stable. After it is stable, a new synchronization process will be started again.

[0129] Based on the same technical concept, see Fig. 9 As shown, the embodiment of the present application provides a frame synchronization control device 900 for a display device. The device 900 can perform any step in the frame synchronization control method for the display device described above, and will not be described here to avoid repetition. The device 900 includes an acquisition module 901, a determination module 902, and an adjustment module 903.

[0130] An acquisition module 901 is used to acquire an image signal of a first image frame in a video stream; and output the image signal of the first image frame to a display device after a delay;

[0131] A determination module 902, configured to determine a first total duration for reading the first image frame according to an image signal of the first image frame and a reference clock;

[0132] adjusting the frequency multiplication of the phase-locked loop of the control device according to the first total duration and the frequency of the reference clock to obtain an output frequency of the phase-locked loop at the frequency multiplication;

[0133] The adjustment module 903 is used to adjust the clock control signal used to output a second image frame to the display device according to the output frequency; the second image frame is the next image frame to be displayed adjacent to the first image frame of the video stream.

[0134] In some embodiments, the adjustment module 903, when adjusting the frequency multiplication of the phase-locked loop of the control device according to the first total duration and the frequency of the reference clock, is specifically configured to:

[0135] Determine the total number of pixel rows in columns when the display device outputs the first image frame;

[0136] Determine a clock period of a crystal oscillator clock of a phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock;

[0137] The frequency multiplication of the phase-locked loop is determined according to the clock period and the frequency of the crystal oscillator clock.

[0138] In some embodiments, the adjustment module 903, when determining the total number of pixel rows in a column when the display device outputs the first image frame, is specifically configured to:

[0139] Determine the number of column effective pixels, the first duration of row effective pixels, and the second duration of a field blanking signal of the first image frame according to the image signal of the first image frame, wherein the first duration and the second duration are represented by the number of clock cycles of the reference clock;

[0140] The total number of column pixel rows of the display device when outputting the first image frame is determined according to the number of effective pixels in the column, the first duration, the second duration, and the number of effective pixels in the row displaying the first image frame.

[0141] In some embodiments, the adjustment module 903, when determining the clock period of the crystal oscillator clock of the phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock, is specifically used to:

[0142] Determine a first delay time length corresponding to the delay, wherein the first delay time length is characterized by the number of clock cycles of the crystal oscillator clock;

[0143] Determine a second total duration of the first image frame, where the second total duration is represented by the number of clock cycles of a crystal oscillator clock;

[0144] The clock period of the crystal oscillator clock of the phase-locked loop is determined according to the total number of pixel rows in the column of the first delay time, the first total time, and the second total time.

[0145] In some embodiments, before determining the clock period of the crystal oscillator clock of the phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock, the determining module 902 is further configured to:

[0146] Determine a time difference between a time length of the first image frame and a time length of a third image frame; the third image frame is a previous image frame adjacent to the first image frame;

[0147] The determination module 902, when determining the clock period of the crystal oscillator clock of the phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock, is specifically configured to:

[0148] Determine a third total duration for outputting the first image frame according to the first total duration and the duration difference;

[0149] The clock period of the crystal oscillator clock is determined according to the third total time length and the frequency of the reference clock.

[0150] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which can realize the function of the frame synchronization control device of the display device discussed above, please refer to Fig.10 , the device includes a processor 1002 and a memory 1001.

[0151] Memory 1001, used for storing program instructions;

[0152] The processor 1002 is used to call the program instructions stored in the memory, and execute any step of the frame synchronization control method of the display device according to the obtained program instructions.

[0153] In the embodiment of the present application, the processor 1002 is the control center of the electronic device, which connects various parts of the electronic device using various interfaces and routes, executes various functions of the electronic device and processes data by running or executing software programs / or modules stored in the memory 1001, and calling data stored in the memory 1001. Optionally, the processor 1002 may include one or more processing units. The processor 1002 may be, for example, a control component such as a processor, a microprocessor, a controller, and may be, for example, a general-purpose central processing unit (CPU), a general-purpose processor, a digital signal processing (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0154] The memory 1001 can be used to store software programs and modules, and the processor 1002 executes various functional applications and data processing by running the software programs and modules stored in the memory 1001. The memory 1001 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function, etc.; the data storage area may store data created according to business processing, etc. The memory 1001, as a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 1001 may include at least one type of storage medium, for example, it may include flash memory, hard disk, multimedia card, card-type memory, random access memory (Random Access Memory, RAM), static random access memory (Static Random Access Memory, SRAM), programmable read only memory (Programmable Read Only Memory, PROM), read only memory (Read Only Memory, ROM), electrically erasable programmable read only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), magnetic memory, disk, optical disk, etc. The memory 1001 is any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1001 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0155] Based on the same inventive concept, the embodiment of the present application provides a computer-readable storage medium, and the computer program product includes: computer program code, when the computer program code is executed on a computer, the computer executes the frame synchronization control method of any display device discussed above. Since the principle of solving the problem by the above-mentioned computer-readable storage medium is similar to the frame synchronization control method of the display device, the implementation of the above-mentioned computer-readable storage medium can refer to the implementation of the method, and the repeated parts will not be repeated.

[0156] Based on the same inventive concept, the embodiment of the present application further provides a computer program product, which includes: computer program code, when the computer program code is run on a computer, the computer executes the frame synchronization control method of the display device as discussed above. Since the principle of solving the problem by the above computer program product is similar to that of the frame synchronization control method of the display device, the implementation of the above computer program product can refer to the implementation of the method, and the repeated parts will not be repeated.

[0157] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0158] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0159] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0160] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0161] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A frame synchronization control method for a display device, characterized in that: Applied to control equipment, including: Acquire an image signal of a first image frame in a video stream, and output the image signal of the first image frame to a display device after delay; determining a first total duration for reading the first image frame according to an image signal of the first image frame and a reference clock; adjusting the frequency multiplication of the phase-locked loop of the control device according to the first total duration and the frequency of the reference clock to obtain an output frequency of the phase-locked loop at the frequency multiplication; A clock control signal used to output a second image frame to the display device is adjusted according to the output frequency; the second image frame is an image frame to be displayed next to the first image frame of the video stream.

2. The method according to claim 1, characterized in that The step of adjusting the frequency multiplication of the phase-locked loop of the control device according to the first total duration and the frequency of the reference clock includes: Determine the total number of pixel rows in columns when the display device outputs the first image frame; Determine a clock period of a crystal oscillator clock of a phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock; The frequency multiplication of the phase-locked loop is determined according to the clock period and the frequency of the crystal oscillator clock.

3. The method according to claim 2, characterized in that The determining the total number of pixel rows in columns when the display device outputs the first image frame includes: Determine the number of column effective pixels, the first duration of row effective pixels, and the second duration of a field blanking signal of the first image frame according to the image signal of the first image frame, wherein the first duration and the second duration are represented by the number of clock cycles of the reference clock; The total number of column pixel rows of the display device when outputting the first image frame is determined according to the number of effective pixels in the column, the first duration, the second duration, and the number of effective pixels in the row displaying the first image frame.

4. The method according to claim 2, characterized in that The step of determining a clock period of a crystal oscillator clock of a phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock comprises: Determine a first delay time length corresponding to the delay, wherein the first delay time length is characterized by the number of clock cycles of the crystal oscillator clock; Determine a second total duration of the first image frame, where the second total duration is represented by the number of clock cycles of a crystal oscillator clock; The clock period of the crystal oscillator clock of the phase-locked loop is determined according to the total number of pixel rows in the column of the first delay time, the first total time, and the second total time.

5. The method according to claim 2, characterized in that Before determining a clock period of a crystal oscillator clock of a phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock, the method further includes: Determine a time difference between a time length of the first image frame and a time length of a third image frame; the third image frame is a previous image frame adjacent to the first image frame; Determining a clock period of a crystal oscillator clock of a phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock includes: Determine a third total duration for outputting the first image frame according to the first total duration and the duration difference; The clock period of the crystal oscillator clock is determined according to the third total time length and the frequency of the reference clock.

6. A frame synchronization control device for a display device, characterized in that: include: An acquisition module, used for acquiring an image signal of a first image frame in a video stream; outputting the image signal of the first image frame to a display device after delay; a determination module, configured to determine a first total duration for reading the first image frame according to an image signal of the first image frame and a reference clock; adjusting the frequency multiplication of the phase-locked loop of the control device according to the first total duration and the frequency of the reference clock to obtain an output frequency of the phase-locked loop at the frequency multiplication; an adjustment module, configured to adjust the clock control signal used to output the second image frame to the display device according to the output frequency; The second image frame is an image frame to be displayed next to the first image frame of the video stream.

7. The device according to claim 6, characterized in that The adjustment module, when adjusting the frequency multiplication of the phase-locked loop of the control device according to the first total duration and the frequency of the reference clock, is specifically used to: Determine the total number of pixel rows in columns when the display device outputs the first image frame; Determine a clock period of a crystal oscillator clock of a phase-locked loop according to the total number of pixel rows in the column, the first total time length, and the frequency of the reference clock; The frequency multiplication of the phase-locked loop is determined according to the clock period and the frequency of the crystal oscillator clock.

8. The device according to claim 7, characterized in that The adjustment module, when determining the total number of pixel rows in a column when the display device outputs the first image frame, is specifically used to: Determine the number of column effective pixels, the first duration of row effective pixels, and the second duration of a field blanking signal of the first image frame according to the image signal of the first image frame, wherein the first duration and the second duration are represented by the number of clock cycles of the reference clock; The total number of column pixel rows of the display device when outputting the first image frame is determined according to the number of effective pixels in the column, the first duration, the second duration, and the number of effective pixels in the row displaying the first image frame.

9. An execution device, characterized in that: include: A memory for storing program instructions; A processor is used to call the program instructions stored in the memory, and execute the method according to any one of claims 1 to 5 according to the obtained program instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium comprises computer program instructions, and when the computer program instructions are executed by a computer, the computer is caused to perform the method according to any one of claims 1 to 5.

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