Distributed base station system

Abstract

The invention relates to the technical field of communication, in particular to a distributed base station system, which at least comprises a plurality of baseband chips, a plurality of base station modules, a plurality of base station modules, a plurality of base station modules, a plurality of base station modules and a plurality of base station modules, a first data end of the field programmable gate array chip is respectively connected with the plurality of baseband chips through optical fibers and performs data interaction with the baseband chips through a JESD protocol; a first data end and a second data end of the network switching equipment are respectively in communication connection with the plurality of baseband chips, and the network switching equipment is used for realizing data interaction between a core network and the baseband chips; the first data end of the front panel device is in communication connection with the second data end of the field programmable gate array chip, and the front panel device is used for transmitting data sent by the field programmable gate array chip to the air interface through the radio frequency antenna, so that a mobile access service function is provided. The distributed base station system is lower in cost on the premise that the overall performance is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular, to a distributed base station system. Background Art

[0002] At present, 5G base stations have weak signal coverage and unstable networks, especially in remote residences with severe building obstructions or insufficient macro base station signal coverage. And with the continuous increase in online live broadcast, education, games, cloud VR / AR and other services, the deployment of small distributed base stations will increase. Compared with conventional macro base stations or indoor base stations, small base stations are low-cost and can be deployed quickly and flexibly to meet the coverage needs of a certain area. Distributed small base stations can flexibly increase or decrease RRU (Remote Radio Unit) or antennas according to actual needs to adapt to changes in different coverage ranges and user densities.

[0003] In the traditional distributed base station solution, the connection solution between UCP4008 (a chip with a highly integrated general-purpose processing core and a domestically produced high-performance digital baseband core) and FPGA (Field-Programmable Gate Array) and RRU is that the UCP4008 and FPGA transmit data through the CPRI (Common Public Radio Interface) protocol, and then the FPGA and RRU also transmit data through the CPRI protocol, so that data can be transmitted from the UCP4008 chip to the RRU, and then sent to the user to complete the data interaction between the base station and the user. At present, the traditional base station solution is a distributed solution based on CPRI and eCPRI. These two transmission methods have high requirements for CPRI, eCPRI transmission rate, number of interfaces and FPGA modules, so the FPGA cost is relatively high. Summary of the invention

[0004] In order to solve the above technical problems, a distributed base station system is provided in an embodiment of the present application.

[0005] A first aspect of an embodiment of the present application provides a distributed base station system, comprising at least:

[0006] Multiple baseband chips, wherein the baseband chips are UCP4008 chips;

[0007] A field programmable gate array chip, wherein the first data end of the field programmable gate array chip is respectively connected to the plurality of baseband chips through optical fibers, and performs data exchange with the baseband chips through a JESD protocol;

[0008] A network switching device, wherein the first data terminal and the second data terminal of the network switching device are respectively connected to the plurality of baseband chips for communication, and the network switching device is used to implement data interaction between the core network and the baseband chips;

[0009] A front panel device, wherein the first data end of the front panel device is communicatively connected to the second data end of the field programmable gate array chip, and the front panel device is used to transmit the data sent by the field programmable gate array chip to the air interface through the radio frequency antenna to provide a mobile access service function.

[0010] In an optional embodiment of the present application, the plurality of baseband chips include at least: a first baseband chip, a second baseband chip, a third baseband chip and a fourth baseband chip; wherein:

[0011] The first baseband chip, the second baseband chip, and the third baseband chip are respectively communicatively connected to the second data end of the network switching device, the fourth baseband chip is communicatively connected to the first data end of the network interaction device, and the fourth baseband chip is used to receive core network data and transmit the core network data to the first baseband chip, the second baseband chip, and the third baseband chip through the network switching device.

[0012] In an optional embodiment of the present application, the fourth baseband chip communicates with the network switching device via a T-MAC protocol; and / or the first baseband chip, the second baseband chip, and the third baseband chip respectively communicate with the network switching device via a T-MAC protocol.

[0013] In an optional embodiment of the present application, the above-mentioned distributed base station system further includes:

[0014] A clock chip, wherein the clock chip is communicatively connected to the first data end of the network switching device, and the clock chip is used to provide a clock synchronization signal to the first baseband chip, the second baseband chip, and the third baseband chip.

[0015] In an optional embodiment of the present application, the first baseband chip and / or the second baseband chip are deployed with multiple TDD NR cells;

[0016] The third baseband chip is deployed with an LTE cell.

[0017] In an optional embodiment of the present application, the number of the TDD NR cells is at least 2; and / or the number of the TDD NR cells is at least 3.

[0018] In an optional embodiment of the present application, the first baseband chip and / or the second baseband chip both carry the physical layer and protocol stack of the TDD NR cell; and / or the third baseband chip carries the physical layer and protocol stack of the LTE cell.

[0019] In an optional embodiment of the present application, the TDD NR cell is a 100M TDD NR cell of 4T4R; and / or, the LTE cell is a 20M LTE FDD cell.

[0020] In an optional embodiment of the present application, the fourth baseband chip is deployed with an OAM functional entity, and the OAM functional entity is used to implement data transmission between the base station and the core network.

[0021] In an optional embodiment of the present application, the front panel is a radio remote unit entity.

[0022] In the first aspect, the first data end of the field programmable gate array chip FPGA of the embodiment of the present application is respectively connected to the multiple baseband chips through optical fibers, and exchanges data with the baseband chips through the JESD protocol, that is, the field programmable gate array chip FPGA is connected to the baseband chip through optical fibers, and exchanges data with the baseband chip through the JESD protocol;

[0023] The traditional JESD (Joint Electronic Device Engineering Council, an international standard for describing and standardizing the transmission process of radio frequency and microwave signals, including descriptions of signal amplitude, phase, frequency change, etc.) is applied to transmit intermediate frequency data between the baseband chip and the Transceiver (RF transceiver). The interface between the baseband and the RF transceiver is an internal interface. In the embodiment of the present application, the data is carried by optical fiber, but the data transmitted in the optical fiber is based on the JESD protocol, and the JESD protocol interface is used to replace the traditional CPRI transmission scheme between UCP4008 and the field programmable gate array chip FPGA. Compared with the CPRI protocol, the mapping method and arrangement of the IQ data (referring to two complex components, namely the orthogonal amplitude components In-phase (I) and Quadrature (Q)) of the JESD protocol are completely different. After the data is arranged, there is no need to compress the data, which can greatly reduce the demand for the number of CPRI interfaces of the field programmable gate array chip FPGA and the demand for the performance of the field programmable gate array chip FPGA, thereby reducing costs. The embodiment of the present application achieves rapid deployment by applying the integrated base station of the UCP4008 chip to the distributed base station solution.

[0024] Secondly, the data arrangement methods of the JESD protocol interface and the CPRI protocol interface are completely different. Since the JESD solution does not need to compress the data, it does not need to reserve space for compressed information at the front end like the CPRI protocol, saving data space. In addition, the data of the JESD protocol interface is arranged in sequence according to the antennas from 0 to 3, and the arrangement method is simpler. It has lower requirements on the number and performance of the field programmable gate array chip FPGA interface, and any field programmable gate array chip FPGA with lower configuration can be flexibly selected according to actual needs, greatly reducing the cost of the field programmable gate array chip FPGA and the cost of the overall system. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0026] Figure 1 It is a schematic diagram of the interaction structure of a traditional distributed base station system;

[0027] Figure 2 A schematic diagram of the structure of a distributed base station system provided in an embodiment of the present application;

[0028] Figure 3 This is a schematic diagram of the data arrangement of the traditional CPRI protocol interface;

[0029] Figure 4 A schematic diagram of data arrangement corresponding to different antennas of the JESD protocol interface in the distributed base station system provided in an embodiment of the present application;

[0030] Figure 5 A schematic diagram of the data arrangement of the JESD protocol interface in the distributed base station system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In the process of implementing this application, the applicant discovered that the cost of FPGA in the current distributed base stations is relatively high.

[0032] In view of the above problems, a distributed base station system is provided in the embodiments of the present application. In order to make the purpose, technical solution and advantages of the present application clearer, the following embodiments and the accompanying drawings further describe a distributed base station system of the present application in detail. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0033] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings). In the description of this application, it should be understood that the orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. are based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to this application.

[0034] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0035] At present, 5G base stations have weak signal coverage and unstable networks, especially in remote residences with severe building obstructions or insufficient macro base station signal coverage. And with the continuous increase in online live broadcast, education, games, cloud VR / AR and other services, the deployment of small distributed base stations will increase. Compared with conventional macro base stations or indoor base stations, small base stations are low-cost and can be deployed quickly and flexibly to meet the coverage needs of a certain area. Distributed small base stations can flexibly increase or decrease RRU (Remote Radio Unit) or antennas according to actual needs to adapt to changes in different coverage ranges and user densities.

[0036] In the traditional distributed base station solution, the connection solution between the UCP4008 chip (a chip with a highly integrated general-purpose processing core and a domestically produced high-performance digital baseband core) and the FPGA (Field-Programmable Gate Array) and the RRU is that the UCP4008 and FPGA transmit data through the CPRI (Common Public Radio Interface) protocol, and then the FPGA and RRU also use the CPRI protocol, so that data can be transmitted from the UCP4008 chip to the RRU, and then sent to the user to complete the data interaction between the base station and the user. The current traditional base station solution is a distributed solution based on CPRI and eCPRI. These two transmission methods have high requirements for CPRI, eCPRI transmission rates, number of interfaces and FPGA modules, so the FPGA cost is relatively high.

[0037] See also Figure 2 In view of the above problems, the embodiment of the present application provides a distributed base station system, which at least includes: a baseband chip, a field programmable gate array chip FPGA, a network switching device switch and a front panel device, wherein:

[0038] The number of the baseband chips is multiple, and the baseband chip is a UCP4008 chip;

[0039] The first data end of the field programmable gate array chip FPGA is respectively connected to the plurality of baseband chips through optical fibers, and performs data exchange with the baseband chips through the JESD protocol;

[0040] The first data terminal and the second data terminal of the network switching device switch are respectively connected to the plurality of baseband chips for communication, and the network switching device switch is used to realize data interaction between the core network and the baseband chips;

[0041] The first data end of the front panel device is communicatively connected to the second data end of the field programmable gate array chip FPGA, and the front panel device is used to transmit the data sent by the field programmable gate array chip FPGA to the air interface through the radio frequency antenna to provide mobile access service functions.

[0042] like Figure 1As shown, in the traditional solution, DU (Distributed Unit, an important logical network element in the 5G network, mainly responsible for wireless signal processing and base station control, including processing physical layer functions and layer functions requiring real-time performance) - field programmable gate array chip FPGA - RRU, wherein the connection between DU and field programmable gate array chip FPGA is external, and data transmission between them is based on CPRI.

[0043] In the first aspect, the first data end of the field programmable gate array chip FPGA of the embodiment of the present application is respectively connected to the multiple baseband chips through optical fibers, and exchanges data with the baseband chips through the JESD protocol, that is, the field programmable gate array chip FPGA is connected to the baseband chip through optical fibers, and exchanges data with the baseband chip through the JESD protocol;

[0044] The traditional JESD (Joint Electronic Device Engineering Council, an international standard for describing and standardizing the transmission process of radio frequency and microwave signals, including descriptions of signal amplitude, phase, frequency change, etc.) is applied to transmit intermediate frequency data between the baseband chip and the Transceiver (RF transceiver). The interface between the baseband and the RF transceiver is an internal interface. In the embodiment of the present application, the data is carried by optical fiber, but the data transmitted in the optical fiber is based on the JESD protocol, and the JESD protocol interface is used to replace the traditional CPRI transmission scheme between UCP4008 and the field programmable gate array chip FPGA. Compared with the CPRI protocol, the mapping method and arrangement of the IQ data (referring to two complex components, namely the orthogonal amplitude components In-phase (I) and Quadrature (Q)) of the JESD protocol are completely different. After the data is arranged, there is no need to compress the data, which can greatly reduce the demand for the number of CPRI interfaces of the field programmable gate array chip FPGA and the demand for the performance of the field programmable gate array chip FPGA, thereby reducing costs. The embodiment of the present application achieves rapid deployment by applying the integrated base station of the UCP4008 chip to the distributed base station solution.

[0045] See also Figure 3-Figure 5 , the following compares the data arrangement scheme of the embodiment of the present application through the JESD protocol and the traditional CPRI protocol interface:

[0046] CPRI protocol interface: NR (New Radio, also known as 5G NR or 5G New Air Interface, is a global 5G standard based on OFDM (Orthogonal Frequency Division Multiplexing) and a new air interface design, which is the basis of cellular mobile technology), for example Figure 3In the NR data transmission, each cell has 32 AxCs (Application Exchange Control, which is a technology for controlling and managing application exchange, used to support exchange and transmission between applications, and data exchange between applications and the network), from AxC0 to AxC31. Areas AxC0 to AxC31 are IQ data of NR cell antenna 0, and areas AxC0 to AxC31 are IQ data of NR cell antenna 1. The front is the control area and the reserved area, and the back is the compression area.

[0047] JESD protocol interface: see Figure 4 Taking slot0 to slot7 (slot refers to time slot, which refers to a period of time divided in time and a unit used to transmit information) as an example, the data length of an antenna is 123008 bytes, data blocks 0, 4, 8...15364, 15368, 15372 are the IQ data of the first antenna, data blocks 1, 5, 9...15365, 15369, 15373 are the IQ data of the second antenna, and so on.

[0048] For convenience, assume that there are two antenna terminals 0 and 1, and there are 56 data blocks numbered 0 to 55, where the area is antenna 0 and the green area is antenna 1. Then the data blocks are arranged in the antenna as follows: Figure 5 As shown. On the second aspect, see Figure 3-Figure 5 By comparison, the data arrangement methods of the JESD protocol interface and the CPRI protocol interface are completely different. Since the JESD solution does not need to compress the data, it does not need to reserve space for compressed information at the front end like the CPRI protocol, saving data space. In addition, the data of the JESD protocol interface is arranged in sequence according to the antennas from 0 to 3, and the arrangement method is simpler. It has lower requirements on the number and performance of the field programmable gate array chip FPGA interface, and any field programmable gate array chip FPGA with lower configuration can be flexibly selected according to actual needs, greatly reducing the cost of the field programmable gate array chip FPGA and the cost of the overall system.

[0049] Please continue to see Figure 2 In an optional embodiment of the present application, the plurality of baseband chips include at least: a first baseband chip UCP4008-1, a second baseband chip UCP4008-2, a third baseband chip UCP4008-3 and a fourth baseband chip UCP4008-4; wherein:

[0050] The first baseband chip UCP4008-1, the second baseband chip UCP4008-2, and the third baseband chip UCP4008-3 are respectively communicatively connected to the second data end of the network switching device switch, and the fourth baseband chip UCP4008-4 is communicatively connected to the first data end of the network interaction device. The fourth baseband chip UCP4008-4 is used to receive core network data and transmit the core network data to the first baseband chip UCP4008-1, the second baseband chip UCP4008-2, and the third baseband chip UCP4008-3 through the network switching device switch.

[0051] In an optional embodiment of the present application, the fourth baseband chip UCP4008-4 communicates with the network switching device switch through the T-MAC protocol; and / or the first baseband chip UCP4008-1, the second baseband chip UCP4008-2, and the third baseband chip UCP4008-3 respectively communicate with the network switching device switch through the T-MAC protocol.

[0052] In an optional embodiment of the present application, the above-mentioned distributed base station system also includes: a clock chip; the clock chip is communicatively connected to the first data end of the network switching device switch, and the clock chip is used to provide a clock synchronization signal to the first baseband chip UCP4008-1, the second baseband chip UCP4008-2, and the third baseband chip UCP4008-3, so as to provide an accurate clock to the baseband chip to ensure that each device on the board can maintain clock synchronization.

[0053] In an optional embodiment of the present application, the first baseband chip UCP4008-1 and / or the second baseband chip UCP4008-2 are deployed with multiple TDD NR (Time Division Duplexing New Radio) cells; the third baseband chip UCP4008-3 is deployed with an LTE (Long Term Evolution) cell.

[0054] In an optional embodiment of the present application, the number of the TDD NR cells is at least 2; and / or the number of the TDD NR cells is at least 3.

[0055] In an optional embodiment of the present application, the first baseband chip UCP4008-1 and / or the second baseband chip UCP4008-2 both carry the physical layer and protocol stack of the TDD NR cell; and / or the third baseband chip UCP4008-3 carries the physical layer and protocol stack of the LTE cell.

[0056] In an optional embodiment of the present application, the TDD NR cell is a 100M TDD NR cell of 4T4R; and / or, the LTE cell is a 20M LTE FDD cell.

[0057] For example Figure 2 The UCP4008-1 chip can be configured with two 4T4R 100M TDD NR cells, and the L1 (physical layer) and L2 (protocol stack) of the cell can be deployed on a single UCP4008 chip.

[0058] For example Figure 2 The functions of the UCP4008-2 chip are the same as those of the UCP4008-1 chip. Two 4T4R 100M TDD NR cells can also be deployed on the UCP4008-2 chip.

[0059] For example Figure 2 The UCP4008-3 chip can be used to deploy LTE cells independently, and can support three 2T2R 20M LTE FDD cells. The L1 (physical layer) and L2 (protocol stack) of the three cells can all be carried on the UCP4008-3 chip.

[0060] The distributed base station system provided in the embodiment of the present application can deploy 4G and 5G cells based on the UCP4008 baseband chip. The fronthaul interface is replaced by the JESD protocol interface instead of the traditional CPRI interface. The JESD204B 4lane configuration can provide a 40Gbps transmission rate, which can meet the transmission requirements of NR single-chip 100M 4T4R dual cells and LTE single-chip 20M 2T2R three cells, greatly improving the overall performance of the distributed base station system.

[0061] When performing signal synchronization between an LTE cell and an NR cell, it is easy for time and frequency to be out of sync. Therefore, in an optional embodiment of the present application, the clock chip is also used to segment and downsample the first air interface data of the signal sending cell to obtain multiple groups of primary synchronization signal sequences with the same symbol length, and adjacent primary synchronization signal sequences contain the same symbols; wherein the signal sending cell is an LTE cell or an NR cell; calculate the correlation between each segment of data in the multiple groups of primary synchronization signal sequences and the first air interface data, and obtain the coarse synchronization position information with the greatest correlation with the first air interface data;

[0062] Determine a signal to be synchronized in the first air interface data based on the coarse synchronization position information and the data synchronization length, wherein the signal to be synchronized includes: a primary synchronization signal, a first auxiliary synchronization signal, and a second auxiliary synchronization signal;

[0063] Determine an actual secondary synchronization signal and a cell ID from the first secondary synchronization signal and the second secondary synchronization signal;

[0064] Performing frequency deviation calculation on the actual auxiliary synchronization signal and the primary synchronization signal to obtain frequency deviation information;

[0065] Time synchronization is performed according to the frequency offset information and the cell ID.

[0066] In an optional embodiment of the present application, determining the actual secondary synchronization signal and the cell ID from the first secondary synchronization signal and the second secondary synchronization signal includes:

[0067] Respectively converting the first auxiliary synchronization signal and the second auxiliary synchronization signal into frequency domain data;

[0068] Performing reverse descrambling calculations on the first auxiliary synchronization signal and the second auxiliary synchronization signal of the frequency domain data respectively to obtain a reverse descrambling result and a cell ID;

[0069] The larger auxiliary synchronization signal in the reverse descrambling result is used as the actual auxiliary synchronization signal.

[0070] In an optional embodiment of the present application, before the first air interface data is segmented and downsampled, the clock chip is also used to receive the center frequency information sent by the upper node; based on the center frequency information, the acquired second air interface data is converted into the first air interface data corresponding to the frequency of the center frequency information.

[0071] In an optional embodiment of the present application, the symbol length of the main synchronization signal sequence is smaller than the correlation calculation length; accordingly, the clock chip is also used to perform automatic gain control on the main synchronization signal sequence so that the symbol length of the main synchronization signal sequence after gain meets the correlation calculation requirements.

[0072] In an optional embodiment of the present application, the calculation of the correlation between each segment of data in the multiple groups of main synchronization signal sequences and the first air interface data to obtain the coarse synchronization position information with the greatest correlation with the first air interface data includes: performing conjugate calculations on the multiple groups of main synchronization signal sequences respectively to obtain multiple groups of conjugate symmetric signals; performing sliding correlation calculations on the first air interface data through the multiple groups of conjugate symmetric signals to obtain multiple groups of correlation value sequences representing the correlation with the first air interface data; normalizing the multiple groups of correlation value sequences to calculate the power value of each segment of data in each of the correlation value sequences; and determining the coarse synchronization position information with the greatest correlation with the first air interface data based on the largest power value.

[0073] In an optional embodiment of the present application, after the normalization processing is performed on the multiple groups of correlation value sequences to calculate the power value of each segment of data in each of the correlation value sequences, the clock chip is also used to determine in turn whether the power value of each segment of data is greater than a preset power value; if the power value of each segment of data is not greater than the preset power value, the second air interface data is reacquired; if the power value of at least one segment of data is greater than the preset power value, the coarse synchronization position information with the greatest correlation with the first air interface data is determined based on the maximum power value.

[0074] In an optional embodiment of the present application, the signal to be synchronized is determined in the first air interface data based on the coarse synchronization position information and the data synchronization length, and the clock chip is also used to determine the signal to be synchronized in the first air interface data including the main synchronization signal, the first auxiliary synchronization signal and the second auxiliary synchronization signal based on the coarse synchronization position information, the data synchronization length and the symbol position of each data in the current communication protocol.

[0075] In an optional embodiment of the present application, the frequency deviation calculation of the actual auxiliary synchronization signal and the main synchronization signal to obtain frequency deviation information includes: converting the main synchronization signal into main synchronization frequency domain data of frequency domain data; calculating the frequency deviation information of the main synchronization frequency domain data and the actual auxiliary synchronization frequency domain data, the actual auxiliary synchronization frequency domain data being the frequency domain data corresponding to the actual auxiliary synchronization signal.

[0076] The overall performance of the distributed base station system provided in the embodiments of the present application is described below in combination with all the above embodiments:

[0077] Taking the number of baseband chips as 4 as an example, they include: a first baseband chip UCP4008-1, a second baseband chip UCP4008-2, a third baseband chip UCP4008-3 and a fourth baseband chip UCP4008-4. The first baseband chip UCP4008-1, the second baseband chip UCP4008-2, the third baseband chip UCP4008-3 and the fourth baseband chip UCP4008-4 and a field programmable gate array chip FPGA constitute a 4-chip distributed base station system, wherein: the first baseband chip UCP4008-1 and the second baseband chip UCP4008-2 are NR's L1 / L2, and can support 2CC 4TR NR 100M cells.

[0078] A UCP4008-3 chip deploys LTE (Long Term Evolution, a long-term evolution of the UMTS (Universal Mobile Telecommunications System) technical standard developed by 3GPP (The 3rd Generation Partnership Project)) L1 (physical layer) / L2 (protocol stack). A single UCP4008-3 baseband chip can support a 3CC 2TR 30M LTE FDD standard cell; the transmission rate and parameters of the LTE FDD standard cell are shown in Table 1 below:

[0079] Table 1

[0080] M S N L F K Sampling rate index rate sysref frequency 5G 16 1 16 4 8 32 122.88M 2CC-4TR 9.8304G 3.84M 4G 16 1 16 2 16 32 30.72M 4CC-2TR 4.9152G 0.96M

[0081] The data transmission method of the first baseband chip UCP4008-1, the second baseband chip UCP4008-2, the third baseband chip UCP4008-3 and the field programmable gate array chip FPGA is the JESD protocol. In this way, the field programmable gate array chip FPGA only needs three interfaces to meet the data transmission requirements of the entire 4 NR 100M TDD 4T4R cells + 3 LTE 20M FDD 2T2R.

[0082] The rates of option 8 / 9 / 10 in the traditional CPRI protocol transmission mode are as follows:

[0083] CPRl line bit rate option 8: 10137.6Mbit / s, 64B / 66B line coding (20x491.52x 66 / 64Mbits)

[0084] CPRl line bit rate option 9: 12165.12Mbit / s, 64B / 66B line coding (24x491.52x 66 / 64Mbits)

[0085] CPRl line bit rate option 10: 24330.24Mbit / s, 64B / 66B line coding (48x491.52x 66 / 64Mbits)

[0086] When data is transmitted from the DU to the field programmable gate array chip FPGA through the CPRI protocol interface, taking option 10 as an example, the transmission rate is 24G bit / s, and the field programmable gate array chip FPGA has the following requirements:

[0087] 1) High-speed interface support: Field programmable gate array chips FPGA need to support high-speed interfaces and be able to handle data transmission rates of 24Gbps. Modern high-end field programmable gate array chips FPGA usually have multiple high-speed SerDes (SERializer / DESerializer, a mainstream time division multiplexing (TDM), point-to-point (P2P) serial communication technology) and support multiple high-speed serial protocols, such as 10GbE, 25GbE, PCIe Gen3 / Gen4, etc.

[0088] 2) Multi-channel support: Multiple SerDes channels may be required to achieve the required total bandwidth.

[0089] 3) High-speed data throughput: Field Programmable Gate Array chips (FPGAs) need to have sufficient logic resources (LUTs, FFs) and DSP (Digital Signal Processing) modules to process 24Gbps data streams, including but not limited to decoding, demultiplexing, error detection and correction, and other functions.

[0090] 4) High-performance PLL (Phase-Locked Loop): used to generate a stable clock signal to ensure the accuracy and integrity of data transmission.

[0091] 5) Clock management: Field programmable gate array chips FPGA need to support complex clock management mechanisms to ensure clock synchronization of all high-speed SerDes interfaces and internal logic circuits.

[0092] This application uses optical fiber to connect the baseband chip and the field programmable gate array chip FPGA, and uses the JESD protocol interface for data transmission between the baseband chip and the field programmable gate array chip FPGA. Compared with the traditional CPRI protocol, taking the JESD204B / C protocol interface and 24G bit / s transmission rate as an example, the advantages of the field programmable gate array chip FPGA are mainly as follows:

[0093] 1) Protocol features:

[0094] CPRI protocol interface: involves more protocol layers and control information, including data compression, time slot synchronization, etc.

[0095] JESD204B / C protocol interface: focuses more on high-speed data transmission, simplifies the data compression process, simplifies the protocol stack, and mainly focuses on the frame structure and synchronization mechanism of the data.

[0096] 2) Differences in requirements for field programmable gate array chips FPGA:

[0097] 2.1 High-speed serial interface support

[0098] For a data transmission rate of 24Gbps, both the CPRI protocol interface and the JESD204B / C protocol interface need to support a high-speed SerDes (Serializer / Deserializer) interface. However, the JESD204B / C protocol interface may focus more on the frame synchronization and clock recovery mechanism of the data.

[0099] 2.2 Data Processing Capabilities

[0100] CPRI protocol interface: requires processing of additional protocol layer information, such as data compression, decompression, and time slot synchronization.

[0101] JESD204B / C protocol interface: focuses on the frame structure and synchronization mechanism of the data. There is no data compression or decompression process, so data processing is simpler and the processing rate is also improved.

[0102] 3) Clock and synchronization

[0103] CPRI protocol interface: needs to handle complex clock and frame synchronization mechanisms, including time slot synchronization, etc.

[0104] JESD204B / C protocol interface: mainly relies on clock recovery and frame synchronization mechanisms and is usually more simplified.

[0105] 4) Power consumption and heat dissipation

[0106] Since the data processing of the JESD204B / C protocol interface is relatively simple, it has more advantages in terms of power consumption.

[0107] 5) Integration and programmability

[0108] CPRI protocol interface: More hard-core IP support may be required, such as Ethernet MAC, protocol stack, etc.

[0109] JESD204B / C protocol interface: Usually has a higher level of integration and requires fewer external components.

[0110] In an optional embodiment of the present application, in the above-mentioned distributed base station system, the fourth baseband chip UCP4008-4 is deployed with an OAM functional entity (Operation Administration and Maintenance, according to the actual needs of the operator's network operation, the network management work is usually divided into three categories: operation, management, and maintenance, referred to as OAM, OAM functional entity refers to a physical device that performs OAM functions), and the OAM functional entity is used to realize data transmission between the base station and the core network.

[0111] The data interaction between the NR cell and the LTE cell and the core network can be transmitted to the network switching device switch through the T-MAC protocol interface (a relay access control (MAC) protocol designed specifically for wireless sensor networks, which aims to reduce the idle listening time of nodes and thus reduce energy consumption), and then transmitted by the network switching device switch to the fourth baseband chip UCP4008-4 for processing. The OAM function can be deployed on the fourth baseband chip UCP4008-4, which is responsible for data transmission between the base station and the core network.

[0112] In an optional embodiment of the present application, the front panel is a radio remote unit entity.

[0113] The first baseband chip UCP4008-1, the second baseband chip UCP4008-2, the third baseband chip UCP4008-3, the uplink and downlink data of the 5G cell and the 4G cell are interacted between the first baseband chip UCP4008-1, the second baseband chip UCP4008-2, the third baseband chip UCP4008-3 and the field programmable gate array chip FPGA through the JESD protocol interface. At the same time, the field programmable gate array chip FPGA can also convert the data into a set format and then transmit it to the front panel device, such as the radio remote unit entity RRU, so that the data on each cell can transmit the signal to the air interface through the radio frequency antenna, and then provide mobile access service functions for users.

[0114] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0115] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A distributed base station system, characterized in that: At least: Multiple baseband chips, wherein the baseband chips are UCP4008 chips; A field programmable gate array chip, wherein the first data end of the field programmable gate array chip is respectively connected to the plurality of baseband chips through optical fibers, and performs data exchange with the baseband chips through a JESD protocol; A network switching device, wherein the first data terminal and the second data terminal of the network switching device are respectively connected to the plurality of baseband chips for communication, and the network switching device is used to implement data interaction between the core network and the baseband chips; A front panel device, wherein the first data end of the front panel device is communicatively connected to the second data end of the field programmable gate array chip, and the front panel device is used to transmit the data sent by the field programmable gate array chip to the air interface through the radio frequency antenna to provide a mobile access service function.

2. The distributed base station system according to claim 1, characterized in that: The plurality of baseband chips include at least: a first baseband chip, a second baseband chip, a third baseband chip and a fourth baseband chip; wherein: The first baseband chip, the second baseband chip, and the third baseband chip are respectively communicatively connected to the second data end of the network switching device, the fourth baseband chip is communicatively connected to the first data end of the network interaction device, and the fourth baseband chip is used to receive core network data and transmit the core network data to the first baseband chip, the second baseband chip, and the third baseband chip through the network switching device.

3. The distributed base station system according to claim 2, characterized in that: The fourth baseband chip communicates with the network switching device via the T-MAC protocol; and / or the first baseband chip, the second baseband chip, and the third baseband chip communicate with the network switching device via the T-MAC protocol respectively.

4. The distributed base station system according to claim 2, characterized in that: Also includes: A clock chip, wherein the clock chip is communicatively connected to the first data end of the network switching device, and the clock chip is used to provide a clock synchronization signal to the first baseband chip, the second baseband chip, and the third baseband chip.

5. The distributed base station system according to claim 2, characterized in that: The first baseband chip and / or the second baseband chip are deployed with multiple TDD NR cells; The third baseband chip is deployed with an LTE cell.

6. The distributed base station system according to claim 5, characterized in that: The number of the TDD NR cells is at least 2; and / or the number of the TDD NR cells is at least 3.

7. The distributed base station system according to claim 5, characterized in that: The first baseband chip and / or the second baseband chip both carry the physical layer and protocol stack of the TDD NR cell; and / or the third baseband chip carries the physical layer and protocol stack of the LTE cell.

8. The distributed base station system according to claim 6, characterized in that: The TDD NR cell is a 100M TDD NR cell of 4T4R; and / or, the LTE cell is a 20M LTE FDD cell.

9. The distributed base station system according to claim 5, characterized in that: The fourth baseband chip is deployed with an OAM functional entity, and the OAM functional entity is used to implement data transmission between the base station and the core network.

10. The distributed base station system according to claim 1, characterized in that: The front panel is a radio remote unit entity.

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