Semiconductor structure and method for manufacturing the same

Abstract

The present invention relates to a semiconductor structure and a method for preparing the same. The semiconductor structure comprises: a substrate; a plurality of active pillars arranged in an array, located in the substrate, and each active pillar is arranged at intervals along a first direction and a second direction; wherein adjacent active pillars arranged at intervals along the first direction are staggered, and adjacent active pillars arranged at intervals along the second direction are arranged in a straight line, and the first direction intersects the second direction. The active pillars are arranged in an array to improve the space utilization of the device, thereby improving the storage density of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] With the development of semiconductor technology, in the current memory design and manufacturing process, transistors are mainly implemented by deep-buried channels or vertical extension. However, the arrangement of transistors in the related art has low space utilization, resulting in low storage density of devices in the related art. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the problem of low storage density in the related art.

[0004] In a first aspect, the present invention provides a semiconductor structure, comprising:

[0005] substrate;

[0006] A plurality of active pillars arranged in an array are located in the substrate, and the active pillars are arranged at intervals along a first direction and a second direction; wherein adjacent active pillars arranged at intervals along the first direction are staggered with each other, and adjacent active pillars arranged at intervals along the second direction are arranged in a straight line, and the first direction intersects with the second direction.

[0007] The semiconductor structure comprises: a substrate; a plurality of active pillars arranged in an array, located in the substrate, wherein the active pillars are arranged at intervals along a first direction and a second direction; wherein adjacent active pillars arranged at intervals along the first direction are staggered, and adjacent active pillars arranged at intervals along the second direction are arranged in a straight line, and the first direction intersects the second direction. Since the active pillars are arranged in an array, the space utilization rate of the device can be improved, thereby improving the storage density of the device.

[0008] In one embodiment, the semiconductor structure further comprises:

[0009] A plurality of bit lines, located below each of the active pillars and in contact with a bottom end of each of the active pillars, each of the bit lines extending along the second direction and arranged at intervals along the first direction;

[0010] A plurality of gate structures are located between the active pillars and contact the sidewalls of the active pillars. The gate structures extend along the first direction and are arranged at intervals along the second direction.

[0011] In one embodiment, the semiconductor structure further comprises:

[0012] A plurality of capacitor structures are located on the top of each of the active pillars and correspond to each of the active pillars one by one. Each of the active pillars and each of the capacitor structures are connected via an interconnection structure.

[0013] In one embodiment, the active pillar is square in top view.

[0014] In a second aspect, the present invention further provides a method for preparing a semiconductor structure, comprising:

[0015] providing a substrate;

[0016] Forming a plurality of initial active pillars in the substrate and arranged at intervals along a first direction and a second direction, wherein the first direction intersects the second direction;

[0017] A portion of each of the initial active pillars is removed to obtain a plurality of active pillars arranged in an array; wherein adjacent active pillars arranged at intervals along the first direction are staggered with each other, and adjacent active pillars arranged at intervals along the second direction are arranged in a straight line.

[0018] The method for preparing the semiconductor structure is as follows: a plurality of initial active pillars are formed in the substrate and arranged at intervals along a first direction and a second direction, wherein the first direction intersects with the second direction; a portion of each of the initial active pillars is removed to obtain a plurality of active pillars arranged in an array; wherein adjacent active pillars arranged at intervals along the first direction are staggered, and adjacent active pillars arranged at intervals along the second direction are arranged in a straight line. The active pillars are arranged in an array to improve the space utilization of the device, thereby improving the storage density of the device.

[0019] In one embodiment, forming a plurality of initial active pillars spaced apart along a first direction and a second direction in the substrate comprises:

[0020] Etching the substrate to form a plurality of first grooves extending along the second direction and arranged at intervals along the first direction;

[0021] Filling a first dielectric layer in the first trench;

[0022] The substrate and the first dielectric layer are etched to form a plurality of second grooves extending along the first direction and arranged at intervals along the second direction, wherein the depth of the second grooves is less than the depth of the first grooves, and the substrate located between each of the first grooves and each of the second grooves serves as each of the initial active pillars.

[0023] In one embodiment, after etching the substrate and the first dielectric layer, the method further includes:

[0024] forming a plurality of bit lines extending along the second direction and arranged at intervals along the first direction under each of the second trenches;

[0025] A plurality of gate structures extending along the first direction and arranged at intervals along the second direction are formed in each of the second trenches.

[0026] In one embodiment, forming a plurality of bit lines extending along the second direction and arranged at intervals along the first direction under each of the second trenches includes:

[0027] forming a second dielectric layer on the sidewalls of each of the second trenches;

[0028] Based on each of the second trenches, the substrate is laterally etched to form a plurality of preset bit line regions located below the second trenches, extending along the second direction and arranged at intervals along the first direction;

[0029] A conductive barrier layer and a conductive layer are sequentially deposited in the preset bit line region to form a bit line.

[0030] In one embodiment, a plurality of gate structures extending along the first direction and arranged at intervals along the second direction are formed in each of the second trenches, including:

[0031] Filling a third dielectric layer in each of the second trenches;

[0032] Etching and removing a portion of the third dielectric layer located in the second groove to form a plurality of third grooves extending along the first direction and arranged at intervals along the second direction, wherein the depth of the third grooves is less than the depth of the second grooves;

[0033] forming a fourth dielectric layer on the sidewalls of each of the third trenches;

[0034] Based on each of the fourth dielectric layers, a portion of the third dielectric layer is removed to form a plurality of preset channel regions located in the second trench, extending along the first direction and arranged at intervals along the second direction;

[0035] A gate oxide layer and a gate conductive layer are sequentially deposited in the preset channel region to form the gate structure.

[0036] In one embodiment, removing a portion of each of the initial active pillars to obtain a plurality of active pillars arranged in an array includes:

[0037] Forming a patterned hard mask layer on the substrate, the patterned hard mask layer comprising a plurality of hard mask structures extending along a third direction and a fourth direction, wherein the third direction intersects the fourth direction; the hard mask structures are interlaced with each other to form a plurality of spacing regions, each of the spacing regions corresponds to each of the initial active pillars one by one, and the surface of each of the initial active pillars is exposed;

[0038] Part of each of the initial active pillars is removed based on each of the spaced regions to form a plurality of active pillars arranged in the array.

[0039] In one embodiment, the first direction is perpendicular to the second direction, and the angle between the third direction and the fourth direction is 30° to 90°.

[0040] In one embodiment, forming a patterned hard mask layer on the substrate includes:

[0041] forming a hard mask layer on the substrate, and forming an oxide layer on the hard mask layer;

[0042] forming a first mask stack on the oxide layer, wherein the first mask stack comprises a first reflective film layer, a first photoresist coating layer, a second reflective film layer and a first photoresist layer stacked sequentially from bottom to top;

[0043] Expose the first photoresist layer to obtain a patterned first photoresist layer, wherein the patterned first photoresist layer includes a plurality of first photolithography openings extending along the third direction;

[0044] Etching the first mask stack and the oxide layer based on the first photolithography openings to obtain a patterned oxide layer, wherein the patterned oxide layer includes a plurality of first openings extending along the third direction, and the first photolithography openings define shapes and positions of the first openings;

[0045] Filling a photolithography filling layer in each of the first openings;

[0046] forming a second mask stack on the oxide layer, wherein the second mask stack comprises a third reflective film layer, a second photoresist coating layer, a fourth reflective film layer and a second photoresist layer stacked sequentially from bottom to top;

[0047] performing an exposure process on the second photoresist layer to obtain a patterned second photoresist layer, wherein the patterned second photoresist layer comprises a plurality of second photolithography openings extending along the fourth direction;

[0048] Etching the second mask stack and the oxide layer based on the second photolithography openings, and removing the third reflective film layer, the second photolithography coating layer, and the fourth reflective film layer, so as to form a plurality of second openings extending along the fourth direction in the patterned oxide layer, wherein the second photolithography openings define the shapes and positions of the second openings, and the first openings and the second openings are staggered with each other;

[0049] The hard mask layer is etched based on each of the first openings and each of the second openings to obtain a patterned hard mask layer.

[0050] In one embodiment, after removing a portion of each of the initial active pillars to obtain a plurality of active pillars arranged in an array, the method further comprises:

[0051] A plurality of capacitor structures are correspondingly formed on the top of each active pillar, and each active pillar is connected to each capacitor structure via an interconnection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0054] Figure 2 is a schematic top view of a semiconductor structure provided in an embodiment;

[0055] Figure 3 is a flowchart of step S20 in a method for preparing a semiconductor structure provided in an embodiment;

[0056] Figure 4 Schematic diagram of the cross-sectional structure of the structure obtained in step S203 of the method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a schematic diagram of the cross-sectional structure along the aa' direction; (b) is a schematic diagram of the cross-sectional structure along the bb' direction; (c) is a schematic diagram of the cross-sectional structure along the cc' direction; (d) is a schematic diagram of the cross-sectional structure along the dd' direction;

[0057] Figure 5 A flowchart of steps for preparing a bit line and a gate structure in a method for preparing a semiconductor structure provided in an embodiment;

[0058] Figure 6is a flowchart of step S204 in a method for preparing a semiconductor structure provided in an embodiment;

[0059] Figure 7 Schematic diagram of the cross-sectional structure of the structure obtained in step S2041 in the method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a schematic diagram of the cross-sectional structure along the aa' direction; (b) is a schematic diagram of the cross-sectional structure along the bb' direction; (c) is a schematic diagram of the cross-sectional structure along the cc' direction; (d) is a schematic diagram of the cross-sectional structure along the dd' direction;

[0060] Figure 8 Schematic diagram of the cross-sectional structure of the structure obtained in step S2042 in the method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a schematic diagram of the cross-sectional structure along the aa' direction; (b) is a schematic diagram of the cross-sectional structure along the bb' direction; (c) is a schematic diagram of the cross-sectional structure along the cc' direction; (d) is a schematic diagram of the cross-sectional structure along the dd' direction;

[0061] Fig. 9 Schematic diagram of the cross-sectional structure of the structure obtained in step S2043 in the method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a schematic diagram of the cross-sectional structure along the aa' direction; (b) is a schematic diagram of the cross-sectional structure along the bb' direction; (c) is a schematic diagram of the cross-sectional structure along the cc' direction; (d) is a schematic diagram of the cross-sectional structure along the dd' direction;

[0062] Fig.10 is a flowchart of step S205 in a method for preparing a semiconductor structure provided in an embodiment;

[0063] Fig.11 Schematic diagram of the cross-sectional structure of the structure obtained in step S2051 in the method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a schematic diagram of the cross-sectional structure along the aa' direction; (b) is a schematic diagram of the cross-sectional structure along the bb' direction; (c) is a schematic diagram of the cross-sectional structure along the cc' direction; (d) is a schematic diagram of the cross-sectional structure along the dd' direction;

[0064] Fig.12 Schematic diagram of the cross-sectional structure of the structure obtained in step S2053 in the method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a schematic diagram of the cross-sectional structure along the aa' direction; (b) is a schematic diagram of the cross-sectional structure along the bb' direction; (c) is a schematic diagram of the cross-sectional structure along the cc' direction; (d) is a schematic diagram of the cross-sectional structure along the dd' direction;

[0065] Fig.13Schematic diagram of the cross-sectional structure of the structure obtained after the gate oxide layer is deposited in step S2055 in the method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a schematic diagram of the cross-sectional structure along the aa' direction; (b) is a schematic diagram of the cross-sectional structure along the bb' direction; (c) is a schematic diagram of the cross-sectional structure along the cc' direction; (d) is a schematic diagram of the cross-sectional structure along the dd' direction;

[0066] Fig.14 Schematic diagram of the cross-sectional structure of the structure obtained after depositing the gate conductive layer in step S2055 in the method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a schematic diagram of the cross-sectional structure along the aa' direction; (b) is a schematic diagram of the cross-sectional structure along the bb' direction; (c) is a schematic diagram of the cross-sectional structure along the cc' direction; (d) is a schematic diagram of the cross-sectional structure along the dd' direction;

[0067] Fig.15 is a flowchart of step S30 in a method for preparing a semiconductor structure provided in an embodiment;

[0068] Fig.16 A schematic diagram of a top view of a structure obtained in step S301 in a method for preparing a semiconductor structure provided in an embodiment;

[0069] Fig.17 is a flowchart of step S301 in a method for preparing a semiconductor structure provided in an embodiment;

[0070] Fig.18 Schematic diagram of the cross-sectional structure of the structure obtained in step S3013 in the method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a schematic diagram of the cross-sectional structure along the aa' direction; (b) is a schematic diagram of the cross-sectional structure along the bb' direction; (c) is a schematic diagram of the cross-sectional structure along the cc' direction; (d) is a schematic diagram of the cross-sectional structure along the dd' direction;

[0071] Fig.19 Schematic diagram of the cross-sectional structure of the structure obtained in step S3015 in the method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a schematic diagram of the cross-sectional structure along the aa' direction; (b) is a schematic diagram of the cross-sectional structure along the bb' direction; (c) is a schematic diagram of the cross-sectional structure along the cc' direction; (d) is a schematic diagram of the cross-sectional structure along the dd' direction;

[0072] Fig. 20Schematic diagram of the cross-sectional structure of the structure obtained in step S3016 in the method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a schematic diagram of the cross-sectional structure along the aa' direction; (b) is a schematic diagram of the cross-sectional structure along the bb' direction; (c) is a schematic diagram of the cross-sectional structure along the cc' direction; (d) is a schematic diagram of the cross-sectional structure along the dd' direction;

[0073] Fig.21 Schematic diagram of the cross-sectional structure of the structure obtained in step S3018 in the method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a schematic diagram of the cross-sectional structure along the aa' direction; (b) is a schematic diagram of the cross-sectional structure along the bb' direction; (c) is a schematic diagram of the cross-sectional structure along the cc' direction; (d) is a schematic diagram of the cross-sectional structure along the dd' direction;

[0074] Fig. 22 Schematic diagram of the cross-sectional structure of the structure obtained in step S3019 in the method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a schematic diagram of the cross-sectional structure along the aa' direction; (b) is a schematic diagram of the cross-sectional structure along the bb' direction; (c) is a schematic diagram of the cross-sectional structure along the cc' direction; (d) is a schematic diagram of the cross-sectional structure along the dd' direction;

[0075] Fig.23 The schematic diagram of the top view of the structure obtained in step S302 in the method for preparing a semiconductor structure provided in one embodiment is shown.

[0076] Explanation of the reference numerals: 1-substrate, 11-initial active pillar, 12-active pillar, 101-second dielectric layer, 20-first trench, 201-first dielectric layer, 30-second trench, 301-third dielectric layer, 40-preset bit line region, 41-bit line, 401-conductive barrier layer, 402-conductive layer, 403-fifth dielectric layer, 50-third trench, 501-fourth dielectric layer, 60-gate structure, 601-gate oxide layer, 602-gate conductive barrier layer, 603-gate conductive material layer, 70-hard mask structure, 701-hard mask layer, 702-oxide layer, 703-photolithography filling layer, 801-first mask stack, 802-first photoresist layer, 901-second mask stack, 902-second photoresist layer. DETAILED DESCRIPTION

[0077] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0078] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0079] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0080] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0081] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0082] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of preferred embodiments of the invention (and intermediate structures), so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0083] See also Figure 1 The present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0084] S10: providing a substrate;

[0085] S20: forming a plurality of initial active pillars arranged in a first direction and a second direction in the substrate, wherein the first direction intersects the second direction;

[0086] S30: removing a portion of each initial active pillar to obtain a plurality of active pillars arranged in an array; wherein adjacent active pillars arranged at intervals along the first direction are staggered with each other, and adjacent active pillars arranged at intervals along the second direction are arranged in a straight line.

[0087] The method for preparing the semiconductor structure is as follows: a plurality of initial active pillars are formed in a substrate and arranged at intervals along a first direction and a second direction, wherein the first direction intersects with the second direction; a portion of each initial active pillar is removed to obtain a plurality of active pillars arranged in an array; wherein adjacent active pillars arranged at intervals along the first direction are staggered, and adjacent active pillars arranged at intervals along the second direction are arranged in a straight line. The active pillars are arranged in an array to improve the space utilization of the device, thereby improving the storage density of the device.

[0088] See also Figure 2 , Figure 2 The aa' direction, bb' direction, cc' direction and dd' direction of the semiconductor structure in the present invention are shown.

[0089] in, Figure 2 The X direction represents the first direction, and the Y direction represents the second direction. It should be noted that: Figure 2 The various directions in the above are only for the convenience of explaining the structure of the present solution, and do not constitute any limitation on the present solution. In addition, in other suitable application scenarios, the first direction and the second direction may also have other suitable definitions.

[0090] See also Figure 2 In step S20, a plurality of initial active pillars 11 are formed in the substrate 1 and arranged at intervals along a first direction and a second direction, wherein the first direction intersects the second direction.

[0091] In one embodiment, Figure 3 As shown, step S20 may include the following steps:

[0092] S201: etching the substrate 1 to form a plurality of first trenches 20 extending along the second direction and arranged at intervals along the first direction.

[0093] Among them, the material of the substrate 1 can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and this embodiment is not limited here.

[0094] S202: Fill the first trench 20 with a first dielectric layer 201, such as Figure 4 shown.

[0095] The material of the first dielectric layer 201 may include an oxide material.

[0096] S203: etching the substrate 1 and the first dielectric layer 201 to form a plurality of second trenches 30 extending along the first direction and arranged at intervals along the second direction, wherein the depth of the second trenches 30 is less than the depth of the first trenches 20, and the substrate 1 between each first trench 20 and each second trench 30 serves as each initial active pillar 11, such as Figure 4 shown.

[0097] Optional, such as Figure 2 As shown, the width of the initial active pillar 11 along the second direction is greater than the width along the first direction.

[0098] In one embodiment, after step S203, Figure 5 As shown, the method for preparing the semiconductor structure also includes:

[0099] S204 : forming a plurality of bit lines 41 extending along the second direction and arranged at intervals along the first direction below each second trench 30 .

[0100] S205 : forming a plurality of gate structures 60 extending along the first direction and arranged at intervals along the second direction in each of the second trenches 30 .

[0101] In one embodiment, Figure 6 As shown, the above step S204 includes:

[0102] S2041: forming a second dielectric layer 101 on the sidewalls of each second trench 30, such as Figure 7 shown.

[0103] The second dielectric layer 101 may include a nitride material, for example, silicon nitride.

[0104] Optionally, a second dielectric layer 101 may be formed at the bottom and sidewalls of each second trench 30 and the upper surface of the initial active pillar 11 by a deposition process, and then the second dielectric layer 101 at the bottom of each second trench 30 and the upper surface of the initial active pillar 11 may be removed by an etching process to obtain the second dielectric layer 101 at the sidewalls of each second trench 30, thereby forming a Figure 7 In the structure shown, the deposition process may include an atomic layer deposition process, and the etching process may include a punch etch process.

[0105] S2042: etching the substrate 1 laterally based on each second trench 30 to form a plurality of preset bit line regions 40 extending along the second direction and arranged at intervals along the first direction under the second trench 30, such as Figure 8 shown.

[0106] An etching process may be used to laterally etch the substrate 1 based on each second trench 30 to define the morphology of the preset bit line region 40 , wherein the etching process may include vapor etching.

[0107] S2043: depositing a conductive barrier layer 401 and a conductive layer 402 in sequence in the predetermined bit line region 40 to form a bit line 41, such as Fig. 9 shown.

[0108] The deposition process for forming the bit line 41 may include an atomic layer deposition process and a chemical vapor deposition process. The material of the conductive barrier layer 401 may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof, and may be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, and / or other suitable processes. The material of the conductive layer 402 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals, and may be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, and / or other suitable processes.

[0109] Optionally, after forming the bit line 41, as Fig. 9 As shown, the step of removing the second dielectric layer 101 on the sidewalls of each second trench 30 may also be included.

[0110] In one embodiment, Fig.10 As shown, the above step S205 includes:

[0111] S2051: Fill each second trench 30 with a third dielectric layer 301, such as Fig.11 shown.

[0112] The third dielectric layer 301 may include an oxide material layer.

[0113] S2052: etching and removing a portion of the third dielectric layer 301 located in the second trench 30 to form a plurality of third trenches 50 extending along the first direction and arranged at intervals along the second direction, wherein the depth of the third trenches 50 is less than the depth of the second trenches 30. Fig.12 shown.

[0114] S2053: forming a fourth dielectric layer 501 on the sidewalls of each third trench 50, such as Fig.12 shown.

[0115] Optionally, a fourth dielectric layer 501 may be formed at the bottom and sidewalls of each third trench 50 and the upper surface of the initial active pillar 11 by a deposition process, and then the fourth dielectric layer 501 at the bottom of each third trench 50 and the upper surface of the initial active pillar 11 may be removed by an etching process to obtain the fourth dielectric layer 501 at the sidewalls of each third trench 50, thereby forming Fig.12 In the structure shown, the deposition process may include an atomic layer deposition process, and the etching process may include a through-hole etching process.

[0116] S2054: Based on each fourth dielectric layer 501, a portion of the third dielectric layer 301 is removed to form a plurality of preset channel regions extending in the first direction and arranged at intervals in the second direction in the second trench 30, such as Fig.13 shown.

[0117] An etching process may be used to remove a portion of the third dielectric layer 301 based on each fourth dielectric layer 501 to expose the sidewall of the second trench 30 , wherein the etching process includes a wet etching process.

[0118] S2055: depositing a gate oxide layer 601 and a gate conductive layer in sequence in the predetermined channel region to form a gate structure 60, such as Fig.14 shown.

[0119] The material of the gate oxide layer 601 may include silicon oxide, and the gate oxide layer 601 may be formed on the exposed sidewall of the second trench 30 by atomic layer deposition and in-situ steam generation (ISSG) process. Thereafter, a gate conductive layer is deposited by a deposition process to form a gate structure 60. The gate conductive layer may include a gate conductive barrier layer 602 and a gate conductive material layer 603, which may be similar to the bit line 41, but in some suitable process scenarios, the gate structure 60 may also be other suitable materials, which is not limited in this embodiment.

[0120] Optionally, the gate conductive barrier layer 602 and the gate conductive material layer 603 may be deposited in sequence by a deposition process, and then an etching process may be used to remove the redundant gate conductive barrier layer 602 and the gate conductive material layer 603. Finally, the third trench 50 is filled with the fifth dielectric layer 403 to finally form the following: Fig.14 The structure shown.

[0121] In one embodiment, Fig.15 As shown, the above step S30 includes:

[0122] S301: forming a patterned hard mask layer 701 on the substrate 1, the patterned hard mask layer 701 comprising a plurality of hard mask structures 70 extending along a third direction and a fourth direction, the third direction intersecting the fourth direction; the hard mask structures 70 are interlaced with each other to form a plurality of spacing regions, each spacing region corresponding to each initial active pillar 11 one by one, and exposing the surface of each initial active pillar 11, such as Fig.16 shown.

[0123] The third direction can be Fig.16 The W direction shown, the fourth direction can be as follows Fig.16 In addition, the design and definition of the third direction and the fourth direction can be determined based on the positions of the initial active pillars 11 , which is not limited in this embodiment.

[0124] In one embodiment, the first direction is perpendicular to the second direction, and the angle between the third direction and the fourth direction is 30° to 90°, for example, 30°, 45°, 60°, 75° or 90°. Preferably, the angle between the third direction and the fourth direction is 60°.

[0125] S302: removing a portion of each initial active pillar 11 based on each spacing area to form a plurality of active pillars 12 arranged in an array, such as Fig.23 shown.

[0126] Optionally, the top-view cross-sectional shape of the active pillar 12 can be a square. This is because the top-view area of ​​the active pillar 12 will affect the device area. Therefore, when designing the device and the lithography process, by designing the top-view cross-sectional shape of the active pillar 12 to be a square, the device area can be reduced as much as possible while ensuring the normal operation of the device.

[0127] Optional, such as Fig.23 As shown, the plurality of active pillars 12 arranged in an array are arranged in a hexagonal close-packed manner.

[0128] In one embodiment, Fig.17 As shown, the above step S301 includes:

[0129] S3011: forming a hard mask layer 701 on the substrate 1, and forming an oxide layer 702 on the hard mask layer 701, such as Fig.18 shown.

[0130] The material of the hard mask layer 701 may include an amorphous carbon layer (ACL), and the material of the oxide layer 702 may include silicon oxide.

[0131] S3012: forming a first mask stack 801 on the oxide layer 702, wherein the first mask stack 801 includes a first reflective film layer, a first photoresist coating layer, a second reflective film layer and a first photoresist layer 802 stacked in sequence from bottom to top. Fig.18 shown.

[0132] S3013: Expose the first photoresist layer 802 to obtain a patterned first photoresist layer 802, wherein the patterned first photoresist layer 802 includes a plurality of first photolithography openings extending along a third direction, such as Fig.18 shown.

[0133] S3014: etching the first mask stack 801 and the oxide layer 702 based on the first photolithography openings to obtain a patterned oxide layer 702, wherein the patterned oxide layer 702 includes a plurality of first openings extending along a third direction, and the first photolithography openings define the shape and position of the first openings, such as Fig.19 shown.

[0134] S3015: Fill each first opening with a photolithography filling layer 703, such as Fig.19 shown.

[0135] S3016: forming a second mask stack 901 on the oxide layer 702, wherein the second mask stack 901 includes a third reflective film layer, a second photoresist coating layer, a fourth reflective film layer and a second photoresist layer 902 stacked in sequence from bottom to top. Fig. 20 shown.

[0136] S3017: Expose the second photoresist layer 902 to obtain a patterned second photoresist layer 902, wherein the patterned second photoresist layer 902 includes a plurality of second photolithography openings extending along a fourth direction, such as Fig. 20 shown.

[0137] S3018: etching the second mask stack 901 and the oxide layer 702 based on the second photolithography openings, and removing the third reflective film layer, the second photolithography coating layer, and the fourth reflective film layer to form a plurality of second openings extending along a fourth direction in the patterned oxide layer 702, wherein the second photolithography openings define the shape and position of the second openings, and the first openings and the second openings are interlaced with each other, such as Fig.21 shown.

[0138] S3019: etching the hard mask layer 701 based on each first opening and each second opening to obtain a patterned hard mask layer 701, such as Fig. 22 The hard mask structures 70 included in the patterned hard mask layer 701 are interlaced with each other, and the spacing regions formed by the interlacing of the hard mask structures 70 correspond to the initial active pillars 11 one by one.

[0139] In one embodiment, after step S40, the method for preparing the semiconductor structure further includes:

[0140] A plurality of capacitor structures are correspondingly formed on the top of each active pillar 12 , and each active pillar 12 is connected to each capacitor structure via an interconnection structure.

[0141] For example, a comparison is made between the device formed in the related art and the device formed by the array arrangement of the present invention, as shown in Table 1:

[0142] Table 1 Comparison of size parameters of semiconductor devices in related art and semiconductor devices of the present invention

[0143]

[0144] It can be seen from Table 1 that, through reasonable design, compared with the traditional technology, the device area of ​​the present invention is basically unchanged, so the present invention can achieve high-density storage.

[0145] In addition, the opening and closing of the device of the present invention is controlled by a single-side gate (such as Fig. 22 As shown in the figure, if the actual switch is relatively small, the switch ratio can be increased by increasing the length of the gate. For vertical devices, this method is also easier to implement and does not affect the device area.

[0146] In addition, since the bit line 41 is deposited in a morphology with a small aspect ratio, the width of the bit line 41 can be reduced as much as possible to further reduce the device area.

[0147] The present invention also provides a semiconductor structure, such as Figure 22-Figure 23 As shown, the semiconductor structure includes: a substrate 1; a plurality of active pillars 12 arranged in an array, located in the substrate 1, and each active pillar 12 is arranged at intervals along a first direction and a second direction; wherein adjacent active pillars 12 arranged at intervals along the first direction are staggered with each other, and adjacent active pillars 12 arranged at intervals along the second direction are arranged in a straight line, and the first direction intersects with the second direction.

[0148] Among them, the material of the substrate 1 can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and this embodiment is not limited here.

[0149] The semiconductor structure comprises: a substrate 1; a plurality of active pillars 12 arranged in an array, located in the substrate 1, and each active pillar 12 is arranged at intervals along a first direction and a second direction; wherein adjacent active pillars 12 arranged at intervals along the first direction are staggered, and adjacent active pillars 12 arranged at intervals along the second direction are arranged in a straight line, and the first direction intersects the second direction. Since the active pillars 12 are arranged in an array, the space utilization rate of the device can be improved, thereby improving the storage density of the device.

[0150] Optional, such as Fig.23 As shown, the plurality of active pillars 12 arranged in an array are arranged in a hexagonal close-packed manner.

[0151] In one embodiment, the semiconductor structure further includes: a plurality of bit lines 41, located below each active pillar 12, contacting the bottom end of each active pillar 12, each bit line 41 extending along the second direction and arranged at intervals along the first direction. A plurality of gate structures 60, located between each active pillar 12, contacting the sidewall of each active pillar 12, each gate structure 60 extending along the first direction and arranged at intervals along the second direction.

[0152] In one embodiment, the semiconductor structure further includes: a plurality of capacitor structures located on the top of each active pillar 12 and corresponding to each active pillar 12 one by one, and each active pillar 12 is connected to each capacitor structure via an interconnection structure.

[0153] In one embodiment, the active pillar 12 has a square shape in top view.

[0154] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0155] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A plurality of active pillars arranged in an array are located in the substrate, and the active pillars are arranged at intervals along a first direction and a second direction; wherein adjacent active pillars arranged at intervals along the first direction are staggered with each other, and adjacent active pillars arranged at intervals along the second direction are arranged in a straight line, and the first direction intersects with the second direction.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A plurality of bit lines, located below each of the active pillars and in contact with a bottom end of each of the active pillars, each of the bit lines extending along the second direction and arranged at intervals along the first direction; A plurality of gate structures are located between the active pillars and contact the sidewalls of the active pillars. The gate structures extend along the first direction and are arranged at intervals along the second direction.

3. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A plurality of capacitor structures are located on the top of each of the active pillars and correspond to each of the active pillars one by one. Each of the active pillars and each of the capacitor structures are connected via an interconnection structure.

4. The semiconductor structure according to claim 1, characterized in that The active pillar is in a square shape in a top view.

5. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; Forming a plurality of initial active pillars in the substrate and arranged at intervals along a first direction and a second direction, wherein the first direction intersects the second direction; A portion of each of the initial active pillars is removed to obtain a plurality of active pillars arranged in an array; wherein adjacent active pillars arranged at intervals along the first direction are staggered with each other, and adjacent active pillars arranged at intervals along the second direction are arranged in a straight line.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The forming of a plurality of initial active pillars in the substrate and arranged at intervals along the first direction and the second direction comprises: Etching the substrate to form a plurality of first grooves extending along the second direction and arranged at intervals along the first direction; Filling a first dielectric layer in the first trench; The substrate and the first dielectric layer are etched to form a plurality of second grooves extending along the first direction and arranged at intervals along the second direction, wherein the depth of the second grooves is less than the depth of the first grooves, and the substrate located between each of the first grooves and each of the second grooves serves as each of the initial active pillars.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: After etching the substrate and the first dielectric layer, the method further includes: forming a plurality of bit lines extending along the second direction and arranged at intervals along the first direction under each of the second trenches; A plurality of gate structures extending along the first direction and arranged at intervals along the second direction are formed in each of the second trenches.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The plurality of bit lines extending along the second direction and arranged at intervals along the first direction are formed below each of the second trenches, including: forming a second dielectric layer on the sidewalls of each of the second trenches; Based on each of the second trenches, the substrate is laterally etched to form a plurality of preset bit line regions located below the second trenches, extending along the second direction and arranged at intervals along the first direction; A conductive barrier layer and a conductive layer are sequentially deposited in the preset bit line region to form a bit line.

9. The method for preparing a semiconductor structure according to claim 7, characterized in that: A plurality of gate structures extending along the first direction and arranged at intervals along the second direction are formed in each of the second trenches, including: Filling a third dielectric layer in each of the second trenches; Etching and removing a portion of the third dielectric layer located in the second groove to form a plurality of third grooves extending along the first direction and arranged at intervals along the second direction, wherein the depth of the third grooves is less than the depth of the second grooves; forming a fourth dielectric layer on the sidewalls of each of the third trenches; Based on each of the fourth dielectric layers, a portion of the third dielectric layer is removed to form a plurality of preset channel regions located in the second trench, extending along the first direction and arranged at intervals along the second direction; A gate oxide layer and a gate conductive layer are sequentially deposited in the preset channel region to form the gate structure.

10. The method for preparing a semiconductor structure according to claim 5, characterized in that: The step of removing a portion of each of the initial active pillars to obtain a plurality of active pillars arranged in an array comprises: Forming a patterned hard mask layer on the substrate, the patterned hard mask layer comprising a plurality of hard mask structures extending along a third direction and a fourth direction, wherein the third direction intersects the fourth direction; the hard mask structures are interlaced with each other to form a plurality of spacing regions, each of the spacing regions corresponds to each of the initial active pillars one by one, and the surface of each of the initial active pillars is exposed; Part of each of the initial active pillars is removed based on each of the spaced regions to form a plurality of active pillars arranged in the array.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: The first direction is perpendicular to the second direction, and an angle between the third direction and the fourth direction is 30° to 90°.

12. The method for preparing a semiconductor structure according to claim 10, characterized in that: A patterned hard mask layer is formed on the substrate, comprising: forming a hard mask layer on the substrate, and forming an oxide layer on the hard mask layer; forming a first mask stack on the oxide layer, wherein the first mask stack comprises a first reflective film layer, a first photoresist coating layer, a second reflective film layer and a first photoresist layer stacked sequentially from bottom to top; Expose the first photoresist layer to obtain a patterned first photoresist layer, wherein the patterned first photoresist layer includes a plurality of first photolithography openings extending along the third direction; Etching the first mask stack and the oxide layer based on the first photolithography openings to obtain a patterned oxide layer, wherein the patterned oxide layer includes a plurality of first openings extending along the third direction, and the first photolithography openings define shapes and positions of the first openings; Filling a photolithography filling layer in each of the first openings; forming a second mask stack on the oxide layer, wherein the second mask stack comprises a third reflective film layer, a second photoresist coating layer, a fourth reflective film layer and a second photoresist layer stacked sequentially from bottom to top; performing an exposure process on the second photoresist layer to obtain a patterned second photoresist layer, wherein the patterned second photoresist layer comprises a plurality of second photolithography openings extending along the fourth direction; Etching the second mask stack and the oxide layer based on the second photolithography openings, and removing the third reflective film layer, the second photolithography coating layer, and the fourth reflective film layer, so as to form a plurality of second openings extending along the fourth direction in the patterned oxide layer, wherein the second photolithography openings define the shapes and positions of the second openings, and the first openings and the second openings are staggered with each other; The hard mask layer is etched based on each of the first openings and each of the second openings to obtain a patterned hard mask layer.

13. The method for preparing a semiconductor structure according to claim 5, characterized in that: After removing a portion of each of the initial active pillars to obtain a plurality of active pillars arranged in an array, the method further comprises: A plurality of capacitor structures are correspondingly formed on the top of each active pillar, and each active pillar is connected to each capacitor structure via an interconnection structure.

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