Semiconductor structure and manufacturing method thereof

Abstract

Embodiments of the present disclosure provide a semiconductor structure including a substrate. The substrate comprises active regions and isolation regions located between the active regions. A first end of each active region has a first head portion, a second end of each active region has a second head portion, and a middle portion of each active region has a waist portion. In a top view, the first head portion and the second head portion of each active area respectively have a first width, and the waist portion of each active area has a second width. And the first width is greater than the second width. In addition, the invention also provides a manufacturing method of the semiconductor structure. According to the embodiment of the invention, the contact resistance can be reduced, and the current performance of the S / D region in the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor structure including an active region having a hammerhead shape and a manufacturing method thereof. Background Art

[0002] As electronic devices become lighter and thinner, semiconductor devices such as dynamic random access memory (DRAM) are becoming more highly integrated. In addition, the performance of DRAM is improved by shortening the pitch between semiconductor structures in DRAM. As the size of semiconductor structures decreases, in addition to increasing the difficulty of the process, the components in the semiconductor structure are also prone to leakage due to the close pitch.

[0003] Therefore, in the semiconductor manufacturing process, how to reduce leakage to improve the process yield of the semiconductor structure becomes an important issue. Summary of the invention

[0004] Some embodiments of the present disclosure provide a semiconductor structure, and the semiconductor structure includes a substrate. The substrate includes a plurality of active regions and a plurality of isolation regions located between the active regions. The first end of each active region has a first head, the second end of each active region has a second head, and the middle portion of each active region has a waist. In a top view, the first head and the second head of each active region respectively have a first width, and the waist of each active region has a second width. In addition, the first width is greater than the second width.

[0005] In some embodiments, the percentage difference between the first width and the second width is 20% to 30%.

[0006] In some embodiments, a maximum ratio between the first width and the second width is 10:8.

[0007] In some embodiments, a minimum ratio between the first width and the second width is 10:7.

[0008] In some embodiments, the first width is 20 nanometers, and the second width is 14 nanometers to 16 nanometers.

[0009] In some embodiments, the semiconductor structure further includes a plurality of source / drain regions. The source / drain regions are disposed in each active region and between the isolation regions.

[0010] In some embodiments, the semiconductor structure further includes a plurality of word line structures extending through the isolation region and the active region.

[0011] In some embodiments, an average of 3 to 4 word line structures are disposed in each active region.

[0012] In some embodiments, one of the source / drain regions shares an adjacent word line structure and is controlled by the adjacent word line structure.

[0013] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, comprising the following steps. A substrate is provided. A plurality of isolation regions are formed in the substrate to define a plurality of active regions; and the two ends of each active region located on the top surface of the substrate have a first width, respectively, and the middle portion of each active region located on the top surface of the substrate has a second width, and the first width is greater than the second width. In addition, a plurality of word line structures are formed on the top surface of the substrate.

[0014] In some embodiments, forming an isolation region in a substrate comprises the following steps: forming a mask on a top surface of the substrate; exposing a plurality of portions not covered by the mask; etching the exposed portions to form a plurality of openings; and depositing a first dielectric layer in the openings and above the substrate.

[0015] In some embodiments, the percentage difference between the first width and the second width is 20% to 30%.

[0016] In some embodiments, the first width is 20 nanometers, and the second width is 14 nanometers to 16 nanometers.

[0017] In some embodiments, after the isolation region and the active region are formed, a top surface of the isolation region and a top surface of the active region are coplanar.

[0018] In some embodiments, the method further comprises the following steps: forming a plurality of source / drain regions in the active region.

[0019] In some embodiments, an average of 3 to 4 word line structures are disposed in each active region.

[0020] In some embodiments, one of the source / drain regions shares an adjacent word line structure and is controlled by the adjacent word line structure.

[0021] In some embodiments, forming the plurality of word line structures comprises the following steps: forming a plurality of first trenches having a first depth in the active region and the isolation region, depositing a conductive layer in the first trenches, and depositing a capping layer in the first trenches and on the conductive layer.

[0022] In some embodiments, forming a word line structure includes the following steps: Before depositing the conductive layer, a dielectric liner is deposited in the first trench.

[0023] In some embodiments, a dielectric liner surrounds the conductive layer and the capping layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following embodiments are read in conjunction with the accompanying drawings to clearly understand the concepts of the present disclosure. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of discussion.

[0025] Figures 1 to 5 is a schematic diagram of a method for manufacturing a semiconductor structure according to some embodiments of the present invention during the formation of a hammerhead-shaped active region;

[0026] Figures 6 to 10 is a schematic diagram of a method of manufacturing a semiconductor structure during the formation of a plurality of word line structures according to some embodiments of the present disclosure; and

[0027] Fig.11 is a schematic diagram of a semiconductor structure according to some embodiments of the present invention. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0029] Additionally, for ease of description, spatially relative terms such as "on," "above," "below," and "between" may be used in the present disclosure to describe the relationship of one element or feature to another element as shown in the drawings) or function. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in the present disclosure should be interpreted accordingly.

[0030] The terms "including", "having", "comprising" and the like used in this disclosure are open terms, meaning including but not limited to.

[0031] It should be noted that when the following drawings (such as Figures 1 to 10 ) is described and illustrated as a series of operations or steps, the order in which these operations or steps are described should not be limited. For example, some operations or steps may be performed in a different order than in the present disclosure, or some operations or steps may occur simultaneously, or some operations may not be performed, and / or some operations or steps may be repeated. In addition, the actual operations or steps of the process stage may need to be performed before the semiconductor structure (e.g., Fig.10 Additional operations or steps are performed before, during, or after the semiconductor structure 100 in the embodiment to complete the semiconductor structure 100. Therefore, the present disclosure may briefly describe some of these additional operations or steps. In addition, unless otherwise specified, for the following figures (e.g. Figures 1 to 10 )The same explanations discussed above can be directly applied to the other figures.

[0032] In the prior art, an array-type semiconductor structure (i.e., an active region in a semiconductor structure arranged in an array in a top view) is formed by a long and narrow active region, which causes the problem of excessive resistance value of the cell side contact (e.g., the two ends of each active region). In fact, due to the reduction in the size of the semiconductor structure, the resistance value of each active region will increase significantly. Therefore, some embodiments of the present disclosure increase the size of the cell side of each active region (e.g., the two ends of each active region) and reduce the size of the digital side of each active region (e.g., the middle part of each active region) to reduce the resistance value and increase the current of each source / drain region. In other words, the embodiments of the present disclosure change the narrow and long active region into a hammer-head shape active region to reduce the resistance and increase the current of each source / drain region.

[0033] The embodiment of the present invention provides a method for manufacturing a semiconductor structure 100 having a plurality of hammerhead-shaped active regions AA to reduce the resistance of the source / drain regions and increase the current. Figures 1 to 5 , Figures 1 to 5 is a schematic diagram of a method for manufacturing a semiconductor structure 100 during formation of a hammerhead-shaped active region AA according to some embodiments of the present invention, wherein Figure 1 is a top view of a semiconductor structure 100 having a plurality of active regions AA and a plurality of isolation regions 110 in a hammerhead shape according to some embodiments of the present invention; Figures 2 to 5 According to some embodiments of the present disclosure, Figure 1 The NN′ section line in FIG. 1 is a cross-sectional view of one of the periods during which the hammerhead-shaped active area AA is formed.

[0034] like Figure 2 As shown, a substrate 102 is provided. In some embodiments, the substrate 102 may include silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. The substrate 102 may include an elemental semiconductor, such as germanium. In some embodiments, the substrate 102 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium indium phosphide, or other suitable materials. In some embodiments, the substrate 102 may include a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), or other suitable materials. In addition, in some embodiments, the substrate 102 may selectively have a semiconductor-on-insulator (SOI) structure.

[0035] In order to form an active region AA (eg Figure 1) and the isolation region 110 (as shown Figure 1 As shown in FIG. 1 , a mask 104 is formed on the top surface of the substrate 102. After the mask 104 is formed, the active area AA (as shown in FIG. Figure 1 ) will be covered and will become the isolation area 110 (as shown in FIG. Figure 1 The other part (hereinafter referred to as the exposed part) of the mask 104 is exposed. Then, the exposed part is exposed by the photolithography process PL. In some embodiments, the mask 104 is a hard mask. In some embodiments, the material of the mask 104 is silicon nitride.

[0036] Next, see Figure 3 , an etching process is performed to remove the upper portion of the exposed portion of the substrate 102 to form a plurality of openings OP. In addition, each opening OP has a first depth D1. In some embodiments, the etching process for removing the upper portion of the exposed portion of the substrate 102 is a dry etching process, a wet etching process, or any appropriate etching process. Then, the mask 104 (such as Figure 2 In some embodiments, the planarization process is a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof. Figure 3 The number of the openings OP shown is 3, but the present disclosure is not limited thereto.

[0037] Also, see Figure 4 , in the opening OP (such as Figure 3 1 and 102. In some embodiments, the first dielectric layer 106 is formed of any suitable dielectric material. In some embodiments, the dielectric material may include an oxide, such as silicon oxide. In some embodiments, the first dielectric layer 106 is formed by using an atomic layer deposition process, other suitable techniques, or a combination thereof.

[0038] Then, if Figure 5 As shown, a plurality of source / drain (S / D) regions 120 are formed in the active region AA of the substrate 102. More specifically, by removing the redundant first dielectric layer 106. Figure 3 After the first dielectric layer 106 is deposited on the substrate 102 (as shown in FIG. 1 ), a planarization process is performed. In some embodiments, the planarization process is a CMP process, an etching process, or a combination thereof. After the planarization process, the active region AA and the isolation region 110 are formed. Moreover, the top surface of the active region AA is coplanar with the top surface of the isolation region 110 (within process variations). Although Figure 5 The numbers of the active area AA and the isolation area 110 shown are 2 and 3 respectively, but the disclosure is not limited thereto.

[0039] Further, please return to Figure 1 After the active area AA is formed, the technical features of the hammer-shaped active area AA are described below. The first end of each active area AA has a first head 122, and the first head 122 refers to the widest part of the first end of each active area AA. The second end of each active area AA has a second head 124, and similarly, the second head 124 refers to the widest part of the second end of each active area AA. The middle part of each active area AA has a waist 126, and the waist 126 refers to the narrowest part of the middle part of each active area AA. The first head 122 and the second head 124 of each active area AA respectively have a first width W1, and the waist 126 of each active area AA has a second width W2. In addition, the first width W1 is greater than the second width W2. In some embodiments, the difference percentage between the first width W1 and the second width W2 is 20% to 30%. In some embodiments, the maximum ratio between the first width W1 and the second width W2 is 10:8. In some embodiments, the minimum ratio between the first width W1 and the second width W2 is 10:7. For example, when the first width W1 is 20 nanometers (nm), the second width W2 is 14nm to 16nm, but the present disclosure is not limited thereto. It should be noted that when the second width W2 is less than 14nm, the manufacturing of the active area AA is difficult, and the subsequent manufacturing process of the word line structure and the bit line structure will also be affected. When the second width W2 is greater than 16nm, the effect of reducing the source / drain region resistance and increasing the current cannot be achieved.

[0040] For further information, see Figure 5 In order to form the S / D regions 120, an ion implantation process may be performed on the substrate 102 to dope an N-type or P-type dopant into the active region AA of the substrate 102. In some embodiments, the N-type dopant may include phosphorus or arsenic, and the P-type dopant may include boron or boron fluoride. In addition, each S / D region 120 has a second depth D2. In addition, the second depth D2 of the S / D region 120 is less than the first depth D1 of each isolation region 110.

[0041] See also Figures 6 to 10 . Figures 6 to 10 is a schematic diagram of a method for manufacturing a semiconductor structure 100 during the formation of a plurality of word line structures WL according to some embodiments of the present disclosure, wherein Figure 6 is a top view of a semiconductor structure 100 having a word line structure WL according to some embodiments of the present disclosure; Figures 7 to 10 According to some embodiments of the present disclosure, Figure 6 The cross-sectional view along the NN′ line is a cross-sectional view during the formation of one of the word line structures WL.

[0042] like Figure 6 and Figure 7As shown, a word line structure (eg, Fig.10 More specifically, the first trenches TC1 are formed by photolithography and etching. Figure 6 Similar to the figure, the first trench TC1 extends through the isolation region 110 and the active region AA. In addition, the first trenches TC1 that will become the word line structure WL are densely distributed in the top view, for example but not limited to, 3 to 4 first trenches TC1 are distributed between each active region AA.

[0043] Then, if Figure 7 As shown, the etching depth of each first trench TC1 is the third depth D3. The third depth D3 is greater than the second depth D2 of each S / D region 120. Figure 7 The number of the first trenches TC1 is 7, but the present disclosure is not limited thereto.

[0044] Furthermore, if Figure 8 As shown in FIG. 1 , a plurality of second trenches TC2 are respectively formed in the first trenches TC1. Similarly, in the top view, the second trenches TC2 extend through the isolation region 110 and the active region AA. More specifically, in the first trenches TC1 (eg Figure 7 A thin dielectric liner 132r is deposited in the first trench TC1 as shown. The fourth depth D4 is less than the third depth D3 of each first trench TC1. In some embodiments, the dielectric liner 132r is formed by an atomic layer deposition process, other appropriate techniques, or a combination thereof. Fig. 9 The number of the second trenches TC2 is 7, but the present disclosure is not limited thereto.

[0045] Then, if Fig. 9 As shown, a conductive layer 134 is deposited in each second trench TC2. More specifically, the conductive layer 134 is formed in each second trench TC2 and contacts the bottom portion of the dielectric liner 132r and the side portion of the dielectric liner 132r. The conductive layer 134 is located at least partially overlapping with each S / D region 120, that is, the S / D region 120 is disposed on the opposite side of the conductive layer 134. In some embodiments, the conductive layer 134 is formed of any suitable conductive material, such as a semiconductor, a metal, a metal nitride, a metal silicide, other suitable conductive materials or a combination thereof. For example, the conductive layer 134 may include doped polysilicon, titanium (Ti), tungsten (W), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), other suitable conductive materials or a combination thereof.

[0046] Then, if Fig.10As shown, a capping layer 136 is formed in each second trench TC2 and on the conductive layer 134. In some embodiments, the material of the capping layer 136 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In addition, after forming the capping layer 136, a planarization process is performed. In some embodiments, the planarization process is a CMP process, an etching process, or a combination thereof.

[0047] exist Fig.10 After the steps, the semiconductor structure 100 having the hammerhead-shaped active region AA is completed. Fig.10 As shown in FIG. 1 , since the area of ​​each active region AA increases, the number of word line structures WL covering each active region AA also increases. As a result, the word line structures WL are distributed quite densely in the top view. For example, but not limited to, 3 to 4 word line structures WL are arranged in each active region on average. Therefore, one S / D region 120 can share adjacent word line structures WL and be controlled by adjacent word line structures WL. Although in Fig.10 The number of word line structures WL in FIG. 7 is 7, but the present disclosure is not limited thereto.

[0048] In addition, an embodiment of the present invention also provides a semiconductor structure 100 including a hammerhead-shaped active region AA. Fig.11 , Fig.11 is a schematic diagram of a semiconductor structure 100 according to some embodiments of the present invention.

[0049] The semiconductor structure 100 includes a substrate 102, and the substrate 102 includes an active region AA and an isolation region 110. The active region AA is defined by a plurality of isolation regions 110. In addition, the isolation regions 110 are located between the active regions AA. Each isolation region 110 has a first depth D1.

[0050] like Figure 6As shown, the first end of each active area AA has a first head 122, and the first head 122 refers to the widest part of the first end of each active area AA. The second end of each active area AA has a second head 124, and similarly, the second head 124 refers to the widest part of the second end of each active area AA. The middle part of each active area AA has a waist 126, and the waist 126 refers to the narrowest part of the middle part of the active area AA. The first head 122 and the second head 124 of each active area AA respectively have a first width W1. The waist 126 of each active area AA has a second width W2. In addition, the first width W1 is greater than the second width W2. In some embodiments, the difference percentage between the first width W1 and the second width W2 is 20% to 30%. In some embodiments, the maximum ratio between the first width W1 and the second width W2 is 10:8. In some embodiments, the minimum ratio between the first width W1 and the second width W2 is 10:7. For example, when the first width W1 is 20nm, the second width W2 is 14nm to 16nm, but the present disclosure is not limited thereto. It should be noted that when the second width W2 is less than 14nm, the manufacturing of the active area AA is difficult, which will also affect the manufacturing process of the word line structure and the bit line structure. When the second width W2 is greater than 16nm, the effect of reducing the source / drain region resistance and increasing the current cannot be achieved.

[0051] In addition, the semiconductor structure 100 further includes S / D regions 120. Each S / D region 120 is disposed in the active region AA and between the isolation regions 110. Each S / D region 120 has a second depth D2, and the second depth D2 is less than the first depth D1.

[0052] like Fig.11 As shown, the semiconductor structure 100 further includes a word line structure WL. In the top view (eg Figure 6 ), each word line structure WL is linear and extends through the isolation region 110 and the active region AA. In addition, each word line structure WL includes a conductive layer 134 and a capping layer 136. The conductive layer 134 refers to the lower portion of each word line structure WL. In some embodiments, the conductive layer 134 is formed of any suitable conductive material, such as a semiconductor, a metal, a metal nitride, a metal silicide, other suitable conductive materials or a combination thereof. For example, the conductive layer 134 may include doped polysilicon, titanium (Ti), tungsten (W), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), other suitable conductive materials or a combination thereof. The capping layer 136 refers to the upper portion of each word line structure WL, and the capping layer 136 is disposed on the conductive layer 134. In some embodiments, the material of the capping layer 136 may include silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.

[0053] In addition, the conductive layer 134 is located at least partially overlapping each S / D region 120. That is, the S / D regions 120 are disposed on opposite sides of the conductive layer 134. Since the word line structures WL of the embodiment of the present invention are quite dense, one S / D region 120 can share and be controlled by an adjacent word line structure WL. Fig.11 The number of the word line structures WL is 7, but the disclosure is not limited thereto.

[0054] In addition, each word line structure WL includes a dielectric liner 132r. The dielectric liner 132r is disposed to surround the conductive layer 134 and the cover layer 136. That is, the conductive layer 134 contacts the bottom portion of the dielectric liner 132r and the side portion of the dielectric liner 132r. And the cover layer 136 contacts the upper portion of the dielectric liner 132r. In addition, each word line structure WL has a third depth D3. The third depth D3 is less than the second depth D2, and the third depth D3 is less than the first depth D1.

[0055] By means of the manufacturing method of the semiconductor structure 100 and the semiconductor structure 100 of the embodiment of the present invention, a hammerhead-shaped active area AA can be obtained. The two ends of each active area AA are wider than the middle part of each active area AA. In this way, the resistance of the unit side contact of each active area AA can be effectively reduced. Moreover, although narrowing the middle part (digital side) of the active area AA may sacrifice a little linear current of each S / D area 120, the maximum current of each S / D area can be significantly increased. Therefore, the embodiment of the present invention can reduce the contact resistance, thereby improving the current performance of the S / D area in the array semiconductor structure.

[0056] Although some embodiments of the present disclosure have been described in considerable detail, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.

[0057] The above briefly describes the features of multiple embodiments of the present disclosure, so that those skilled in the art can more easily understand the present disclosure. Any person skilled in the art should understand that the present disclosure can easily serve as a basis for the change or design of other structures or processes to achieve the same purpose and / or obtain the same advantages as the embodiments of the present disclosure. Any person skilled in the art can also understand that the structures equivalent to the above do not depart from the spirit and scope of protection of the present disclosure, and can be changed, replaced and modified without departing from the spirit and scope of the present disclosure.

[0058]

Explanation of symbols

[0059] 100:Semiconductor structure

[0060] 102:Substrate

[0061] 104: Mask

[0062] 106: first dielectric layer

[0063] 110: Quarantine

[0064] 120: Source / Drain Region / S / D Region

[0065] 122: First Head

[0066] 124: Second Head

[0067] 126: Waist

[0068] 132r: Dielectric liner

[0069] 134: Conductive layer

[0070] 136: Covering layer

[0071] AA: Active Area

[0072] D1: First Depth

[0073] D2: Second Depth

[0074] D3: Third Depth

[0075] D4: Fourth Depth

[0076] PL: Photolithography

[0077] TC1: First groove

[0078] TC2: Second groove

[0079] OP: Opening

[0080] W1: First width

[0081] W2: Second width

[0082] WL: word line structure

[0083] NN': Section line.

Claims

1. A semiconductor structure, characterized in that: include: A substrate including a plurality of active regions and a plurality of isolation regions between the plurality of active regions; The first end of each active region has a first head, the second end of each active region has a second head, and the middle portion of each active region has a waist. In the top view, the first head and the second head of each active region have a first width, and the waist of each active region has a second width, and The first width is greater than the second width.

2. The semiconductor structure according to claim 1, characterized in that: A difference percentage between the first width and the second width is 20% to 30%.

3. The semiconductor structure according to claim 2, characterized in that: A maximum ratio between the first width and the second width is 10:

8.

4. The semiconductor structure according to claim 2, characterized in that: A minimum ratio between the first width and the second width is 10:

7.

5. The semiconductor structure according to claim 2, characterized in that: The first width is 20 nanometers, and the second width is 14 nanometers to 16 nanometers.

6. The semiconductor structure according to claim 1, characterized in that Further including: A plurality of source / drain regions are disposed in each of the active regions and located between the plurality of isolation regions.

7. The semiconductor structure according to claim 6, characterized in that: Further including: A plurality of word line structures extend through the plurality of isolation regions and the plurality of active regions.

8. The semiconductor structure according to claim 7, characterized in that: The number of word line structures disposed in each active area is 3 to 4 on average.

9. The semiconductor structure according to claim 8, characterized in that: One of the plurality of source / drain regions shares the plurality of adjacent word line structures and is controlled by the plurality of adjacent word line structures.

10. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of isolation regions in the substrate to define a plurality of active regions, wherein both ends of the two heads of each active region located on the top surface of the substrate respectively have a first width, a middle portion of each active region located on the top surface of the substrate has a second width, and the first width is greater than the second width; and A plurality of word line structures are formed on the top surface of the substrate.

11. The method according to claim 10, characterized in that Forming the plurality of isolation regions in the substrate comprises: forming a mask on the top surface of the substrate; exposing a plurality of portions not covered by the mask; etching the exposed portions to form a plurality of openings; and A first dielectric layer is deposited in the plurality of openings and over the substrate.

12. The method according to claim 10, characterized in that A difference percentage between the first width and the second width is 20% to 30%.

13. The method according to claim 12, characterized in that The first width is 20 nanometers, and the second width is 14 nanometers to 16 nanometers.

14. The method according to claim 10, characterized in that After forming the plurality of isolation regions and the plurality of active regions, top surfaces of the plurality of isolation regions and top surfaces of the plurality of active regions are coplanar.

15. The method according to claim 10, characterized in that Further including: A plurality of source / drain regions are formed in the plurality of active regions.

16. The method according to claim 15, characterized in that The number of word line structures disposed in each active area is 3 to 4 on average.

17. The method according to claim 16, characterized in that One of the plurality of source / drain regions shares the plurality of adjacent word line structures and is controlled by the plurality of adjacent word line structures.

18. The method according to claim 15, characterized in that Forming the plurality of word line structures comprises: forming a plurality of first trenches having a first depth in the plurality of active regions and the plurality of isolation regions; depositing a conductive layer in each of the first trenches; and A capping layer is deposited in each of the first trenches and on the conductive layer.

19. The method according to claim 18, characterized in that Forming the plurality of word line structures comprises: Before depositing the conductive layer, a dielectric liner is deposited in each of the first trenches.

20. The method according to claim 19, characterized in that The dielectric liner surrounds the conductive layer and the cover layer.

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