A method for forming a memory structure of a 3D NAND flash memory

Abstract

A method for forming a memory structure of a 3D NAND flash memory comprises: forming a layer stack on a substrate, comprising an alternating sequence of gate layers and inter-gate spacer layers; forming a first recessed region in a sidewall of a memory hole by laterally etching back the inter-gate spacer layers from a memory hole; forming a sacrificial layer in the first recessed region; forming a second recessed region in the sidewall by laterally etching back the gate layer from the memory hole; forming a lateral memory stack in the second recessed region by selectively depositing a blocking oxide and depositing a charge trap material in the second recessed region; removing the sacrificial layer by etching from the memory hole; regrowing the inter-gate spacer layers so that the lateral memory stack is vertically separated by the regrown inter-gate spacer layers; forming a tunneling oxide layer in the memory hole; forming a channel layer along the tunneling oxide layer. The method can reliably form an interrupted / cut-off charge trap layer under strong z-pitch scaling.

Description

Technical Field

[0001] The present invention generally relates to a method of forming a memory structure of a 3D NAND flash memory. Background Art

[0002] The bit density in the 3D NAND Flash memory roadmap increases year by year. So far, this growth has been achieved by increasing the number of stacked memory cells (along the vertical dimension). However, this route is becoming increasingly difficult and expensive. As a result, there is a growing interest in scaling cell technologies along the vertical dimension. Vertical scaling ("z-pitch scaling") is achieved by reducing the thickness of layers in the layer stack, such as the wordline (gate) layer and the oxide inter-gate spacer layer.

[0003] Current 3D NAND technology is typically based on so-called charge trap cells, utilizing a charge trap layer (e.g. SiN) as a storage layer. Traditionally, the charge trap layer is deposited as a continuous layer along the sidewalls of the memory hole in the layer stack. Z scaling results in reduced cell-to-cell separation, which in turn may reduce the retention performance of the continuous charge trap layer. Therefore, a scalable technology that allows the formation of interrupted charge trap layers is needed, so that each memory cell can be provided with a separate charge trap layer. Summary of the invention

[0004] It is an object of the present invention to provide a method for forming a memory structure suitable for 3D NAND Flash memory, allowing reliable formation of interrupted / cut-off charge trap layers also under strong z-pitch scaling.

[0005] Therefore, according to one aspect of the present invention, there is provided a method for forming a memory structure of a 3D NAND flash memory, the method comprising:

[0006] forming a layer stack on a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers;

[0007] forming a first recessed region in a sidewall of the memory hole surrounding the layer stack by etching back the inter-gate spacer layer laterally from the memory hole relative to the gate layer;

[0008] forming a sacrificial layer in the first recessed region;

[0009] forming a second recessed region in the sidewall by etching back the gate layer laterally from the memory hole relative to the sacrificial layer;

[0010] forming a lateral memory stack in each second recessed region by selectively depositing a blocking oxide and subsequently depositing a charge trap material in the second recessed region, wherein the sacrificial layer defines a deposition inhibition zone for selective deposition of the blocking oxide and the charge trap material;

[0011] removing the sacrificial layer from the memory hole by etching;

[0012] After removing the sacrificial layer, regrowing the inter-gate spacer layer so that the lateral memory stack is vertically separated by the regrown inter-gate spacer layer;

[0013] After regrowing the inter-gate spacer layer, forming a tunnel oxide layer in the memory hole; and

[0014] A channel layer is formed along the tunnel oxide layer.

[0015] Thus, the method according to the present aspect enables the formation of a memory structure comprising vertically separated lateral memory stacks, each lateral memory stack comprising a discrete charge trapping layer, in particular a respective discrete charge trapping layer for each gate layer or equivalently for each memory cell.

[0016] Rather than depositing a continuous charge trap layer and then "cutting" the charge trap layer into multiple discrete parts by etching, the method uses an area selective deposition process (ASD) to "directly" deposit discrete charge trap layers, in which a sacrificial layer is used to define a deposition inhibition area ("non-growth area"). It is therefore possible to avoid the charge trap material from being deposited in the vertical region between the gate layers, thereby eliminating the need to cut the charge trap material by etching. Since etching is not required, the thickness dimension of the charge trap layer (shown in the lateral dimension) can be precisely controlled by maintaining the growth conditions of the selective deposition until the target thickness is reached. The above discussion applies accordingly to the blocking oxide.

[0017] Because the inter-gate spacer is formed of a dielectric material (typically an oxide), it is conceivable that selectively depositing a blocking oxide and a charge trapping material in the second recessed region (i.e., in the vertical plane of the gate layer) without any significant simultaneous deposition on the inter-gate spacer is challenging. However, by etching back the inter-gate spacer to form a first recessed region in the sidewall, and then forming a sacrificial layer in the first recessed region (e.g., filling the first recessed region with a sacrificial layer material), the area selectivity can be significantly improved. That is, the sacrificial layer material can be selected to promote area selective deposition without regard to its suitability in a finished functional memory device. In general, the sacrificial layer can be formed of a sacrificial layer material that is selected to be deposition inhibiting for the selective deposition of the blocking oxide and the charge trapping material, and is selectively etchable relative to the charge trapping material, the blocking oxide, and the material of the gate layer (e.g., the sacrificial layer material can be etched at a greater rate than each of the charge trapping material, the blocking oxide, and the material of the gate layer).

[0018] Another advantage of the deposition inhibition property of the sacrificial layer is that the risk of pinching off the second recessed region by deposition of blocking oxide or charge trapping material can be avoided.

[0019] In some embodiments, forming the sacrificial layer includes conformally depositing a sacrificial material to fill the first recessed area and cover the sidewalls of the memory hole, and etching back the sacrificial material to expose the end surface of the gate layer at the sidewall. The conformal deposition of the sacrificial material allows the first recessed area to be reliably filled. The subsequent etching back of the sacrificial material removes the sacrificial material deposited outside the first recessed area.

[0020] In some embodiments, forming the sacrificial layer alternatively comprises selectively depositing a sacrificial material in the first recessed region to fill the first recessed region. Thus, similar to the blocking oxide and the charge trapping material, the sacrificial material may be deposited using an ASD process. During the ASD of the sacrificial material, the gate layer may define a deposition inhibition region ("non-growth region"), while the (etched back) inter-gate spacer defines a deposition promotion region.

[0021] In some embodiments, the blocking oxide is laterally grown in the second recessed region to a thickness of 4-12 nm.

[0022] In some embodiments, the charge trap material is laterally grown in the second recessed region to a thickness of 4-8 nm.

[0023] In some embodiments, the gate layer is a nitride-containing layer, such as a SiN layer, or a polysilicon-containing layer. A polysilicon-containing gate layer (e.g., highly doped) can be used as a functionalized gate in a final device. A nitride-containing gate layer allows the formation of a final functionalized gate in a replacement metal gate (RMG) process.

[0024] In some embodiments, the inter-gate spacer layer is an oxide-containing layer, such as a SiO 2 layer.

[0025] In some embodiments, the sacrificial layer is a metal oxide layer (e.g., an Al2O3 or TiO2 layer), a metal nitride layer (e.g., an AlN or TiN layer), a metal layer (e.g., a Co, Ru, Cu, W, or Mo layer), or a carbon-containing layer (e.g., an amorphous carbon or organic spin-coated layer). Any of these types of sacrificial materials aid in process control because they tend to define a deposition-inhibiting surface for the ASD relative to the blocking oxide and charge trapping material. These sacrificial materials further achieve etch selectivity relative to the charge trapping material, the blocking oxide, and the gate layer material (when it is polysilicon or a nitride-containing material). This is particularly applicable to carbon-containing layers, such as amorphous carbon, or organic spin-coated layers.

[0026] In some embodiments, the method further includes functionalizing the etched-back gate layer in the second recessed region before depositing the blocking oxide, and then depositing the blocking oxide on the functionalized surface portion.

[0027] Thus, the surface portions of the etched-back gate layer in the second recessed region may be made more reactive with respect to the deposition process and thus the selectivity of the deposition on these surface portions may be improved.

[0028] By "functionalizing" a surface portion with respect to a subsequent deposition process, it is meant herein any treatment process that renders the surface portion increasingly reactive with respect to the deposition process. Thus, the surface portion may have a stronger tendency to react with one or more precursors of the deposition process. Thus, nucleation of a deposited material (e.g., a barrier oxide) on the functionalized surface portion may be promoted.

[0029] In some embodiments, the functionalization step includes depositing a deposition promoting layer on the surface portion of the etched-back gate layer in the second recessed region, thereby forming a deposition promoting layer (i.e., a "seed layer") and thereby improving the area selectivity of the subsequent selective deposition of the blocking oxide.

[0030] In some embodiments, the method further comprises, prior to depositing the blocking oxide, performing a treatment process suitable for passivating the exposed surface portion of the sacrificial layer relative to the selective deposition of the blocking oxide and the charge trapping material. Thus, the deposition inhibition characteristics of the exposed surface portion of the sacrificial layer may be increased relative to the corresponding ASD process of the blocking oxide and the charge trapping material. Thus, the exposed surface portion of the sacrificial layer may have a smaller tendency to react with one or more precursors of the deposition process. Thus, nucleation of the blocking oxide and the charge trapping material on the sacrificial layer may be further hindered. It should be noted that the treatment process may also be performed in place of or in addition to the above-described functionalization step.

[0031] In some embodiments, the method further includes selectively depositing a dielectric liner on the gate layer in the second recessed region, and then selectively depositing a blocking oxide on the dielectric liner.

[0032] Therefore, prior to the deposition of the lateral memory stack, a dielectric liner may be deposited on the etched-back gate layer (or on the deposition promoting layer if functionalized according to the aforementioned embodiment). The dielectric liner may form a gate dielectric between the gate layer and the lateral memory stack by itself or in combination with an additional gate dielectric deposited during a subsequent replacement metal gate (RMG) process. The dielectric liner may be formed in particular of a high-k dielectric material.

[0033] In some embodiments, the gate layer (e.g., a nitride-containing gate layer) is a sacrificial gate layer, and the method further includes replacing the sacrificial gate layer with a replacement metal gate stack after depositing the blocking oxide and the charge trapping material. Thus, the sacrificial gate layer can be replaced by the functionalized metal gate stack through an RMG process. The sacrificial gate layer can be removed from a second hole (different from the memory hole) in the layer stack by etching back the sacrificial gate layer, and then forming a replacement metal gate stack to replace the sacrificial gate layer.

[0034] In some embodiments, the method further comprises selectively depositing a dielectric liner on the gate layer in the second recessed region, and then selectively depositing a blocking oxide on the dielectric liner, and using the dielectric liner as an etch stop when removing the sacrificial gate layer to be replaced by the replacement metal gate stack. Thus, the lateral memory stack (especially the blocking oxide) can be protected from the etching chemistry used when removing the sacrificial gate layer as part of the RMG process. Another advantage related to Z scaling is that the limited vertical space available for the metal gate stack does not need to accommodate the gate dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] This and other aspects of the invention will now be described in more detail, with reference to the appended drawings showing embodiments of the invention.

[0037] Figure 1a -b schematically show a schematic cross-sectional view and a schematic top view of a starting structure for forming a memory structure according to one embodiment.

[0038] Figure 2 The structure after forming the first recessed region is shown.

[0039] Figure 3 The structure after forming a sacrificial layer in the first recessed region is shown.

[0040] Figure 4 The structure after forming the second recessed region is shown.

[0041] Figure 5 The structure is shown after deposition of a blocking oxide in the second recessed region.

[0042] Figure 6 The structure is shown after depositing a charge trap material in the second recessed region.

[0043] Figure 7 The structure is shown after removal of the sacrificial layer.

[0044] Figure 8 The structure is shown after regrowth of the inter-gate spacers.

[0045] Fig. 9 The structure is shown after forming a tunnel oxide layer and a channel layer.

[0046] Fig.10 A structure is shown in which a dielectric liner is formed in the second recessed region before depositing the blocking oxide according to another embodiment.

[0047] Fig.11 Shown according to Fig.10 A lateral memory stack is formed.

[0048] Fig.12 A lateral memory stack formed in accordance with another embodiment is shown.

[0049] Fig.13 The formation of a sacrificial layer according to another embodiment is shown. DETAILED DESCRIPTION

[0050] Embodiments of a method for forming a memory structure for a 3D NAND flash memory [e.g., a 3D-Gate-All Around-NAND (3D GAA NAND)] will now be described with reference to the accompanying drawings. The drawings are schematic only, and the relative sizes of some structures and layers may be exaggerated and not drawn to scale. Instead, the sizes may be adjusted for clarity of illustration and ease of understanding. When appearing in the accompanying drawings, the indicated axes X, Y, and Z uniformly refer to a first horizontal or lateral direction, a second horizontal or lateral direction, and a vertical direction, respectively. As used herein, the terms "horizontal" and "lateral" refer to directions parallel to (the main surface of) the supporting substrate of the memory structure. The term "vertical" refers to a direction parallel to the vertical direction of (the main surface of) the substrate, i.e., a direction that crosses the substrate.

[0051] Figure 1a -b schematically show a schematic cross-sectional view and a schematic top view, respectively, of a structure 1 at an initial stage of the method. The structure 1 comprises a layer stack 10 representing a precursor or starting structure of a memory structure, which will undergo the processing steps of the method disclosed below.

[0052] A layer stack 10 is formed on a substrate 2 , the layer stack comprising an alternating sequence of gate layers 14 and inter-gate spacer layers 12 .

[0053] The substrate 2 may be a conventional substrate suitable for semiconductor processing and suitable for providing support for the memory structure of the 3D NAND flash memory. For example, the substrate 2 may be a Si substrate, a Ge substrate, or a SiGe substrate. Other examples include a silicon-on-insulator (SOI) substrate, a GeOI substrate, or a SiGeOI substrate.

[0054] The gate layer 14 may be a nitride-containing layer, such as a SiN layer, thereby forming a sacrificial gate layer 14 intended to be replaced by an RMG stack in a subsequent process step. The gate layer 14 may also be a functionalized gate layer, such as a highly doped polysilicon-containing layer.

[0055] The inter-gate spacer 12 may be an oxide-containing layer, such as a SiO2 layer, or another suitable inter-layer dielectric (such as a low-k dielectric). The inter-gate spacer 12 is disposed in the layer stack 10 to provide vertical separation between memory cells / word lines in the memory device to be formed.

[0056] The layer stack 10 may be composed of interchangeable deposited layers of gate material (e.g. nitride) and inter-gate spacer material (e.g. oxide) obtained by a deposition process known per se in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0057] The number of inter-gate spacer layers 12 and gate layers 14 formed may be determined based on the expected number of stacked memory cells of the memory device. It should be noted that the number of layers 12, 14 of the layer stack 10 shown is merely a non-limiting example, and the methods disclosed herein are compatible with stacks of any number of memory cells currently used or envisioned in the industry, such as 64, 128, 256 or more.

[0058] For example, the inter-gate spacer layer 12 and the gate layer 14 may each be formed with a respective layer thickness of 5 nm to 25 nm. The z-pitch of the layer stack 10 (ie, the combined thickness of one inter-gate spacer layer and one gate layer 14) may be about 45 nm to 15 nm or less.

[0059] As shown, the layer stack 10 further comprises a capping layer in the form of a semiconductor layer 16, which is deposited on top of the topmost inter-gate spacer layer 12. For example, the semiconductor layer 16 may be formed of Si.

[0060] After deposition of layers 12 and 14 (and optionally 16) of layer stack 10, memory holes 4 may be patterned in layer stack 14, for example, by photolithography and etching processes. Figure 1a -b shows a portion of the layer stack 10 surrounding a single memory hole 4, but it should be noted that a corresponding memory hole 4 can be patterned at each location where a respective vertical memory cell string is needed. As shown, the memory hole 4 can be formed to extend through each of the inter-gate spacer layer 12 and the gate layer 14 of the layer stack 10. Figure 1bAs further shown in the top view of FIG. 4 , the memory hole 4 can form a circular cross-sectional shape, so that the memory hole 4 can form a substantially cylindrical shape. However, the memory hole 4 can also form other cross-sectional shapes, such as an ellipse or a polygon.

[0061] Although not in Figure 1a As shown in FIG. 1 , as is known in the art per se, the layer stack 10 also includes a sub-stack of a selection layer and a source layer below the layers 12 and 14, for forming a selection plate and a source plate of a memory device, respectively. Thus, the selection layer and the source layer may form a bottom sub-stack of the layer stack 10. The selection layer and the source layer may be formed by conventional techniques and materials, such as doped semiconductor layers (e.g., polysilicon), and separated by an interlayer dielectric layer.

[0062] exist Figure 2 In the embodiment of the present invention, a first recessed region 18 is formed in the sidewall of the layer stack 10 surrounding the memory hole 4 by laterally etching back the inter-gate spacer layer 12 from the memory hole 4 relative to the gate layer 14. The inter-gate spacer layer 12 is selectively laterally etched back (along the X-axis) to the gate layer 14, thereby forming the first recessed region 18 between the gate layers 14. That is, each of the recessed regions / recesses in the first recessed regions 18 is formed between a pair of gate layers 14. Since the sidewalls extend around the circumference of the memory hole 4, the first recessed region 18 may extend circumferentially around the memory hole 4. In the example of a circular memory hole 4, the first recessed region 18 may be annular.

[0063] The inter-gate spacer 12 may be etched back using an etching process suitable for selectively etching the inter-gate spacer 12 relative to the gate layer 14. That is, the etching process may be suitable for selectively etching (i.e., removing) the material (e.g., oxide material) of the inter-gate spacer 12 relative to the material (e.g., nitride material) of the gate layer 14, so that the inter-gate spacer 12 may be laterally etched back without causing substantial etching back of the gate layer 14. The etching process may be applied to the sidewalls of the layer stack 10 via the memory hole 4. Any suitable selective etching process (wet or dry) may be used to provide a sufficient lateral etching component relative to the inter-gate spacer 12 (e.g., an isotropic etching process).

[0064] Having semiconductor layer 16 as the top layer of layer stack 10 ensures that the topmost inter-gate spacer layer 12 can also be recessed. That is, semiconductor layer 16 can act as an etch mask for the topmost inter-gate spacer layer 12 to counteract its vertical etch back during the lateral etch back.

[0065] The depth of the first recessed region 18 (along the X-axis) is at least equal to or exceeds the expected lateral thickness of the charge trap material 26 of the lateral memory stack 27 (optionally, the complete lateral memory stack 27) formed at the level of the gate layer 14 (see below). Figure 5-6 For example, the depth of the first recessed region 18 (ie, the amount of lateral etch-back) may be between 4 and 40 nm. The depth of the recessed region 18 may be controlled by the timing of the lateral etch-back.

[0066] exist Figure 3 A sacrificial layer 20 is formed in the first recessed region 18. As shown, the sacrificial layer 20 is formed to fill (i.e., refill) the first recessed region 18. As a result, the sidewalls around the memory hole 4 can be restored to a substantially straight profile. The sacrificial layer 20 defines a temporary locator for the gate spacer 12 to be regrown later. The sacrificial layer 20 is formed of a sacrificial material that is selected to be deposition-inhibiting for the subsequent selective deposition of the blocking oxide and the charge trap material. The sacrificial material should also be selected to be a material that can be selectively etched relative to the material of the lateral memory stack 27, so that the sacrificial layer 20 can be removed at a subsequent stage of the method without removing the lateral memory stack 27. Example materials of the sacrificial layer 20 include a metal oxide layer (e.g., an Al2O3 layer or a TiO2 layer), a metal nitride layer (e.g., an AlN layer or a TiN layer), a metal layer (e.g., a Co layer, a Ru layer, a Cu layer, a W layer, or a Mo layer), or a carbon-containing layer (e.g., an amorphous carbon layer or an organic spin-coated layer).

[0067] The sacrificial layer 20 may be formed by selectively depositing a sacrificial material using an ASD process to fill the first recessed region 18, wherein the gate layer 14 defines a non-growth region and the inter-gate spacer layer 12 defines a growth region relative to the ASD process. The deposition of the sacrificial material continues until the first recessed region 18 is filled with the sacrificial material and the inner end surface of the sacrificial layer 20 (i.e., facing inward relative to the memory hole 4) is substantially flush with the inner end surface of the gate layer 14.

[0068] Fig.13 An alternative method for forming the sacrificial layer 20 is depicted, the method comprising conformally depositing a sacrificial material layer 201 (e.g., by ALD) to fill the first recessed region 18 and cover the sidewalls of the memory hole 4. The sacrificial material layer 201 may then be etched back (e.g., using an isotropic etch) to expose the inner end surface of the gate layer 14 at the sidewalls of the memory hole 4.

[0069] exist Figure 4 In the embodiment, the second recessed region 22 is formed in the sidewall surrounding the memory hole 4 by etching back the gate layer 14 laterally from the memory hole 4 relative to the sacrificial layer 20 .

[0070] The gate layer 14 is selectively etched back laterally (along the X-axis) to the sacrificial layer 20, thereby forming a second recessed region 22 between the sacrificial layers 20. That is, each recessed region / recess of the second recessed region 22 is formed between a pair of sacrificial layers 20. Since the sidewalls extend around the circumference of the memory hole 4, the second recessed region 22 may extend circumferentially around the memory hole 4. In the example of a circular memory hole 4, the second recessed region 22 may be annular.

[0071] The gate layer 14 may be etched back using an etching process suitable for selectively etching the gate layer 14 relative to the sacrificial layer 20. That is, the etching process may be suitable for selectively etching (i.e., removing) the material (e.g., nitride material) of the gate layer 14 relative to the sacrificial material of the sacrificial layer 20, so that the gate layer 14 may be laterally etched back without causing substantial etching back of the sacrificial layer 20. The etching process may be applied to the sidewalls of the layer stack 10 via the memory hole 4. Any suitable selective etching process (wet or dry) may be used to provide a sufficient lateral etching component relative to the gate layer 14 (e.g., an isotropic etching process).

[0072] The depth of the second recessed region 22 (along the X-axis) corresponds to the expected lateral thickness of a lateral memory stack 27 formed at the level of the gate layer 14 (see below). Figure 5-6 For example, the depth of the second recessed region 22 (ie, the amount of lateral etch-back) may be between 6 nm and 20 nm. The depth of the second recessed region 22 may be controlled by the timing of the lateral etch-back.

[0073] By forming the second recessed region 22 having a smaller lateral depth than the first recessed region 18, the inter-gate spacer layer 12 may be masked during the etching back of the gate layer 14 (e.g., because the inter-gate spacer layer 12 may be masked by the sacrificial layer 20 and the (etched back) gate layer 14). If this is not the case, the etching process used to etch back the gate layer 14 may advantageously be adapted to selectively etch the material of the gate layer 14 (e.g., nitride material) relative to the sacrificial material of the sacrificial layer 20 and the material of the inter-gate spacer layer 12 (e.g., oxide).

[0074] Figure 5-6 The method of selectively depositing a blocking oxide 24 ( Figure 5 ) and subsequently depositing a charge trap material 26 ( Figure 6) to form a lateral memory stack 27 in each second recessed region 22. Therefore, the blocking oxide 24 and the charge trap material 26 are selectively deposited, wherein the sacrificial layer 20 defines a deposition inhibition region (non-growth region) for the selective deposition of the blocking oxide 24 and the charge trap material 26. Since the blocking oxide 24 and the charge trap material 26 are selectively deposited in the second recessed region 22, the blocking oxide 24 can define a discrete blocking oxide layer (which may also be referred to by the reference numeral 24 hereinafter) in each second recessed region 22, and the charge trap material 26 can form a discrete charge trap layer (which may also be referred to by the reference numeral 26 hereinafter).

[0075] The blocking oxide 24 may include SiO x (e.g., SiO2) or some other oxide material suitable for use as a blocking oxide. The blocking oxide 24 may be deposited using any deposition process (e.g., ALD or CVD process) that allows for area-selective deposition of the blocking oxide 24 (e.g., SiO2), such that the blocking oxide 24 is deposited on a growth-promoting surface portion or a seed surface portion in the second recessed region 22, but not on a growth-inhibiting region defined by the sacrificial layer 20. The growth-promoting surface portion may specifically be a surface portion of the etched-back gate layer 14 exposed in the second recessed region 22 (i.e., Figure 4 The end face 14a) shown is delimited.

[0076] The charge trap material 26 may include or be SiN (e.g., Si3N4). SiN represents an efficient and reasonable implementation of a charge trap memory cell. However, it is contemplated that the present method is also compatible with other choices of charge trap materials, as long as they can be deposited in the second recessed region 22 in a regionally selective manner, for example, on the etched-back gate layer 14. The charge trap material 26 may be deposited using any deposition process (e.g., ALD or CVD process) that allows for regional selective deposition of the charge trap material 26 (e.g., SiN), such that the charge trap material 26 is deposited on a growth promoting surface portion or a seed surface portion in the second recessed region 22, but not on a growth inhibiting region defined by the sacrificial layer 20. The growth promoting surface portion may specifically be defined by an already deposited blocking oxide 24.

[0077] Prior to depositing the blocking oxide 24, the layer stack 10 may be subjected to a treatment step to promote the selective deposition of the blocking oxide 24, the treatment step being suitable for functionalizing the surface portion / end face 14a of the etched-back gate layer 14 in the second recessed area 22, and subsequently depositing the blocking oxide 24 on the functionalized surface portion in the second recessed area 22. For example, Figure 4As schematically shown in one of the recessed regions 22 of the functionalization process, the functionalization process may include depositing a deposition promoting layer 15 on a surface portion 14a of the etched-back gate layer 14 in the second recessed region. Additionally or alternatively, the layer stack 10 may be subjected to a treatment process that is suitable for passivating the exposed surface portion of the sacrificial layer 20 (relative to the selective deposition of the blocking oxide 24 and the charge trap material 26). For example, as is known in the art itself, some deposition processes are favorable for deposition on hydrogen terminated surfaces (e.g., the deposition process preferentially deposits material on the hydrogen terminated surface). Therefore, the treatment process may be suitable for increasing the occurrence of hydrogen terminated bonds on the gate layer 14 (thereby promoting deposition on the hydrogen terminated surface) and / or reducing the occurrence of hydrogen terminated bonds on the sacrificial layer 20 (thereby inhibiting deposition on the hydrogen terminated surface). However, this is merely a non-limiting example, and other techniques are known to those skilled in the art.

[0078] As an illustrative example, the gate layer 14 may be a SiN layer and the sacrificial layer 20 may be an Al2O3 layer, wherein the blocking oxide 24 (SiO2) may be selectively deposited by a plasma enhanced ALD (PEALD) process comprising repeatedly performing a deposition cycle of: A) passivating the sacrificial layer 20 using acetylacetone, B) introducing a Si precursor bis(diethylamino)silane (BDEAS), and C) providing an O2 plasma as a co-reactant. The acetylacetone will initiate grafting of the Al2O3 surface, thereby making the surface of the sacrificial layer 20 (but not the SiN of the gate layer 14) inert with respect to the Si precursor, allowing the blocking oxide (SiO2) to be selectively deposited in the second recessed region 22. The selective deposition of the charge trap material 26 (SiN) may be achieved in a corresponding manner, i.e., using a PEALD process, comprising repeatedly performing the following deposition cycles: A) passivation of the sacrificial layer 120, B) introducing a Si precursor, and C) providing an N2 or NH3 plasma. Various other variations of these methods are contemplated herein. For example, the sacrificial layer 20 may be formed of other metal oxides (e.g., TiO2). The passivation of the sacrificial layer 20 may be achieved by using organic carboxylic acids such as pivalic acid, butyric acid, etc. Some other relatively large Si precursors may be used instead of BDEAS. In addition, a thermal ALD process may be used instead of a PEALD process.

[0079] The blocking oxide 24 may be grown laterally (along the X-axis) in the second recessed regions 22 to form a blocking oxide layer having a thickness (along the X-axis) in the range of 4-12 nm in each second recessed region 22. The charge trap material 26 may be grown laterally (along the X-axis) in the second recessed regions 22 to form a charge trap layer having a thickness (along the X-axis) in the range of 4-8 nm in each second recessed region 22. More generally, the deposition of the charge trap material 26 may continue until the second recessed regions 22 are filled with the charge trap material and the inner end surface of the charge trap material / layer 26 (i.e., facing inward relative to the memory hole 4) is substantially flush with the inner end surface of the sacrificial layer 20. Thus, the lateral memory stack 27 may fill the lateral depth of the second recessed regions 22, whereby the sidewalls surrounding the memory hole 4 may be restored to a substantially straight profile.

[0080] exist Figure 7 In the embodiment, the sacrificial layer 20 is removed from the layer stack 10 by etching the sacrificial layer 20 from the memory hole 4. The sacrificial layer 20 may be removed by selective etching, which is selective etching of the sacrificial material relative to the charge trap material 26 and the blocking oxide 24. Any suitable selective etching process (wet or dry) may be used to provide a sufficient lateral etching component relative to the sacrificial layer 20 (e.g., an isotropic etching process). By removing the sacrificial layer 20, the first recessed region (at Figure 8 and later marked as 28) can be restored or reopened.

[0081] Figure 8 The structure 1 is described after removing the sacrificial layer 20 and regrowing the gate spacer 12 in the restored first recessed region 28. As a result, the lateral memory stack 27 (including the blocking oxide 24 and the charge trap material 26) in the second recessed region 22 is vertically separated by the regrown gate spacer 12. The gate spacer 12 can be regrown by a process that includes depositing an oxide material (e.g., SiO2) of the gate spacer 12, for example, using a conformal deposition process (e.g., ALD). Both area-selective and non-area-selective deposition techniques are possible. For example, a selective oxide-on-oxide deposition process can be used to re-deposit the oxide material on the gate spacer 12. Using a non-area-selective deposition technique, the oxide material can be conformally deposited to fill the first recessed region 28 and cover the sidewalls of the memory hole 4 (e.g., including the charge trap material 26), and then laterally etched back to expose the inner end surface of the charge trap material 26 at the sidewalls of the memory hole 4.

[0082] exist Fig. 9, a tunneling oxide layer 30 and a subsequent channel layer 32 are formed in the memory hole 4 along its sidewalls. Therefore, the tunneling oxide layer 30 is formed along the discrete charge trap layers 26 of the lateral memory stack 27 (more specifically along or in contact with the corresponding inner end surfaces of the charge trap layers 26). The tunneling oxide layer 30 and the channel layer 32 can each be conformally deposited, for example, using a corresponding ASL process. After the tunneling oxide layer 30 is deposited, the tunneling oxide layer 30 can be anisotropically etched in a top-down orientation (opposite to the Z-axis direction) to remove some portions of the tunneling oxide layer 30 deposited on the horizontally oriented surface of the structure 1.

[0083] Tunnel oxide layer 30 may be formed of any material conventionally used in the industry for tunnel oxide layers, one non-limiting example being SiON. Channel layer 32 may similarly be formed of any suitable channel material conventionally used in the industry for channel layers, typically a semiconductor material such as Si, SiGe, or Ge. Although Fig. 9 Not shown, the channel layer 32 may provide an extension outside of the shown portion of the structure 1 to facilitate connection with peripheral semiconductor devices and circuits, such as select transistors.

[0084] If the gate layer 14 is a sacrificial gate layer, the method may be as follows Fig. 9 The sacrificial gate layer 14 is replaced with a replacement metal gate stack 34 as shown. The sacrificial gate layer 14 can be removed by etching back the sacrificial gate layer 14 from a second hole (not shown) in the layer stack 10 (e.g., the memory hole 4 is shown as a front hole or opening, and the second hole can be referred to as a back hole or opening). The lateral cavity thus formed at the level of the sacrificial gate layer 14 can then be filled with a replacement metal gate stack replacing the sacrificial gate layer 14. The replacement metal gate stack deposition itself is known in the art and includes depositing one or more conductive layers, such as a metal (such as one or more of TiN and W). A (conformal) high-k gate dielectric can be deposited before depositing the conductive layer.

[0085] Fig.10 A variation of the aforementioned process flow is shown, wherein a dielectric liner 23 is formed in the second recessed region 22 after etching back the gate layer 14 and before depositing the blocking oxide 24. The dielectric liner 23 may be a high-k dielectric (e.g., Al2O3 or HfO2), wherein the liner 23 may define the gate dielectric. In addition to this function, in the case of an RMG process, when the sacrificial gate layer 14 is removed during RMG, the dielectric liner 23 may be used as an etch stop layer, thereby masking the lateral memory stack 27 from the etching chemistry used when removing the sacrificial gate layer 14.

[0086] Similar to the blocking oxide 24, the dielectric liner 23 can be selectively deposited in the second recessed area 22, i.e., using a deposition process that allows the liner material of the dielectric liner 23 to be selectively deposited on the growth promoting or seeding surface portion in the second recessed area 22 (and not on the growth inhibiting area defined by the sacrificial layer 20). The deposition of the dielectric liner 23 can be preceded by one or more treatment processes for functionalization and / or inhibition of the gate layer 14 and the sacrificial layer 20, respectively, including the processes associated with the selective deposition of the blocking oxide 24 described above. The dielectric liner 23 can thus be deposited on the end surface 14a of the etched-back gate layer 14 (see Figure 4 ) or deposited on a deposition promoting layer 15 formed on the end surface.

[0087] Fig.11 The resulting lateral memory stack 27 is shown after depositing a blocking oxide 24 on the dielectric liner 23 followed by depositing a charge trapping material 26 .

[0088] Fig.12 A lateral memory stack 127 according to yet another variation is shown, wherein a (second) dielectric liner 25 (e.g. also a high-k dielectric) is selectively deposited on the blocking oxide 24 in the second recessed region 22 after depositing the blocking oxide 24 and before depositing the charge trap material 26. Then, the charge trap material 26 is selectively deposited on the dielectric liner 25. Thus, each lateral memory stack 127 comprises a lateral stack of blocking oxide 24, dielectric liner 25 and charge trap material 26.

[0089] Those skilled in the art will appreciate that the present invention is by no means limited to the above-described embodiments. On the contrary, many modifications and variations are possible within the scope of the appended claims.

Claims

1. A method for forming a memory structure (1) of a 3D NAND flash memory, the method comprising: forming a layer stack (10) on a substrate (2), the layer stack (10) comprising an alternating sequence of gate layers (14) and inter-gate spacer layers (12); forming a first recessed region (18) in a sidewall of the memory hole (4) surrounding the layer stack by laterally etching back the inter-gate spacer layer (12) from the memory hole (4); forming a sacrificial layer (20) in the first recessed region (18); By laterally etching back the gate layer (14) from the memory hole (4), a second recessed region (22) is formed on the side wall; forming a lateral memory stack (27) in each second recessed region (22) by selectively depositing a blocking oxide (24) and subsequently depositing a charge trap material (26) in the second recessed region (22), wherein the sacrificial layer (20) defines a deposition inhibition zone for selectively depositing the blocking oxide (24) and the charge trap material (26); removing the sacrificial layer (20) by etching from the memory hole (4); After removing the sacrificial layer (20), regrowing the inter-gate spacer layer (12) so that the lateral memory stack (27) is vertically separated by the regrown inter-gate spacer layer (12); After regrowing the inter-gate spacer layer (12), forming a tunnel oxide layer (30) in the memory hole (4); and A channel layer (32) is formed along the tunnel oxide layer (30).

2. The method of claim 1, wherein: Forming the sacrificial layer (20) includes conformally depositing a sacrificial material (201) to fill the first recessed area (18) and cover the sidewall of the memory hole (4), and etching back the sacrificial material (201) to expose the surface of the gate layer (14) at the sidewall.

3. The method of claim 1, wherein: Forming the sacrificial layer (20) includes selectively depositing a sacrificial material in the first recessed area (18) to fill the first recessed area (18).

4. A method as claimed in any one of the preceding claims, wherein: The blocking oxide (24) is laterally grown in the second recessed region (22) to a thickness of 4-12 nm.

5. A method as claimed in any one of the preceding claims, wherein: The charge trap material (26) is laterally grown in the second recessed region (22) to a thickness of 4-8 nm.

6. A method as claimed in any one of the preceding claims, wherein: The gate layer (14) is a nitride-containing layer, such as a SiN layer, or a polysilicon layer.

7. A method as claimed in any one of the preceding claims, wherein: The inter-gate spacer layer (12) is an oxide-containing layer, such as a SiO2 layer.

8. A method as claimed in any one of the preceding claims, wherein: The sacrificial layer (20) is a metal oxide layer, such as an Al2O3 layer or a TiO2 layer; a metal nitride layer, such as an AlN layer or a TiN layer; a metal layer, such as a Co layer, a Ru layer, a Cu layer, a W layer or a Mo layer; or a carbon-containing layer, such as an amorphous carbon layer or an organic spin-coated layer.

9. The method of any one of the preceding claims, further comprising functionalizing a surface portion (14a) of the etched-back gate layer (14) in the second recessed region (22) before depositing the blocking oxide (24), and subsequently depositing the blocking oxide (24) on the functionalized surface portion (14a).

10. The method of claim 9, wherein: The functionalization step comprises depositing a deposition promoting layer (15) on a surface portion (14a) of the etched-back gate layer (14) in the second recessed region (22).

11. The method of any of the preceding claims, further comprising, prior to depositing the blocking oxide, performing a treatment process suitable for passivating exposed surface portions of the sacrificial layer (20) relative to the selective deposition of the blocking oxide (24) and the charge trapping material (26).

12. The method according to any of the preceding claims, further comprising selectively depositing a dielectric liner (23) on the gate layer (14) in the second recessed region (22), and subsequently selectively depositing a blocking oxide (24) on the dielectric liner (23).

13. A method as claimed in any one of the preceding claims, wherein: The gate layer (14) is a sacrificial gate layer, and the method further includes replacing the sacrificial gate layer (14) with a replacement metal gate stack (34) after depositing the blocking oxide and the charge trapping material.

14. The method of claim 13 when dependent on claim 12, further comprising using the dielectric liner (23) as an etch stop layer when removing the sacrificial gate layer (14) to be replaced by the replacement metal gate stack (34).

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