1.5 T SONOS device and preparation method thereof

Abstract

The invention discloses a 1.5 T SONOS (Silicon Oxide Nitride Oxide Semiconductor) device and a preparation method thereof. Under the condition that the thickness of the ONO layer and the transverse length of the storage tube grid electrode are not increased, the slope is formed on the surface of the substrate, the ONO layer is deposited, the control capacity of the storage grid electrode on a channel is improved, the length of the ONO layer is increased, the total number of defects in the ONO layer is increased, the effect of improving the charge storage capacity of a device is achieved, and the working performance of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, in particular to a 1.5T SONOS device and a preparation method thereof. Background Art

[0002] Flash memory is an essential storage device in computers. It plays an important storage function for the processed information and is widely used in various embedded electronic products such as financial IC cards and automotive electronics. However, since flash memory with a floating gate structure requires high voltage operation during reading, writing and erasing, while complementary metal oxide semiconductor (CMOS) does not require high voltage operation, and flash memory is a double-layer polysilicon structure with a floating gate and a control gate, while CMOS is a single-layer polysilicon structure, the integration of flash memory and CMOS devices is difficult and the process is complex. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) technology is well compatible with CMOS technology. It only needs to embed SONOS memory on the basis of the logic platform. In addition, SONOS memory has a low operating voltage, good storage retention, and low cost, making it extremely competitive in terms of manufacturing, use and cost.

[0003] Traditional SONOS devices use silicon oxide-silicon nitride-silicon oxide (ONO) instead of a floating gate, in which the silicon nitride layer is a capture layer. The traps in the capture layer serve as the location for storing charges, so the size of the silicon nitride layer determines the amount of stored charge. The silicon oxide at the bottom is a tunneling oxide layer, and the silicon oxide at the top is a blocking layer.

[0004] The traditional 1.5T (transistor) SONOS storage unit includes a selection tube and a storage tube, see Figure 1 The selector is mainly used to turn on and off the storage tube to reduce leakage. The storage tube is mainly used to store charge and realize data storage through different Vt states. The two transistors are arranged closely, which can significantly reduce the storage unit area compared with the 2T SONOS structure. Figure 1 b in.

[0005] In 1.5T SONOS devices, the lateral length of the ONO layer is limited by the lateral length of the polysilicon gate of the storage tube. With the further development of electronic products, people hope that the storage devices of electronic products will be smaller in size and higher in performance. The lateral length of the polysilicon gate is constantly decreasing, so the lateral length of the ONO layer is also constantly decreasing, which not only leads to a smaller contact area between the storage gate and the ONO layer above the channel, thereby reducing the control ability of the storage gate over the channel, but also reduces the charge storage capacity of the silicon nitride layer. If the storage capacity of silicon nitride needs to be maintained, its thickness must be increased, but this increase in thickness will make the device appear tall and thin, and the deposition and etching in the process steps will become more and more difficult, and the yield rate will become lower and lower. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention provides a 1.5T SONOS device and a preparation method thereof.

[0007] One aspect of the present invention provides a method for preparing a 1.5T SONOS device, comprising:

[0008] Step 1: On the semiconductor substrate, doping is first performed to form a PWell, and then self-oxidation is performed to form a silicon dioxide oxide layer;

[0009] Step 2: deposit a layer of polysilicon on the grown silicon dioxide oxide layer, and then perform ion doping and implantation of As into the polysilicon;

[0010] Step 3: Make a patterned mask, apply a layer of photoresist on the silicon wafer, and transfer the pattern on the mask to the photoresist layer through photolithography technology;

[0011] After that, the photoresist in the exposed area is removed by developing, so that the surface of the silicon wafer is exposed to the area to be etched; the excess polysilicon is removed and a groove with slopes on both sides is generated;

[0012] Step 4: Generate an ONO layer on the surface;

[0013] Step 5: Perform light doping injection on both sides of the storage tube gate and the selection tube gate, and then perform heavy ion doping;

[0014] Step 6: Generate a silicon dioxide oxide layer by oxidizing silicon itself;

[0015] Step 7: After the oxide layer growth in step 6 is completed, a layer of polysilicon is deposited on the entire surface of the silicon wafer;

[0016] Step 8: Make a patterned mask, then perform photolithography to remove excess polysilicon, and dope the polysilicon after the photolithography is completed;

[0017] Step 9: deposit a layer of silicon nitride film on the surface, and then perform photolithography to remove excess silicon nitride to form a sidewall;

[0018] Step 10: deposit NiSi to form a metal electrode and deposit high-density silicon dioxide;

[0019] Step 11: Use a patterned mask to etch high-density silicon dioxide to open a through hole; deposit a layer of TiN on the surface of the through hole, and then deposit metal tungsten in the through hole to form a metal interconnection through hole.

[0020] Another aspect of the present invention provides a 1.5T SONOS device prepared by the above method.

[0021] Beneficial effects of the present invention: The storage medium of the device of the present invention is a sloped ONO layer, which increases the contact area between the storage gate and the storage medium, can effectively increase the control ability of the storage gate over the channel, and can extend the length of the ONO layer, so that the device has better charge storage capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a traditional SONOS storage unit;

[0023] Figure 2 Schematic diagram of the 1.5T SONOS device structure provided for this application;

[0024] Figure 3 Schematic diagram of the process of forming a PWell in step 1 of this embodiment;

[0025] Figure 4 This is a schematic diagram of the oxide layer formation process in step 1 of this embodiment;

[0026] Figure 5 This is a process schematic diagram of step 2 of this embodiment;

[0027] Figure 6 This is a process schematic diagram of step 3 of this embodiment;

[0028] Figure 7 This is a process schematic diagram of step 4 of this embodiment;

[0029] Figure 8 This is a schematic diagram of the process of removing the redundant ONO layer in step 5 of this embodiment;

[0030] Fig. 9 This is a schematic diagram of the doping process in step 5 of this embodiment;

[0031] Fig.10 This is a process schematic diagram of step 6 of this embodiment;

[0032] Fig.11This is a schematic diagram of the process of depositing a layer of polysilicon in step 7 of this embodiment;

[0033] Fig.12 Schematic diagram of the CMP polishing process using silicon dioxide as a barrier layer in step 7 of this embodiment;

[0034] Fig.13 This is a process schematic diagram of step 8 of this embodiment;

[0035] Fig.14 This is a process schematic diagram of step 9 of this embodiment;

[0036] Fig.15 Schematic diagram of the metal electrode forming process in step 10 of this embodiment;

[0037] Fig.16 This is a schematic diagram of the high-density silicon dioxide deposition process in step 10 of this embodiment;

[0038] Fig.17 This is a process schematic diagram of step 11 of this embodiment; DETAILED DESCRIPTION

[0039] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0040] Step 1: In Figure 3 The semiconductor substrate shown in the figure is first doped to form a PWell, and then oxidized to form a silicon dioxide oxide layer with a thickness of about like Figure 4 shown.

[0041] Step 2: If Figure 5 , a layer of polysilicon is deposited on the grown silicon dioxide oxide layer. The thickness of the polysilicon is about Then, ion doping is performed on the polysilicon at a concentration of 10 15 cm -2 As.

[0042] Step 3: Make a patterned mask (photomask) according to the design requirements, apply a layer of photoresist on the silicon wafer, and transfer the pattern on the mask to the photoresist layer through photolithography technology. Then perform development to remove the photoresist in the exposed area, exposing the area to be etched on the silicon wafer surface. Use etching methods to remove excess polysilicon and generate Figure 6 The groove shown has sloped sides and a depth of approximately After etching is completed, the remaining photoresist is removed and a cleaning process is performed.

[0043] Step 4: Generate an ONO layer (silicon oxide-silicon nitride-silicon oxide) on the surface. Use thermal oxidation or chemical vapor deposition (CVD) technology to grow a layer of silicon oxide on the surface of the silicon wafer with a thickness of about On top of the silicon oxide layer, a layer of silicon nitride is deposited by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) technology with a thickness of about Silicon nitride can provide good electrical isolation and physical protection. Finally, a layer of silicon oxide is deposited on top of the silicon nitride layer with a thickness of about A deposition method similar to that of the first silicon oxide layer can be used to make this silicon oxide layer closely bonded to the silicon nitride layer below to form a complete ONO layer, such as Figure 7 .

[0044] Step 5: Etch to remove the excess ONO layer, such as Figure 8 Then, light doping is first performed on both sides of the storage tube gate and the selection tube gate, and heavy ions are injected. The shallow junction is formed with an energy of 10 keV and an implantation dose of 10 14 cm -2 The lightly doped implant can suppress the drain-induced barrier lowering effect ( induced Then, heavy ion doping is performed, and As is injected at a dose of 10 15 cm -2 order of magnitude, forming source and drain. Fig. 9 shown.

[0045] Step 6: Fig.10 As shown in Figure 2, after the source and drain electrodes are formed, silicon itself is oxidized to form a silicon dioxide oxide layer with a thickness of approximately

[0046] Step 7: Fig.11 As shown in FIG. 1 , after the oxide layer is grown, a layer of polysilicon is deposited on the entire surface of the silicon wafer. After the polysilicon deposition is completed, CMP polishing is performed using silicon dioxide as a barrier layer, as shown in FIG. Fig.12 shown.

[0047] Step 8: Make a patterned mask, then perform photolithography to remove excess polysilicon, such as Fig.13 As shown, after the photolithography is completed, the polysilicon is doped with an injection concentration of 10 15 cm -2 As.

[0048] Step 9: Deposit a layer of silicon nitride film on the surface, and then perform photolithography to remove excess silicon nitride to form a side wall, such as Fig.14 shown.

[0049] Step 10: Deposit NiSi to form a metal electrode, such as Fig.15 Deposition High density silica (HDPOX), such as Fig.16 shown.

[0050] Step 11: Use a patterned mask to etch the HDP OX, open the through hole, first deposit a layer of TiN on the surface of the through hole, and then deposit metal tungsten in the through hole to form a metal interconnect through hole. Fig.17 shown.

[0051] The preparation method of the present invention forms a slope on the surface of the substrate and deposits the ONO layer without increasing the thickness of the ONO layer and the lateral length of the storage tube gate, thereby increasing the control ability of the storage gate over the channel and increasing the length of the ONO layer, thereby increasing the total number of defects in the ONO layer, achieving the effect of improving the charge storage capacity of the device and improving the working performance of the device.

[0052] The present invention also provides a 1.5T SONOS memory device prepared according to the above method, such as Figure 2 As shown in Figure 1, the device uses a channel hot carrier injection mechanism when writing. A high voltage is applied to the CG and source, so that electrons are accelerated from the source side by a horizontal high electric field, and then injected into the ONO layer under the action of a vertical electric field. This mechanism will generate a higher current, but requires a smaller voltage.

[0053] When erasing, the BTBT (Band-to-band tunneling hot-hole injection) mechanism is used. A positive high voltage is applied to the source end and a negative high voltage is applied to the storage gate to complete the erase operation. BTBT injection has a lower operating voltage and a faster erase speed than FN tunneling. When reading, V is applied to the select gate, storage gate, and drain respectively. DD The operating voltage is shown in the table below.

[0054] Operation Vd Vs Vx Vc Erase 0 3V 0 -7V Program 0 3V 0 7V Read 1.2V 0 1.2V 1.2V

[0055] The above are preferred embodiments of the present invention. It should be noted that a person skilled in the art may make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications are also considered to be within the protection scope of the present invention.

Claims

1. A method for preparing a 1.5T SONOS device, characterized in that: The method comprises the following steps: Step 1: On the semiconductor substrate, doping is first performed to form a PWell, and then self-oxidation is performed to form a silicon dioxide oxide layer; Step 2: deposit a layer of polysilicon on the grown silicon dioxide oxide layer, and then perform ion doping and implantation of As into the polysilicon; Step 3: Make a patterned mask, apply a layer of photoresist on the silicon wafer, and transfer the pattern on the mask to the photoresist layer through photolithography technology; After that, the photoresist in the exposed area is removed by developing, so that the surface of the silicon wafer is exposed to the area to be etched; the excess polysilicon is removed and a groove with slopes on both sides is generated; Step 4: Generate an ONO layer on the surface; Step 5: Perform light doping injection on both sides of the storage tube gate and the selection tube gate, and then perform heavy ion doping; Step 6: Generate a silicon dioxide oxide layer by oxidizing silicon itself; Step 7: After the oxide layer growth in step 6 is completed, a layer of polysilicon is deposited on the entire surface of the silicon wafer; Step 8: Make a patterned mask, then perform photolithography to remove excess polysilicon, and dope the polysilicon after the photolithography is completed; Step 9: deposit a layer of silicon nitride film on the surface, and then perform photolithography to remove excess silicon nitride to form a sidewall; Step 10: deposit NiSi to form a metal electrode and deposit high-density silicon dioxide; Step 11: Use a patterned mask to etch high-density silicon dioxide to open a through hole; deposit a layer of TiN on the surface of the through hole, and then deposit metal tungsten in the through hole to form a metal interconnection through hole.

2. The method for preparing a 1.5T SONOS device according to claim 1, characterized in that: The thickness of the oxide layer in step 1 is 90Å.

3. The method for preparing a 1.5T SONOS device according to claim 1, characterized in that: In step 2, the thickness of polysilicon is 650Å and the As implantation concentration is 10 15 cm -2 .

4. The method for preparing a 1.5T SONOS device according to claim 1, characterized in that: The groove depth described in step 3 is 300Å.

5. The method for preparing a 1.5T SONOS device according to claim 1, characterized in that: The energy of the light doping injection in step 5 is on the order of 10 keV, and the injection dose is 10 14 cm -2 The heavy doping injection dose is 10 15 cm -2 The injected ions are all of Ås in size to form the source and drain.

6. The method for preparing a 1.5T SONOS device according to claim 1, characterized in that: Step 7: After the polysilicon deposition is completed, CMP polishing is performed using silicon dioxide as a barrier layer.

7. The method for preparing a 1.5T SONOS device according to claim 1, characterized in that: In step 8, the polysilicon is doped with an injection concentration of 10 15 cm -2 As.

8. The method for preparing a 1.5T SONOS device according to claim 1, characterized in that: In step 10, 1400Å of high density silica is deposited.

9. A 1.5T SONOS device, obtained by the preparation method according to any one of claims 1 to 8.

10. The 1.5T SONOS device according to claim 9, characterized in that: The device uses the channel hot carrier injection mechanism when writing data and the BTBT mechanism when erasing data.

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