A novel three-dimensional in-memory computing chip array structure and its fabrication method

Abstract

The present invention belongs to but is not limited to the field of computing power chips, and in particular relates to a novel three-dimensional storage and computing integrated chip array structure and a preparation method thereof, which has a storage unit layer, which includes multiple storage units for data storage; a storage array based on a NOR architecture can access any unit to perform computing tasks; by using storage units for computing tasks to achieve storage and computing integration, the energy consumption caused by data transmission is reduced, and by optimizing the design of interconnection channels, the signal transmission delay is reduced, thereby improving the overall performance; a control module is used to accurately control each NOR type storage unit, and by optimizing the design of interconnection channels, the signal transmission delay is reduced; the performance is further improved through a three-dimensional integrated architecture, and more units are integrated in the three-dimensional structure, thereby achieving higher integration and shorter signal transmission paths, effectively solving the problem of insufficient capacity.

Description

Technical Field

[0001] The present invention belongs to but is not limited to the field of computing power chips, and in particular relates to a novel three-dimensional storage and computing integrated chip array structure and a preparation method thereof. Background Art

[0002] In traditional computer architecture, the separation of data processing units and data storage units leads to two major bottlenecks: memory wall and IO wall. The memory wall refers to the data transmission delay between the processor and the memory, which limits the improvement of system performance. Although the processor speed has increased rapidly, the improvement of memory performance has lagged behind, thus forming a bottleneck in data processing speed. The IO wall stems from the difference in data transmission rate between external storage devices and processors, which significantly reduces efficiency when processing large-scale data. In order to solve these traditional bottleneck problems, storage-computing integrated technology came into being. This technology integrates data storage and computing functions in the same chip, and significantly improves system performance by reducing the transmission of data between storage and computing units. Storage-computing integrated technology can not only reduce power consumption, but also increase data processing speed. It is one of the important development directions in the post-Moore era. However, the traditional planar storage-computing integrated chip design is limited by the effective chip area, and it is difficult to significantly increase chip capacity. To break through this limitation, 3D storage-computing integrated chip technology came into being. Based on the storage and computing integrated technology, the 3D storage and computing integrated chip further improves the performance through a three-dimensional integrated architecture. This chip integrates more units in a three-dimensional structure, thereby achieving higher integration and shorter signal transmission paths, effectively solving the problem of insufficient capacity.

[0003] In view of the above analysis, the technical problems that need to be solved urgently in the prior art are: 1: The contradiction between storage density and computing power: The 2D planar layout limits the integration density and it is difficult to meet the growing demand.

[0004] 2: Data transmission delay: Even in storage-computing integrated technology, data transmission delay during large-scale data processing cannot be ignored.

[0005] 3: Power consumption problem: The expansion of chip scale leads to increased power consumption, which becomes a performance bottleneck, especially in high-performance computing scenarios.

[0006] 4: Complexity of manufacturing process: As the requirements for integration continue to increase, more units need to be integrated in a smaller range. The existing manufacturing process is difficult to meet the demand, limiting the widespread application of technology. Summary of the invention

[0007] In view of the many problems exposed by existing technologies, the present invention has carefully constructed a new three-dimensional storage-computing integrated chip architecture based on NOR array. This architecture achieves the integration of high-density storage and high-performance computing functions. Its core goal is to resolve the challenges encountered by current storage-computing integrated chips and effectively promote the development of semiconductor technology.

[0008] Specifically, the present invention has the following features: it covers one or more layers of storage units, each layer contains a large number of storage units for data storage; and each storage unit can act as a computing unit under the drive of the peripheral circuit, and can access any unit in the array by precise control of voltage, thereby performing computing tasks. By optimizing the design of the interconnection channel, the delay of signal transmission is significantly reduced, thereby achieving a significant improvement in overall performance.

[0009] Furthermore, the present invention also includes a control module for accurately controlling each NOR type unit to further improve the system efficiency. Through the precise regulation of voltage, the storage unit can be used to perform computing tasks, combining the computing unit with the storage unit. At the same time, a data transmission bus and a signal control bus are also provided, which are used for data transmission between layers and transmission of control signals respectively.

[0010] Furthermore, the storage unit of the present invention adopts a charge trapping device, and its ideal charge trapping layer medium has a high trap density and can capture enough charges in an extremely thin storage layer. High trap density materials are crucial for feature size reduction technology. In addition, deep trap energy levels help reduce the probability of electrons escaping from traps through tunneling layers and barrier layers. This medium is widely used in various types of memory chip technologies, such as SRAM, DRAM, Flash Memory, PCM and MRAM. The comprehensive application of these technologies enables the chip array of the present invention to achieve an excellent balance in terms of storage capacity, read and write speed and power consumption.

[0011] Furthermore, the storage unit layer is used for calculation using any one or more of the following computing technologies: (1) a computing unit based on an adder; (2) a computing unit based on a multiplier; (3) a computing unit based on a logic gate; (4) a computing unit based on a neural network.

[0012] Furthermore, the control module includes: a data read and write controller for managing data read and write operations, wherein the read voltage of NOR flash memory is generally low, between 2.5V and 3.6V, while the write operation (programming) voltage is higher, between 12V and 21V; a computing task scheduler for arranging computing tasks at the computing unit layer; and a power consumption management unit for monitoring and managing the power consumption of the chip array.

[0013] Furthermore, the chip array also includes: a cache module for temporarily storing recently or frequently accessed data to speed up re-access, reduce access latency, and reduce the number of I / O operations. The cache module can handle a large number of read and write requests and reduce direct access to underlying storage devices (such as hard disks, SSDs).

[0014] Furthermore, the chip array needs to adopt the following multiple manufacturing processes: photolithography, etching, epitaxial growth, ion implantation, chemical vapor deposition and physical vapor deposition. In addition, it is also necessary to integrate the peripheral circuit module, NO stacking module, step module and channel hole module in the 3D semiconductor process.

[0015] The present invention also provides a data processing method of a 3D storage-computing integrated chip array based on a NOR array, comprising the following steps: S1: Store input data in the storage unit layer.

[0016] S2: Access the specified unit in the array by regulating the peripheral circuit.

[0017] S3: Calculate the memory cells that need to perform tasks using adders, multipliers, logic gates, or neural networks.

[0018] S4: Return the calculation results to the cell array through the interconnection channel for storage or further output.

[0019] S5: The control module schedules the storage unit layer to perform calculation operations, optimizes data flow transmission efficiency, and reduces signal transmission delay.

[0020] Further, the following steps are included: S1: Using a charge trapping memory device to store data, the charge trapping layer has a high trap density and a deep trap energy level to improve the reliability of data storage.

[0021] S2: Use the cache module to temporarily store frequently accessed data to reduce direct access to the storage unit layer.

[0022] S3: The read operation of the storage unit uses a low voltage (2.5V to 3.6V), and the write operation uses a high voltage (12V to 21V). The data read and write management is completed by the data read and write controller.

[0023] Further, the following steps are included: S1: The control module monitors the power consumption of the chip array in real time and calculates the energy consumption distribution of each unit and storage unit layer that needs to perform computing tasks.

[0024] S2: Dynamically adjust the computing task scheduler to optimize the workload distribution at the computing unit layer according to the energy consumption distribution.

[0025] S3: Use the power management unit to put idle computing units or storage units into sleep mode, thereby reducing overall power consumption.

[0026] S4: Switches between high-performance and low-power modes, dynamically allocating resources based on task requirements.

[0027] In combination with the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solutions to be protected by the present invention are as follows: First, the 3D storage-computing integrated chip array provided by the present invention is based on the NOR structure and adopts a new three-dimensional arrangement method to arrange multiple vertical storage groups on the horizontal plane. All storage transistors share a vertically extended columnar gate structure, which significantly improves the integration density of the storage array. Alternatively, a storage group is arranged in the vertical direction, and these storage groups share a bit line and source selection line, which greatly improves the storage density.

[0028] The present invention achieves more efficient data transmission and access by connecting word lines and bit lines of different vertical storage groups in the same row, further improving the use efficiency. It has the advantages of simple preparation process, fast erasing speed, wide threshold range and excellent retention characteristics, which is crucial to the stability and capacity of the memory chip, so it is of great significance to study this technology. The uniqueness of the present invention lies in the structural design of the cell array, including source selection lines, floating gate units, word lines and top bit lines.

[0029] The present invention adopts a multi-layer stack of oxide and nitride, realizes a metal / oxide / nitride structure through a linear "W / L cutting" etching technology and a unique gate replacement process.

[0030] The present invention designs an innovative integrated storage and computing architecture, which is not only fully compatible with the existing NOR Flash technology, ensuring seamless integration with existing devices and systems, but also has excellent scalability. In addition, the present invention complies with the electrical characteristic standards of NOR Flash, such as voltage range, timing parameters, etc., ensuring stable operation under different power supply conditions and clock frequencies.

[0031] The present invention utilizes the characteristic that the storage unit can perform computing tasks, and stores data in the NOR type unit through a high-speed cache mechanism. The characteristic of the NOR type structure based on it enables direct access to the data for processing, reducing the delay and energy consumption caused by data movement. This modular and integrated design concept makes each storage unit an independent module, which can be independently upgraded or replaced without affecting the operation of the entire system. It fully considers the development trend of future technology, reserves upgrade interfaces and expansion slots, and facilitates the integration of more advanced storage technology and computing architecture in the future.

[0032] Second, the present invention integrates storage and computing units into a three-dimensional array architecture, greatly reducing the data transmission delay between storage and processors. This architecture successfully overcomes the "storage wall" problem of low data transfer efficiency in the traditional von Neumann architecture, thereby achieving efficient data processing and computing performance. In addition, the present invention is based on storage and computing integration, and with the help of precise voltage control and intelligent power consumption management, it significantly reduces overall energy consumption.

[0033] As artificial intelligence and big data technologies are widely used, the demand for high-efficiency computing hardware is exploding, and the market size is expected to increase from 300 million yuan in 2022 to 113.6 billion yuan in 2030. The three-dimensional storage and computing integrated chip architecture of the present invention has extremely broad market application prospects, especially in the fields of smart wearable devices, mobile terminals, smart driving and data centers.

[0034] The current storage and computing technology is still dominated by two-dimensional arrays. Faced with the rapid growth of storage capacity and computing speed requirements, the expansion of two-dimensional arrays can no longer meet application needs. The present invention significantly improves storage density and computing efficiency through innovative three-dimensional array technology and an architecture based on NOR memory. At the same time, NOR Flash memory has the characteristics of mature technology, high reliability and high integration, which significantly enhances the technical feasibility and stability of the three-dimensional storage and computing architecture.

[0035] Traditional AI architecture chips are constrained by technical bottlenecks such as "storage wall" and "power wall", making it difficult for the chip to effectively reduce power consumption during high-performance computing. The present invention greatly reduces the frequency of data transfer by performing computing tasks within the storage unit, thereby improving the computing efficiency of the chip and reducing power consumption. At the same time, NOR Flash-based storage units have the advantages of low cost, mature technology, and strong mass production capabilities, avoiding high manufacturing costs. In addition, the non-volatile nature of Flash storage enables it to directly store network weights without the need for external memory, further reducing chip costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is an equivalent circuit diagram of a NOR type memory cell array provided by an embodiment of the present invention.

[0037] Figure 2 The present invention provides a circuit diagram for performing sum-product operations using a NOR type storage unit.

[0038] Figure 3 It is a bird's-eye view of a row of arrays provided by an embodiment of the present invention.

[0039] Figure 4 It is a bird's-eye view of an array provided by an embodiment of the present invention.

[0040] Figure 5 is a circuit equivalent diagram of a row array provided by an embodiment of the present invention.

[0041] Figure 6 It is a circuit equivalent diagram of a column array provided by an embodiment of the present invention.

[0042] Figure 7 It is a schematic diagram of power consumption reduction implemented by the present invention.

[0043] Figure 8 It is the expected effect diagram of the implementation of the present invention. DETAILED DESCRIPTION

[0044] In order to more clearly illustrate the purpose, technical solution and advantages of the present invention, the present invention is described in detail below in conjunction with specific embodiments. It should be understood that the embodiments described herein are only used to explain the present invention and do not constitute a limitation on the scope of the present invention.

[0045] The novel three-dimensional storage and computing integrated chip architecture of the present invention adopts a storage unit layer based on a NOR array. By optimizing the design of the storage unit, it can not only store data, but also work as a computing unit when needed. Each storage unit is supported by a charge capture device, and can perform logical operations and simple arithmetic operations while maintaining high-density storage. The fusion design of storage and computing units effectively solves the problem of frequent data transmission between storage units and computing units, thereby significantly improving computing efficiency and reducing system power consumption.

[0046] As a key core component of the chip, the control module is responsible for coordinating the operation of the storage unit and the computing unit. This module uses an optimized circuit design to achieve precise control of the voltage of each storage unit. According to the requirements of the task, the control module can dynamically distribute the voltage, prompting some storage units to convert to computing mode and perform specific computing tasks. The optimized signal path design effectively reduces the delay of the voltage signal during the transmission process, effectively ensuring the efficient operation of the overall system.

[0047] The chip array adopts a three-dimensional stacking structure. Each storage unit layer is connected to the upper and lower layers through a data transmission bus and a signal control bus, realizing efficient data interaction between multiple layers. Among them, the signal control bus is used to transmit operation instructions, while the data transmission bus is responsible for transmitting storage data between different layers. Inter-layer communication reduces the delay of signal transmission through the optimized interconnection channel design, ensuring that efficient data processing capabilities are maintained in complex computing task scenarios.

[0048] The storage unit uses a charge trapping device, in which the charge trapping layer has a high trap density and deep trap energy level. This design enhances the data retention performance of the storage unit and also reduces the probability of electron escape. Compared with traditional storage technology, this technology has shown extraordinary performance in storage density, write speed and data stability, especially in line with the chip manufacturing process with continuously reduced feature size. Moreover, this technology plays a key role in the low-power design of the chip.

[0049] The computing unit layer of the present invention supports a variety of computing technologies, including computing units based on adders, multipliers, logic gates, and neural networks. The control module allocates appropriate computing units according to specific tasks to achieve parallel processing of multiple tasks. For applications related to neural networks, the computing units can efficiently perform matrix operations and activation function calculations, thereby providing hardware support for deep learning tasks.

[0050] The power management unit optimizes the power consumption distribution of the entire chip array by monitoring the working status of the storage and computing units in real time. The unit can dynamically adjust the voltage of inactive units to put them in low power consumption mode, while ensuring that the computing units of high priority tasks maintain optimal performance. By introducing such a refined power management mechanism, the present invention greatly reduces the overall energy consumption and prolongs the operating time of the chip in high-performance working mode.

[0051] Application Example 1: High-Performance Edge Computing Device Edge computing devices need to perform real-time data processing and computing at a location close to the data source, such as industrial Internet of Things, smart manufacturing, and autonomous driving. Such applications not only require high-density storage and real-time computing capabilities, but also have extremely strict limitations in terms of power consumption and space.

[0052] The three-dimensional storage and computing integrated chip architecture involved in the present invention can significantly improve the performance of edge computing devices by integrating storage and computing functions into the same array. This device can store massive amounts of sensor data through the high-density storage layer of the chip, and process the data in real time through the computing unit layer, such as implementing signal filtering, edge detection, or machine learning inference. The three-dimensional stacked structure reduces the transmission delay between the stored data and the computing unit. At the same time, the power management unit also optimizes the energy consumption of the edge device, allowing it to run stably for a long time. This application provides a solid and reliable hardware solution for edge computing modules in industrial Internet of Things nodes and driverless cars.

[0053] Application Example 2: Neural Network Accelerator Deep learning tasks require efficient matrix operations and activation function calculations, which places extremely high demands on the parallel processing capabilities and storage bandwidth of hardware. In traditional computing architectures, the bottleneck of data transmission limits the efficiency of deep learning tasks.

[0054] The three-dimensional storage and computing integrated chip of the present invention can support the computing unit layer based on the neural network, so it can directly achieve matrix operations and weight updates in the storage unit, thereby accelerating the reasoning and training process of deep learning. For example, in the image classification task, the storage unit is responsible for storing the weight parameters, while the computing unit performs convolution and activation function operations. The chip's efficient data transmission bus and intelligent power consumption management unit further improve the efficiency of task execution while reducing energy consumption. This architecture is extremely suitable for deployment in AI acceleration cards in data centers, and can also be used in neural network acceleration chips in mobile devices, which can significantly enhance AI computing capabilities and extend battery life.

[0055] The present invention proposes a 3D storage-computing integrated chip array based on the NOR structure, which uses an innovative three-dimensional arrangement method to arrange multiple vertical storage groups on a horizontal plane. All storage transistors share a vertically extended columnar gate structure, which significantly improves the integration density of the storage array.

[0056] The present invention greatly improves the storage density by arranging a group of storage cells in the vertical direction and sharing a bit line and source selection line. The present invention realizes efficient data transmission and access by connecting the word lines and bit lines of different vertical storage cells in the same row, further improving the utilization efficiency. The present invention has the advantages of simple preparation process, fast erasing speed, wide threshold range and excellent retention characteristics, which is crucial to improving the stability and capacity of the memory chip. Therefore, it is of great significance to study this technology. Its uniqueness lies in the structural design of the cell array, including the source selection line, floating gate unit, word line and top bit line.

[0057] The present invention adopts a multi-layer stacking form of oxide and nitride, and achieves a metal / oxide / nitride structure by means of a linear "W / L cutting" etching technology and a unique gate replacement process.

[0058] The present invention has carefully planned a highly innovative integrated storage and computing architecture, which is not only fully compatible with existing NOR Flash technology, effectively ensuring seamless integration with existing devices and systems, but also has excellent scalability. In addition, the present invention strictly follows the electrical characteristic standards of NOR Flash (such as voltage range, timing parameters, etc.), effectively ensuring stable operation under various power supply conditions and clock frequencies.

[0059] Furthermore, the storage unit in the present invention can perform computing tasks, store data in the NOR storage unit through the cache mechanism, and then access and perform computing tasks for any unit in conjunction with the peripheral circuit, effectively reducing the delay and energy consumption caused by data movement. This modular design concept makes each storage unit and computing unit an independent module, which can be easily upgraded or replaced without affecting the operation of the entire system. At the same time, the development trend of future technologies is fully considered, and upgrade interfaces and expansion slots are reserved to facilitate the integration of more advanced storage technologies and computing architectures in the future.

[0060] The present invention aims to propose a novel 3D storage-computing integrated chip array structure and a preparation method thereof, specifically: arranging multiple storage units in a row or a column in the XY plane, sharing a source line and a bit line according to the characteristics of the NOR type storage array structure (i.e., a parallel structure), integrating more storage units in the Z direction, and focusing on the research of novel storage array technology, including device design and preparation, mechanism research, performance characterization, etc.

[0061] like Figure 1 The core principle of the NOR Flash disclosed by the embodiment of the present invention is shown. In this structure, each NOR storage cell is connected to the bit line in parallel, so that each cell can be randomly accessed. Thanks to the dedicated address line configuration, this structure can achieve one-time direct addressing, significantly reducing the response delay of Flash to processor instructions.

[0062] like Figure 2 As shown in the figure, two NOR-type Flash memories are used to perform sum-product operations. This example demonstrates the basic principle of NOR-type Flash memories being used for storage and computing.

[0063] Substrate preparation: Select suitable materials, such as silicon wafers, as the substrate. Then clean and pre-treat the substrate, use decon cleaning agent for ultrasonic cleaning, further clean it with anhydrous ethanol, and blow dry it with a nitrogen gun. Finally, put the substrate into a blast drying oven and dry it at 120°C for 30 minutes to remove surface impurities and oxide layers to ensure that the substrate has good electrical properties.

[0064] Depositing the bottom layer material: Epitaxial deposition is a process of uniformly coating a substrate with a layer of silicon dioxide. During epitaxial deposition, reactive gases are passed through the surface of a high-temperature wafer, and the high temperature drives the gases to react on the surface of the wafer. The deposited atoms generated in the gas reaction move on the surface of the wafer and form bonds with the atoms on the surface of the wafer in the same crystal orientation at certain locations.

[0065] Photolithography isolation layer: First, the designed isolation layer pattern needs to be made on the mask, and then the pattern on the mask is mapped on the surface of the wafer coated with a photosensitive film using ultraviolet light, so that the photosensitive film is cured and imaged. In the present invention, the storage units are stacked vertically. The demand for photolithography technology has shifted from size miniaturization to more complex and diverse pattern formation.

[0066] Constructing a vertical channel: Advanced etching techniques such as deep reactive ion etching (DRIE) are used to create vertical nanoholes with high aspect ratios. This process can provide excellent feature size and etching profile sidewall control, reducing photoresist peeling and adhesion. Subsequently, conductive materials such as tungsten or polysilicon are filled to form charge storage nodes. Figure 3 and Figure 4 As shown, the cylinder is the channel hole structure. Numerous channel holes form a storage array. The array string includes an upper selection tube and a lower selection tube, and there are multiple storage units between the upper and lower selection tubes. In actual products, silicon nitride is filled between the gates, around the channels, and around the contact plugs, thereby achieving the role of an isolation layer. During the preparation process, the hard mask must first be etched. The hard mask is usually composed of materials such as an amorphous carbon layer and an anti-reflective coating. After successfully removing the hard mask, the ON stack can be continuously etched through in the same etching operation to achieve the preparation of deep channel holes. The characteristic dimensions of these channel holes usually require a depth of more than 4μm and an aspect ratio greater than 40:1. Finally, it is etched onto a single crystal silicon substrate. In the channel hole etching process, it is necessary to keep the upper and lower characteristic dimensions of the deep hole as consistent as possible, and the roundness of the channel hole is good, thereby forming a good device structure and laying a good foundation. In the process of etching the channel holes, in order to ensure the effective connection between the array string and the source end, the etching depth must be precisely controlled until the predetermined position on the surface of the silicon substrate is reached and the etching is stopped. If the etching is excessive, the array string will not be able to establish a connection with the source end, which will lead to the problem of reduced yield. When etching many holes at the same time, it is also necessary to ensure that the deep hole stops at the appropriate position and the uniformity of the channel hole depth is good. This is a huge challenge for the deep channel hole etching process.

[0067] Fabrication of charge trapping layer: Tunnel oxide, charge trap silicon nitride, polysilicon, etc. are deposited in the channel hole in sequence to complete the manufacture of the charge trap layer. CVD technology is used to uniformly deposit a layer of high-quality silicon dioxide on the inner wall of the channel hole as tunnel oxide. It should be noted that the thickness of the tunnel must be precisely controlled to ensure proper charge tunneling characteristics and data retention time. Then, ALD technology is used to deposit silicon nitride layer by layer, so that a very uniform and dense film can be obtained. This process requires adjusting the thickness and doping concentration of the silicon nitride layer according to design requirements to optimize the charge capture capability and durability.

[0068] Forming the top electrode: Use evaporation to deposit a metal layer, such as copper or gold, as a word line or bit line. Use a step process to ensure that each memory cell is effectively connected to the external circuit. Copper is deposited using physical vapor deposition. Physical vapor deposition uses argon plasma to bombard a copper target, sputtering copper onto a wafer to deposit a layer of metal copper we need. However, PVD growth of copper has certain requirements for the size and shape of the wire. It is usually required that the sidewall angle of the shape cannot be too large, otherwise the sputtered copper cannot grow on the sidewall. In addition, PVD copper requires that the line width cannot be too small. Because copper is a metal with strong fluidity, during the PVD copper process, copper atoms will move and gather in places where there are more copper atoms. Therefore, the copper at the bottom of the through hole will move upward to the opening of the shape and gather, which will cause the opening to be sealed in advance, and the copper cannot fill the shape, and form voids in the metal wire and through hole, affecting the resistance and reliability of the metal connection. Electroplating requires first using PVD to grow a very thin layer of copper as a seed layer to facilitate the growth of copper. On the other hand, electroplating also requires this layer of copper as the cathode of electroplating.

[0069] After copper deposition is completed, annealing is required to allow the copper grains to grow. On the one hand, this is to obtain a smaller resistance, and on the other hand, it is to eliminate the stress of the metal film to prevent defects in subsequent processes and enhance the copper material's resistance to electromigration and stress migration.

[0070] This structure uses a gate replacement process, that is, the gate is deposited after the gate dielectric layer is formed. The gate replacement technology is: first, a stacked structure is constructed by alternately depositing an oxide layer and a sacrificial silicon nitride layer. Subsequently, the stacked structure is separated between the memory pillars using etching technology. Next, the sacrificial silicon nitride layer is removed. Finally, the gate dielectric layer and the tungsten metal gate are deposited in sequence. Finally, the excess tungsten is etched away to isolate the different gate layers. In this way, a metal gate SONOS device is formed, as shown in Figure 1. Figure 5 and Figure 6The circuit equivalent diagram shown in the figure shows that the gate is made of metal, and the current in the channel can be controlled by voltage. Compared with the traditional polysilicon gate, the metal gate can not only achieve higher density integration but also reduce defects in the gate oxide layer, thereby improving long-term reliability. This device structure can achieve faster erase speed. Stronger charge retention ability, larger threshold voltage window value, in addition, the metal gate reduces the lead resistance of the word line and improves the operation speed. Another benefit of this structure is that block erase operation can be realized. The vertical columnar memory is formed on a p-type substrate instead of an n+ implanted substrate. There is an n+ implanted area near each NOR memory string to drive the current. During the erase process, holes are directly provided by the substrate instead of being generated near the source selection line using the GIDL effect. This structure uses a gate-last process, and the charge capture layer is a serpentine structure. This structure reduces the charge diffusion effect, making it difficult for the captured charge to drift from one device to another.

[0071] Package: Wafer-level packaging is performed to protect the device from environmental factors such as temperature and humidity.

[0072] Post-processing and testing: Chemical mechanical polishing (CMP) technology is used to flatten the device surface and improve the yield. CMP is a combination of chemical reaction and mechanical action. The abrasive used contains reactive liquid in addition to abrasive. CMP makes the surface material easy to remove through the chemical reaction between the abrasive and the surface material, and then mechanically removes the surface material through the action of the abrasive and the polishing pad. Electrical tests and reliability tests are then carried out to verify the performance indicators of the memory, including read and write speed, durability, data retention time and long-term stability.

[0073] Optimization and Improvement: Implement feedback loops to adjust process parameters and production processes based on test results. Introduce new materials and processes to continuously improve product performance and reduce costs.

[0074] The non-volatile function of Flash and the high performance of storage-computing integrated technology make the present invention promising for use in the fields of smart phones, smart wearables, the Internet of Things, and vehicle-mounted applications.

[0075] The NOR Flash-based integrated storage and computing chip of the present invention can avoid the "storage wall" and "power wall" bottlenecks encountered by traditional AI architecture chips, significantly improve computing efficiency, and greatly reduce power consumption. This is because the integrated storage and computing technology reduces unnecessary data transfer between the memory and the processor, thereby reducing energy consumption to 1 / 10~1 / 100. The schematic diagram of reducing power consumption is shown in the figure below. Figure 7 The left side shown represents the traditional Feng structure, while the right side is the storage and computing integrated architecture.

[0076] It should be noted that the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware. The hardware portion can be implemented using dedicated logic; the software portion can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated hardware. A person of ordinary skill in the art will appreciate that the above-mentioned devices and methods can be implemented using computer executable instructions and / or contained in a processor control code, such as a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. Such code is provided on a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The device and its modules of the present invention can be implemented by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., can also be implemented by software executed by various types of processors, or can be implemented by a combination of the above-mentioned hardware circuits and software, such as firmware. The expected effect diagram of the present invention is shown in FIG. Figure 8 shown.

[0077] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principle of the present invention should be covered by the protection scope of the present invention.

Claims

1. A novel three-dimensional storage and computing integrated chip array structure, characterized in that: The chip array includes: A storage unit layer, including multiple storage units based on NOR architecture, for data storage; The NOR structure allows any cell to be accessed and the required storage cells to be used to perform computing tasks; The control module is used to manage the operation of storage units and computing units. Through optimized circuit design, it can accurately control voltage, reduce signal transmission delay, and improve the overall performance of the chip array.

2. The novel three-dimensional storage and computing integrated chip array structure as claimed in claim 1, characterized in that: The storage unit of the storage unit layer adopts a charge trapping device, wherein the medium of the charge trapping layer has a high trap density and a deep trap energy level.

3. The novel three-dimensional storage and computing integrated chip array structure as claimed in claim 1 is characterized in that: The compute units in the compute unit layer support one or more of the following compute technologies: Adder-based computational unit; Multiplier-based computational unit; Computational units based on logic gates; A computational unit based on a neural network.

4. The novel three-dimensional storage and computing integrated chip array structure as claimed in claim 1, characterized in that: The control module comprises: A data read-write controller, used to manage data read and write operations of the storage unit; The computing task scheduler is used to allocate and schedule computing tasks at the computing unit layer; The power management unit is used to monitor and optimize the power consumption of the chip array in real time.

5. The novel three-dimensional storage and computing integrated chip array structure as claimed in claim 1, characterized in that: The chip array includes a cache module for temporarily storing recently or frequently accessed data, reducing direct access to underlying storage devices, reducing access latency and optimizing data transmission efficiency.

6. The novel three-dimensional storage and computing integrated chip array structure as claimed in claim 1, characterized in that: The chip array is manufactured using the following multiple processes: photolithography, etching, epitaxial growth, ion implantation, chemical vapor deposition and physical vapor deposition, integrating peripheral circuit modules, NO stack modules, step modules and channel hole modules.

7. The novel three-dimensional storage and computing integrated chip array structure as claimed in claim 1, characterized in that: The design of the vertical interconnection channel optimizes the signal transmission path, reduces transmission delay, and supports high-speed parallel data transmission between multi-layer storage units and computing units.

8. A method for preparing a novel three-dimensional storage and computing integrated chip array, characterized in that: The following steps are involved: S1: Store input data in the storage unit layer; S2: Access any cell in the array by regulating the peripheral circuits; S3: performing addition, multiplication, logic gate or neural network calculation on the units that need to be calculated; S4: returning the calculation results to the storage unit layer through the vertical interconnection channel for storage or further processing; S5: The control module schedules the storage unit layer and regulates the units that need to be calculated to optimize the data flow transmission efficiency and reduce the signal transmission delay.

9. The method for preparing the novel three-dimensional storage and computing integrated chip array according to claim 8, characterized in that: The following steps are involved: S1: Using a charge trapping memory device to store data, the charge trapping layer has a high trap density and a deep trap energy level to improve the reliability of data storage; S2: Use the cache module to temporarily store frequently accessed data to reduce direct access to the storage unit layer; S3: A low voltage is used for the read operation of the storage unit, and a high voltage is used for the write operation. The data read and write management is completed by the data read and write controller.

10. The method for preparing the novel three-dimensional storage and computing integrated chip array according to claim 8, characterized in that: The following steps are involved: S1: The control module monitors the power consumption of the chip array in real time and calculates the energy consumption distribution of each computing unit layer and storage unit layer; S2: Dynamically adjust the computing task scheduler to optimize the workload distribution at the computing unit layer according to the energy consumption distribution; S3: using the power management unit to perform a sleep operation on the idle computing unit or storage unit, thereby reducing the overall power consumption; S4: Switches between high-performance and low-power modes, dynamically allocating resources based on task requirements.

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