High-durability FeNAND device with micro heater and preparation method of high-durability FeNAND device

Abstract

The invention discloses a high-durability FeNAND device with a micro heater and a preparation method of the high-durability FeNAND device, and belongs to the technical field of micro-nano electronics. The FeNAND memory is composed of the FeNAND memory and the micro heater, and the Joule heat generated by the micro heater is utilized to recover the fatigue of the FeNAND device caused by write-in circulation, so that the durability of the FeNAND is effectively optimized, and the storage density of the FeNAND memory is not influenced at the same time. The FeNAND device with the micro heater is compatible with an advanced node three-dimensional NAND storage technology, no extra technology cost is introduced, the influence on the storage density is small, and the FeNAND device can be conveniently applied to the three-dimensional FeNAND storage technology.

Description

Technical Field

[0001] The invention belongs to the technical field of micro-nanoelectronics, and in particular relates to a novel high-durability FeNAND device with a microheater and a preparation method thereof. Background Art

[0002] Currently, 3D NAND memory based on charge trap flash (CTF) has become the mainstream technology in the field of high-density storage. However, with the continuous improvement of memory integration and performance requirements, 3D NAND has encountered significant technical challenges in further reducing the vertical spacing. Among them, inter-cell interference and the physical thickness limitation of the oxide spacer between adjacent cells have become the main bottlenecks. Since CTF technology relies on the charge storage mechanism, charge migration is prone to occur when the storage cells are stacked closely vertically, resulting in inter-cell interference problems. In addition, the thickness of the oxide spacer between cells is difficult to further reduce, which limits the vertical miniaturization capability of the memory and hinders the realization of higher integration density.

[0003] In response to the above problems, NAND technology based on hafnium oxide-based ferroelectric field effect transistors (FeFETs) (referred to as FeNAND) is regarded as one of the most promising candidates for the next generation of 3D NAND technology. Unlike traditional CTF technology, FeNAND significantly suppresses the charge migration phenomenon between cells through the bistable polarization characteristics of ferroelectric materials, effectively reducing the occurrence of interference. At the same time, FeNAND relies on the lower switching voltage characteristics of ferroelectric materials to achieve a lower operating voltage, which allows the vertical height of the storage cell and the spacing between cells to be further reduced, thereby not only achieving a higher integration density in the vertical height, but also significantly improving the reliability of the memory, providing a new technical path for the next generation of high-density 3D NAND storage technology.

[0004] Although the storage window of ferroelectric field effect transistors (FeFETs) is smaller than that of traditional charge trap flash (CTF), recent research on FeFETs with MIFIS (Metal-Insulator-Ferroelectric-Insulator-Semiconductor) structures has made important progress. By utilizing the trapped charges in the gate interface layer, the storage window can be expanded to a maximum of 15V. This technological breakthrough significantly improves the performance of FeFETs and lays the foundation for its greater potential in practical applications. Benefiting from the lower operating voltage, lower power consumption and faster write speed of FeNAND compared to traditional CTF flash memory, as well as the high density potential brought by three-dimensional stacking, FeNAND has also shown great application potential in new computing architectures, such as in-memory computing. However, in new computing architectures that require frequent writing, FeNAND still faces severe durability issues, which has become a key factor restricting its further development. In particular, after the introduction of the gate interface layer, due to the additional charge trapping effect, the performance degradation of the storage unit under high-frequency operation is more serious. This phenomenon not only shortens the write / erase cycle life of the unit, but also makes FeNAND technology face a severe trade-off between storage density and reliability. In high-density storage application scenarios, in order to further improve the integration and performance of storage units, most research focuses on improving storage density, ignoring the need for coordinated optimization of storage density and durability. This unilateral pursuit of storage density research trend may cause durability to become a key bottleneck for the actual deployment and widespread application of FeNAND in the future. Therefore, how to balance storage density in FeNAND while solving the long-standing durability challenges has become a technical problem that needs to be overcome. Summary of the invention

[0005] In response to the above-mentioned demand for FeNAND technology that takes into account both storage density and durability, the present invention proposes a new type of high-durability FeNAND device with a microheater and a preparation method thereof, which consists of a FeNAND memory and a microheater surrounding it. The Joule heat generated by the microheater can restore the fatigue of the FeNAND device caused by the write cycle, thereby effectively optimizing the durability of the FeNAND without affecting the storage density of the FeNAND memory. The FeNAND device with a microheater proposed by the present invention is compatible with the advanced node three-dimensional NAND storage technology process, does not introduce additional process costs, has little impact on storage density, and can be easily applied to three-dimensional FeNAND storage technology.

[0006] Specifically, the technical solution of the present invention is as follows:

[0007] A high-durability FeNAND device with a microheater comprises a silicon substrate, a gate stack structure, a gate metal electrode, and a source and drain region; the silicon substrate comprises a bottom silicon layer, a buried oxide layer, and a top silicon layer from bottom to top, a plurality of gate stack structures are arranged above the top silicon layer, and the gate stack structure comprises an aluminum oxide channel interface layer, a hafnium zirconium oxide ferroelectric layer, and an aluminum oxide gate interface layer from bottom to top: the aluminum oxide channel interface layer is located on the top silicon layer, the hafnium zirconium oxide ferroelectric layer is on the aluminum oxide channel interface layer, the aluminum oxide gate interface layer is on the hafnium zirconium oxide ferroelectric layer, and one of the gate stack structures is used as The gate of the FeNAND device, the source and drain regions of the FeNAND device are arranged on both sides of the top silicon below the gate stack, the gate metal electrode is on the gate stack structure, the other gate stack structures and the conductive filaments arranged thereon are used as micro heaters, the conductive filaments are wavy or zigzag and are located on both sides of the gate of the FeNAND device, the top silicon is filled with passivation layer material, the passivation layer is left with gate metal electrodes, source and drain regions of the FeNAND device and contact holes of the micro heater, and the contact metal fills the contact holes and covers the passivation layer.

[0008] Furthermore, the silicon substrate adopts a fully depleted SOI wafer, wherein the thickness of the top silicon is 10-15nm, the thickness of the silicon dioxide buried oxide layer under the top silicon is 15-30nm, and the thickness of the bottom silicon is about 500μm. In the top silicon, for n-type FeNAND, a lower concentration of arsenic or phosphorus is used for doping, and for p-type FeNAND, a lower concentration of boron is used for doping.

[0009] Furthermore, the thickness of the aluminum oxide channel interface layer is 1 to 2 nm.

[0010] Furthermore, in the hafnium zirconium oxide ferroelectric layer, the ratio of hafnium atoms to zirconium atoms is 1:1, and the thickness is 10-20 nm.

[0011] Furthermore, the thickness of the aluminum oxide gate interface layer is 3-6 nm.

[0012] Furthermore, the gate metal material may be a metallic material with a relatively low resistivity such as TiN, TaN or W, and a certain stress needs to be formed on the ferroelectric layer to induce the formation of stable ferroelectricity.

[0013] Furthermore, the source and drain of the FeNAND device are regions formed by implanting high-concentration ions in the top silicon layer, with high-concentration arsenic or phosphorus doping for n-type FeNAND and high-concentration boron doping for p-type FeNAND.

[0014] Furthermore, the conductive filament of the microheater is made of the same material as the gate metal electrode, which is made of a metallic material such as TiN and W that has good conductivity and high thermal stability, and needs to have a small size to provide sufficient Joule heat.

[0015] Furthermore, the passivation layer is made of silicon dioxide with a thickness of 300-700 nm.

[0016] Furthermore, the contact metal material includes but is not limited to Al, Pt, Cr, Cu, Au, Ti and the like; the contact metal should have a low resistivity and form a good ohmic contact with the source and drain to reduce the contact resistance.

[0017] The present invention also provides a method for preparing a high-durability FeNAND device with a microheater, comprising the following steps:

[0018] (1) Define the active area on the SOI silicon substrate, then use the photoresist as a barrier layer to etch away the top silicon of the non-active area, leaking the buried oxide layer underneath, thereby forming isolation between devices, and then remove the photoresist;

[0019] (2) using a diluted hydrofluoric acid solution or a buffered hydrofluoric acid etchant (BOE) to remove the natural oxide layer on the top silicon surface of the active area silicon substrate;

[0020] (3) growing an aluminum oxide channel interface layer by atomic layer deposition on the top silicon layer of the active area;

[0021] (4) growing a hafnium zirconium oxide ferroelectric layer on the aluminum oxide channel interface layer by atomic layer deposition;

[0022] (5) growing an aluminum oxide gate interface layer on the hafnium zirconium oxide ferroelectric layer by atomic layer deposition;

[0023] (6) growing a gate metal electrode and a conductive filament material on the aluminum oxide gate interface layer by physical vapor deposition (PVD);

[0024] (7) defining the gate metal electrode region and the conductive filament region by electron beam lithography, using electron beam photoresist as a barrier layer, and then dry etching to remove the gate metal electrode and conductive filament materials in other regions;

[0025] (8) using photoresist and gate metal electrodes as barrier layers, forming the source and drain regions of the FeNAND device by self-aligned ion implantation on the top silicon on both sides of the gate region of the FeNAND device, and the middle between the source and drain regions is the channel region of the FeNAND device;

[0026] (9) Rapid thermal annealing (RTP) is performed on the entire chip to simultaneously activate the ferroelectricity of the mixed ferroelectric layer and the ions injected into the source and drain regions;

[0027] (10) growing a silicon dioxide passivation layer over the entire wafer by chemical vapor deposition (CVD);

[0028] (11) Then, the gate, source, drain regions of the FeNAND and the contact hole pattern of the microheater are defined by ultraviolet lithography, and the photoresist is used as a barrier layer. The silicon dioxide passivation layer in the contact hole region is removed by dry etching and wet etching to form a through hole, and then the photoresist is removed;

[0029] (12) depositing source, drain, and gate contact metals on the entire wafer by sputtering, evaporation, or other physical vapor deposition methods, wherein the contact metals fill the contact holes and cover the surface above the silicon dioxide passivation layer;

[0030] (13) defining the pattern of the contact metal electrodes of the gate, source, and drain by ultraviolet lithography, using the photoresist as a barrier layer, and removing the contact metal in the remaining area by dry etching to ensure that the etching is carried through to the silicon dioxide passivation layer, and then removing the photoresist;

[0031] (14) Finally, the alloy is annealed to form an ohmic contact between the contact metal and the source and drain.

[0032] Furthermore, in the steps (3), (4) and (5), the method of atomic layer deposition (ALD) is preferably used to grow the aluminum oxide interface layer and the hafnium zirconium oxide ferroelectric layer, and trimethylaluminum (TMA), tetrakis(dimethylamino)hafnium (TDMAHf), tetrakis(dimethylamino)zirconium (TDMAZr) and water can be used as precursors of aluminum, hafnium, zirconium and oxygen, respectively. The deposition can be completed in the same atomic layer deposition (ALD) step, and the growth order of the material and the ratio of the number of atoms in the hafnium zirconium oxide layer can be controlled by setting the pulse sequence of different components in the program, thereby simplifying the process steps. The ratio of the number of hafnium atoms to the number of zirconium atoms in the finally formed hafnium zirconium oxide ferroelectric layer is 1:1, thereby ensuring stable ferroelectricity.

[0033] Furthermore, the gate metal electrode and the conductive filament grown by PVD in step (6) are made of the same metallic material, such as TiN, thereby simplifying the process.

[0034] Furthermore, the electron beam lithography in step (7) is used to define a gate region with a smaller width and length and a thinner conductive filament region, so that the formed FeNAND device has a higher storage density and the microheater has a better heating effect.

[0035] Furthermore, in the self-aligned ion implantation of step (8), it is necessary to perform ion implantation on the entire wafer using appropriate energy and dosage according to the doping concentration and depth of the desired source and drain to ensure that a source and drain with low resistivity can be formed without damaging other structures.

[0036] Furthermore, the temperature and time of the rapid thermal annealing process in step (9) need to simultaneously meet the conditions for mixed ferroelectric layer activation and source-drain activation, and need to be flexibly adjusted according to the ferroelectric layer material, gate material, implanted ion type and dosage, and the approximate range is: annealing temperature is 500-900°C, and annealing time is 10-120s.

[0037] Furthermore, in step (14), the alloy annealing temperature is 400-450° C. and the time is about 30 minutes.

[0038] The technical effects of the present invention are as follows:

[0039] 1. The Joule heating effect of the electric current generated by the microheater can be used to restore the performance of the fatigued FeNAND device, thereby improving the durability of the FeNAND device and extending its service life.

[0040] In the present invention, unlike other common FeNAND devices, the proposed high-durability FeNAND device is surrounded by a microheater. In the FeNAND memory device, each time a write is performed, a large amount of trapped charge capture occurs in the gate stack of the FeNAND device due to the influence of the larger write electric field, and new interface traps are generated. As the number of writes increases, a large amount of interface trap charges will accumulate in the gate stack, and a large number of new interface traps will be generated. These new interface traps will further increase the trapped trap charges, gradually shielding the ferroelectric polarization, thereby causing the threshold voltage of the FeNAND device to shift, the storage window to decrease, and the performance to degrade. By utilizing the Joule heating effect generated by the microheater when the current is passed, the temperature around the FeNAND device can be increased. Under the action of high temperature, the interface trap charges accumulated in the FeNAND gate stack are decaptured, and the traps in the gate stack will be passivated, thereby restoring the performance of the fatigued FeNAND device. By using this durability recovery method, the durability of the FeNAND device can be further extended.

[0041] Second, the microheater proposed in the present invention is compatible with the integration process of the three-dimensional structure FeNAND device, does not increase the cost of the device manufacturing process, and due to its small size, can maximize the guarantee that the storage density of the three-dimensional structure FeNAND memory is not affected. The FeNAND device with a microheater proposed in the present invention is compatible with the three-dimensional structure NANDFlash process of advanced nodes, and is expected to be combined with the future high-density three-dimensional structure FeNAND storage technology to improve its durability. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1In the figure, (a) is a cross-sectional schematic diagram of a high-durability FeNAND device with a microheater prepared in an embodiment of the present invention, and (b) is a top view of a high-durability FeNAND device with a microheater prepared in an embodiment of the present invention;

[0043] Figure 2 Schematic diagram of each step of preparing a high-durability FeNAND device with a microheater according to an embodiment of the present invention, wherein:

[0044] (a) is a cross-sectional view of a SOI substrate after the active area pattern is first defined by UV lithography and then the top silicon of the non-active area is removed by dry etching;

[0045] (b) is a cross-sectional view after an aluminum oxide channel interface layer, a hafnium zirconium oxide ferroelectric layer and an aluminum oxide gate interface layer are grown by atomic layer deposition (ALD) on the basis of (a);

[0046] (c) is a cross-sectional view after the gate metal electrode and microheater are grown by physical vapor deposition (PVD) such as sputtering on the basis of (b);

[0047] (d) is a cross-sectional view after the gate area and micro-heater pattern are defined by electron beam lithography based on (c), and the gate metal and gate dielectric layers (aluminum oxide channel interface layer, hafnium zirconium oxide ferroelectric layer and aluminum oxide gate interface layer) in other areas are removed by dry etching;

[0048] (e) is a cross-sectional view after forming source and drain regions by self-aligned ion implantation based on (d) using photoresist and metal layer as barrier layers and annealing;

[0049] (f) is a cross-sectional view after a silicon dioxide passivation layer is grown by chemical vapor deposition (CVD) on the basis of (e);

[0050] (g) is a cross-sectional view of the process of first defining the contact hole pattern by ultraviolet lithography, then removing the silicon dioxide in the contact hole by dry etching and wet etching, and then growing the contact metal by physical vapor deposition methods such as sputtering and evaporation;

[0051] (h) is a cross-sectional view of (g) after the contact metal electrode pattern is defined by UV lithography and the contact metal in the remaining area is removed by dry etching.

[0052] Figure 1 and Figure 2 middle:

[0053] 1——The bottom silicon of SOI substrate 2——The buried oxide layer of SOI substrate

[0054] 3——Top silicon of SOI substrate 4——Aluminum oxide channel interface layer

[0055] 5——Hafnium zirconium oxide ferroelectric layer 6——Aluminum oxide gate interface layer

[0056] 7——Gate metal electrode 8——Micro heater

[0057] 9——Source 10——Drain

[0058] 11——Silicon dioxide passivation layer 12——Contact metal electrode

[0059] Figure 3 This is the recovery effect of the micro-heater of the embodiment of the present invention on the FeNAND device, wherein:

[0060] (a) is after 10 6 After the first write cycle, as the voltage of the micro heater increases, the FeNAND device I d -V g The recovery effect of the curve;

[0061] (b) Changes in threshold voltage and on-state current extracted after recovery as the voltage of the microheater increases;

[0062] Figure 4 This is the result of the durability test of the FeNAND device with a micro heater according to an embodiment of the present invention. DETAILED DESCRIPTION

[0063] The present invention will be further described below by way of examples in conjunction with the accompanying drawings.

[0064] like Figure 1 As shown, the FeNAND device with a microheater prepared in this embodiment includes a bottom silicon layer 1 of a SOI substrate, a buried oxide layer 2 of a SOI substrate, a top silicon layer 3 of a SOI substrate, an aluminum oxide channel interface layer 4, a hafnium zirconium oxide ferroelectric layer 5, an aluminum oxide gate interface layer 6, a gate metal electrode 7, a microheater 8, a source 9 of the FeNAND device, a drain 10 of the FeNAND device, a silicon dioxide passivation layer 11 and a contact metal electrode 12. The gate stack structure includes, from bottom to top, an aluminum oxide channel interface layer, a hafnium zirconium oxide ferroelectric layer and an aluminum oxide gate interface layer: the aluminum oxide channel interface layer 4 in the gate stack structure is located on the top silicon 3, the hafnium zirconium oxide ferroelectric layer 5 is located on the aluminum oxide channel interface layer 4, the aluminum oxide gate interface layer 6 is located on the hafnium zirconium oxide ferroelectric layer 5, the gate metal electrode 7 is located on the gate of the FeNAND device, the microheater 8 includes a gate stack structure and conductive filaments arranged thereon, the conductive filaments are wavy or serrated and are located on both sides of the gate of the FeNAND device, the source 9 and the drain 10 of the FeNAND device are located on both sides below the gate of the FeNAND device, and the gate, source, and drain contact metal electrodes 12 are respectively connected to the gate metal electrode 9, the source 10, the drain 11 of the FeNAND device and the microheater 8.

[0065] The process steps of the FeFET preparation method are as follows: Figure 2 As shown, specifically including:

[0066] 1) Define the pattern of the active area on the SOI substrate by UV lithography, then use the photoresist as a barrier layer, and use dry etching to remove the top silicon 3 (thickness of about 12nm) of the non-active area, ensuring appropriate over-etching to expose the buried oxide layer 2 (thickness of about 20nm) underneath, so as to achieve isolation between different FeNAND devices, and finally remove the photoresist, such as Figure 2 As shown in (a);

[0067] 2) Use a diluted hydrofluoric acid solution or a hydrofluoric acid buffered etching solution BHF to remove the natural oxide layer on the surface of the top silicon 3 in the active area. Pay attention to controlling the etching time to avoid etching the exposed buried oxide layer in the non-active area.

[0068] 3) Then, a 2 nm thick aluminum oxide channel interface layer 4 is deposited on the top silicon layer of the active area by atomic layer deposition (ALD);

[0069] 4) A 16 nm thick hafnium zirconium oxide ferroelectric layer 5 is deposited on the aluminum oxide channel interface layer by atomic layer deposition (ALD), wherein the atomic ratio of hafnium atoms to zirconium atoms is 1:1, as shown in FIG. Figure 2 As shown in (b);

[0070] 5) depositing a 3 nm thick aluminum oxide gate interface layer 6 on the hafnium zirconium oxide HZO ferroelectric layer by atomic layer deposition (ALD);

[0071] 6) A 50 nm thick gate metal material 7 is grown on the aluminum oxide gate interface layer by a physical vapor deposition (PVD) method such as evaporation or sputtering, such as Figure 2 As shown in (c);

[0072] 7) Define the pattern of the gate area and the microheater by electron beam lithography, then use the electron beam photoresist as a barrier layer and use dry etching to remove the remaining area not covered by the photoresist and the underlying gate stack structure, such as Figure 2 As shown in (d), the remaining parts are the gate metal electrode 7 and the micro heater 8;

[0073] 8) According to the n-type or p-type FeFET, select appropriate ions to implant the whole wafer with an energy of 5 keV and a surface dose of 10 14 cm -2In the gate region, due to the blocking of the photoresist and the gate stack structure, the ions will not be injected into the gate structure, and the ions on both sides of the gate stack structure are injected into the top silicon 3 to form the source 9 and drain 10 regions, and the middle of the source and drain regions is the channel region. For n-type FeFET, high-concentration arsenic or phosphorus and other elements can be used to form n-type sources and drains, and for p-type FeFET, high-concentration boron and other elements can be used to form p-type sources and drains.

[0074] 9) Then the whole chip is subjected to rapid thermal annealing treatment, the annealing temperature is 700-900℃, the annealing time is 10-60s, the annealing conditions need to be flexibly adjusted according to the doping ratio of the ferroelectric layer, the gate type and the type, concentration and dosage of the implanted ions, etc., and it is necessary to ensure that the ferroelectricity of the ferroelectric layer and the implanted ions in the source and drain regions are activated at the same time, such as Figure 2 As shown in (e);

[0075] 10) A thick silicon dioxide passivation layer 11 (about 500 nm) is grown on the whole wafer by chemical vapor deposition (CVD). Figure 2 As shown in (f);

[0076] 11) defining the through-hole pattern of the gate metal electrode 9, source 10, and drain 11 regions by ultraviolet lithography, forming through-holes in the silicon dioxide passivation layer 12 by combining dry etching and wet etching, ensuring that the gate metal electrode 7, microheater 8, source 9, and drain 11 regions are exposed by overetching, and then removing the photoresist;

[0077] 12) Then, source, drain, and gate contact metal electrodes 12 (about 1 μm) are grown on the entire wafer by physical vapor deposition (PVD) methods such as sputtering and evaporation. The contact metal fills the through holes and covers the surface of the silicon dioxide passivation layer 11. Figure 2 As shown in (g);

[0078] 13) Define the pattern of the contact metal electrode 12 by ultraviolet lithography, use the photoresist as a barrier layer, and use dry etching to remove the contact metal in the remaining area, ensuring that the etching reaches the silicon dioxide passivation layer 11, and then remove the photoresist, such as Figure 2 As shown in (h);

[0079] 14) Finally, alloy annealing is performed to form ohmic contact between the contact metal and the source and drain. The alloy annealing temperature is 400-450° C. and the time is about 30 minutes.

[0080] At this point, the high-durability FeNAND device with a micro-heater can be manufactured.

[0081] Figure 3 This is the recovery effect of the microheater prepared in the present invention on the FeNAND device. From (a), it can be found that after 10 6After the first write cycle, the FeNAND device fatigues, the on-state current decreases, and the threshold voltage shifts to the negative direction. As the voltage applied to the microheater increases, the current flowing through the microheater increases, the current Joule heating effect intensifies, the temperature around the FeNAND gate stack increases, and the I d -V g The curve gradually recovers, the on-state current increases, and the threshold voltage shifts in the positive direction, indicating that the microheater can effectively recover the FeNAND device that is fatigued after cycling. (b) is the threshold voltage and V of the FeNAND device after recovery by the microheater. g =The relationship between the on-state current at -1V and the voltage applied to the microheater. As the microheater voltage increases from 0V to 8V, the threshold voltage of the FeNAND device increases from 0.71V to 1.22V, while V g = The on-state current at -1V increases from 2.35μA to 5.72μA.

[0082] Figure 4 The durability test results of the FeNAND device with a microheater prepared in the embodiment of the present invention are shown in FIG. 6 After 10 write cycles, the storage window is reduced to about 2.0V. 6 After each writing cycle, a voltage is applied to the microheater to perform heating once as a recovery cycle. After 200 recovery cycles, that is, after 2×10 8 After the write cycle, the FeNAND device still maintains a storage window greater than 2.0V, and no obvious threshold voltage shift occurs. Therefore, the durability of the FeNAND device with a microheater proposed in the present invention is improved by more than two orders of magnitude compared to the durability of the FeNAND device without a microheater, effectively optimizing the durability of the FeNAND.

[0083] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A high-durability FeNAND device with a microheater, characterized in that: The invention comprises a silicon substrate, a gate stack structure, a gate metal electrode and a source and drain region; the silicon substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer from bottom to top, a plurality of gate stack structures are arranged above the top silicon layer, and the gate stack structure comprises an aluminum oxide channel interface layer, a hafnium zirconium oxide ferroelectric layer and an aluminum oxide gate interface layer from bottom to top: the aluminum oxide channel interface layer is located on the top silicon layer, the hafnium zirconium oxide ferroelectric layer is located on the aluminum oxide channel interface layer, the aluminum oxide gate interface layer is located on the hafnium zirconium oxide ferroelectric layer, and one of the gate stack structures is used as a gate of a FeNAND device. The gate stack has a gate metal electrode on both sides of the top silicon layer below the gate stack, and other gate stack structures and conductive filaments thereon serve as micro-heaters. The conductive filaments are wavy or zigzag and are located on both sides of the gate of the FeNAND device. A passivation layer material is filled above the top silicon layer, and the gate metal electrode, the source and drain regions of the FeNAND device, and the contact holes of the micro-heater are reserved in the passivation layer. The contact holes are filled with contact metal and covered on the passivation layer.

2. The high-durability FeNAND device with a microheater according to claim 1, characterized in that: The thickness of the aluminum oxide channel interface layer in the gate stack structure is 1-2 nm; the ratio of hafnium atoms to zirconium atoms in the hafnium zirconium oxide ferroelectric layer is 1:1, and its thickness is 10-20 nm; the thickness of the aluminum oxide gate interface layer is 3-6 nm.

3. The high-durability FeNAND device with a microheater according to claim 1, wherein: The silicon substrate specifically adopts a fully depleted SOI wafer, wherein the thickness of the top silicon is 10-15nm, the thickness of the silicon dioxide buried oxide layer under the top silicon is 15-30nm, and the thickness of the bottom silicon is within 500μm, wherein for n-type FeNAND, the top silicon is doped with arsenic or phosphorus at a relatively low concentration, and for p-type FeNAND, the top silicon is doped with boron at a relatively low concentration.

4. The high-durability FeNAND device with a microheater according to claim 1, wherein: The conductive filaments of the micro heater and the gate metal electrode are made of the same material, which is TiN, TaN or W metallic material.

5. The high-durability FeNAND device with a micro-heater according to claim 1, characterized in that: The source and drain regions of the FeNAND device are regions formed by implanting high-concentration ions into the top silicon layer. For n-type FeNAND, high-concentration arsenic or phosphorus doping is used, and for p-type FeNAND, high-concentration boron doping is used.

6. The high-durability FeNAND device with a micro-heater according to claim 1, characterized in that: The contact metal material is selected from one of Al, Pt, Cr, Cu, Au, and Ti.

7. The high-durability FeNAND device with a micro-heater according to claim 1, characterized in that: The material of the passivation layer is silicon dioxide, and the thickness is 300-700nm.

8. A method for preparing a high-durability FeNAND device with a microheater as claimed in claim 1, comprising the following steps: 1) Define the active area on the SOI silicon substrate, then use the photoresist as a barrier layer to etch away the top silicon of the non-active area, leaking the buried oxide layer underneath, thereby forming isolation between devices, and then remove the photoresist; 2) using a diluted hydrofluoric acid solution or a hydrofluoric acid buffered etching solution to remove the natural oxide layer on the top silicon surface of the active area silicon substrate; 3) On the top silicon layer of the active area, an aluminum oxide channel interface layer is grown by atomic layer deposition; 4) growing a hafnium zirconium oxide ferroelectric layer on the aluminum oxide channel interface layer by atomic layer deposition; 5) growing an aluminum oxide gate interface layer by atomic layer deposition on the hafnium zirconium oxide ferroelectric layer; 6) growing a gate metal electrode and a conductive filament material on the aluminum oxide gate interface layer by physical vapor deposition; 7) defining the gate metal electrode region and the conductive filament region by electron beam lithography, using electron beam photoresist as a barrier layer, and then dry etching to remove the gate metal electrode and conductive filament materials in other regions; 8) Using photoresist and gate metal electrodes as barrier layers, self-aligned ion implantation is used to form the source and drain regions of the FeNAND device on the top silicon on both sides of the gate region of the FeNAND device, and the middle between the source and drain regions is the channel region of the FeNAND device; 9) Rapid thermal annealing is performed on the entire chip to simultaneously activate the ferroelectricity of the mixed ferroelectric layer and the ions injected into the source and drain regions; 10) growing a silicon dioxide passivation layer on the entire wafer by chemical vapor deposition; 11) Define the gate, source, drain regions of FeNAND and the contact hole pattern of the microheater by ultraviolet lithography, use photoresist as a barrier layer, use dry etching and wet etching to remove the silicon dioxide passivation layer in the contact hole area to form a through hole, and then remove the photoresist; 12) The source, drain and gate contact metals are grown and deposited on the whole wafer by sputtering, evaporation or other physical vapor deposition methods, and the contact metals fill the contact holes and cover the surface above the silicon dioxide passivation layer; 13) defining the pattern of the contact metal electrodes of the gate, source and drain by ultraviolet lithography, using the photoresist as a barrier layer, and removing the contact metal in the remaining area by dry etching to ensure that the etching reaches the silicon dioxide passivation layer, and then removing the photoresist; 14) Finally, alloy annealing is performed to form an ohmic contact between the contact metal and the source and drain.

9. The preparation method according to claim 8, characterized in that: The rapid thermal annealing temperature in step 9) is 500-900° C., and the annealing time is 10-120 seconds.

10. The preparation method according to claim 8, characterized in that: In the step 14), the alloy annealing temperature is 400-450° C. and the time is within 30 minutes.

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