Memory with four-end structure, memory array and memory preparation method

Abstract

The invention discloses a memory with a four-end structure, a memory array and a memory preparation method, and belongs to the technical field of semiconductor memories. Comprising a substrate; the vertical structure resistive random access memory and the transverse structure ferroelectric memory are formed on the substrate; the resistive random access memory and the ferroelectric memory are integrated in a single device; the memory comprises four terminals. A resistive random access memory with a vertical structure and a ferroelectric memory with a transverse structure are combined, the resistive random access memory and the ferroelectric memory are integrated in a single device, and the prepared device is simple in structure, can freely switch a binary digital storage function and can simulate a resistive random behavior in a multi-valued manner. According to the memory with the four-end structure, freely selected digital or analog resistance switch behaviors can be realized in a single device, a highly integrated digital / analog memory unit is realized, and flexible storage application is realized in a targeted storage scene.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor memory, and in particular to a memory with a four-terminal structure, a memory array and a memory preparation method. Background Art

[0002] In modern society, storage devices, as a core component of information technology, undertake the key task of storing and managing massive amounts of data, and are one of the foundations for promoting the development of the information age. With the continuous deepening of the digitalization process, technologies such as big data, artificial intelligence and cloud computing have flourished, and the amount of data generated, stored and processed has increased rapidly, bringing huge challenges and changes to the way data is stored and processed.

[0003] Traditional memory technology faces many challenges, such as high energy consumption, difficulty in size reduction, slow reading and writing speed, etc., which makes it difficult to meet the growing market demand. High-density and multifunctional memory devices are increasingly expected. New random access memory technologies, such as resistive random access memory, phase change memory, magnetoresistive random access memory and ferroelectric memory, have the advantages of high integration, high speed, low energy consumption and long data retention time, and are gradually being applied to various electronic devices and data centers. According to the different states of stored information, memory devices can be divided into binary digital memory and multi-value analog memory. Binary digital storage has high precision, high stability and strong anti-interference ability, and occupies a major position in storage and computing systems. Analog storage with multi-value information mode is conducive to improving storage density, allowing multiple states in a single storage unit, with higher information storage density and versatility in storing complex information, and has the potential to simulate artificial synaptic behavior, which is gradually becoming one of the important directions for research on new memory devices.

[0004] Therefore, there is an urgent need to provide a memory with a four-terminal structure, a memory array and a memory preparation method to meet the above requirements. Summary of the invention

[0005] The purpose of the present invention is to provide a memory, a memory array and a memory preparation method with a four-terminal structure, so as to realize free selection of analog and digital resistance switching behaviors in a single device, realize highly integrated digital / analog storage units, and realize flexible storage applications in targeted storage scenarios.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a memory with a four-terminal structure, the memory comprising:

[0008] substrate;

[0009] A resistive memory and a ferroelectric memory are formed on the substrate; the resistive memory is a vertical structure, and the ferroelectric memory is a lateral structure;

[0010] The resistive memory and the ferroelectric memory are integrated into a single device; the memory includes four terminals.

[0011] Optionally, the substrate serves as a fourth terminal;

[0012] The memory includes a first terminal, a second terminal, a third terminal and a semiconductor material;

[0013] The first terminal is formed on a semiconductor material, and the semiconductor material is formed between the third terminal and the first terminal.

[0014] Optionally, the substrate serves as a fourth terminal, the third terminal is formed on the fourth terminal, the semiconductor material is formed between the second terminal and the fourth terminal, and a portion of the semiconductor material is located on the fourth terminal.

[0015] Optionally, the resistive memory at least includes: a first terminal, a first semiconductor material and a third terminal; the third terminal is formed on the fourth terminal, and the first terminal is formed on the first semiconductor material; the first semiconductor material is located between the first terminal and the third terminal;

[0016] The resistive memory at least comprises: a first terminal, a first semiconductor material and a third terminal; the first terminal is formed on the first semiconductor material; the first semiconductor material is located between the first terminal and the third terminal;

[0017] The ferroelectric memory at least includes: a first terminal, a second terminal and a second semiconductor material; the first terminal and the second terminal are formed on the second semiconductor material.

[0018] Optionally, the resistive memory has a binary non-volatile resistive behavior; the memory has a binary non-volatile resistive behavior, and the memory implements switching of multi-valued conductivity states;

[0019] When the memory realizes artificial synaptic behavior through the multi-valued conductance state of the ferroelectric memory, the memory activates a first terminal and a second terminal, any one of the first terminal and the second terminal is a drain, the other terminal is a source, one end is a synaptic back end, and the other end is a synaptic front end;

[0020] Alternatively, the first terminal, the second terminal and the fourth terminal are activated to form a back-gate field effect transistor structure having a ferroelectric semiconductor channel, any one of the first terminal and the second terminal is a drain, the other terminal is a source, the fourth terminal is a gate, and the fourth terminal is an excitation terminal;

[0021] Alternatively, the first terminal, the second terminal and the fourth terminal are activated to form a back-gate field effect transistor structure having a ferroelectric semiconductor channel;

[0022] Any one of the first terminal and the second terminal is a drain, the other terminal is a source, and the fourth terminal is a gate; any one of the first terminal and the second terminal is a synaptic front end, the other terminal is a synaptic back end, and the fourth terminal is a modulation end.

[0023] Optionally, when the memory uses the resistance change of the resistive memory to control the activation or shutdown of the artificial synaptic behavior, a voltage-dividing resistor is connected between the first terminal and the power supply voltage; the second terminal and the third terminal are grounded; and the fourth terminal is a modulation terminal applied to the second semiconductor material;

[0024] The voltage at the first terminal is a common input voltage of the storage and synaptic parts. When the resistive memory is in a high-resistance state, the voltage at the first terminal is greater than a preset threshold voltage, and the artificial synapse works normally; when the resistive memory enters a low-resistance state, the voltage at the first terminal is less than a preset threshold voltage, and the artificial synapse is closed.

[0025] Optionally, when the ferroelectric memory in the memory constructs a reconfigurable logic state, the first terminal is the first input terminal, the second terminal is the second input terminal, the current at the second terminal serves as the output, the third terminal is the control terminal, and the fourth terminal serves as a control terminal and an input terminal for reconstructing the logic function using a pre-written signal; the logic input corresponds to the voltage input of the first terminal and the fourth terminal, and the logic output is the current value at the second terminal.

[0026] Optionally, a reconfigurable logic function is realized by controlling a pre-written signal of the fourth terminal;

[0027] When the write voltage signal of the control terminal is positive, the memory is set to an AND logic gate function; when the control terminal uses a negative voltage signal to write to the memory, the memory is set to an OR logic gate function state.

[0028] Compared with the prior art, the memory of the four-terminal structure provided by the present invention combines the resistive memory of the vertical structure with the ferroelectric memory of the lateral structure, integrates the resistive memory and the ferroelectric memory in a single device, and the prepared device has a simple structure and can freely switch between binary digital storage functions and multi-value analog resistive switching behaviors. The memory of the four-terminal structure provided by the present invention can realize the free selection of digital and analog resistance switching behaviors in a single device, realize a highly integrated digital / analog storage unit, and realize flexible storage applications in targeted storage scenarios.

[0029] In a second aspect, the present invention provides a memory array with a four-terminal structure, wherein the memory array is composed of a plurality of memories with a four-terminal structure as described in the first aspect.

[0030] In a third aspect, the present invention provides a method for preparing a memory having a four-terminal structure, comprising:

[0031] providing a substrate;

[0032] forming a resistive memory on the substrate,

[0033] And, a ferroelectric memory is formed on the substrate; the resistive memory is a vertical structure, and the ferroelectric memory is a lateral structure; the resistive memory and the ferroelectric memory are integrated in a single device; and the memory includes four terminals.

[0034] Optionally, the memory includes a first terminal, a second terminal, a third terminal and a semiconductor material;

[0035] The forming of a resistive random access memory on the substrate specifically includes:

[0036] preparing a third terminal on the substrate;

[0037] preparing a semiconductor material, and transferring the semiconductor material to the substrate;

[0038] Expose and write the electrode pattern onto the photoresist, and develop it in a developer for a preset time to obtain a photoresist layer with the electrode pattern, and prepare a first terminal;

[0039] The electrode is stripped and the patterned first terminal is obtained; the ferroelectric memory is formed on the substrate, specifically comprising:

[0040] preparing a semiconductor material, and transferring the semiconductor material to the substrate;

[0041] Expose and write the electrode pattern onto the photoresist, and develop it in a developer for a preset time to obtain a photoresist layer with the electrode pattern, and prepare a first terminal and a second terminal;

[0042] The electrodes are stripped and the first and second patterned terminals are obtained.

[0043] The technical effects achieved by the memory array provided in the second aspect and the method-like solutions provided in the third aspect are the same as those achieved by the method-like solutions provided in the first aspect, and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0045] Figure 1 A schematic diagram of the structure of a memory with a four-terminal structure provided by the present invention;

[0046] Figure 2 A schematic diagram of the structure of a resistive random access memory in a four-terminal memory provided by the present invention;

[0047] Figure 3 A schematic diagram of the structure of a ferroelectric memory in a four-terminal memory provided by the present invention;

[0048] Figure 4 A schematic diagram of a memory array structure of a four-terminal structure provided by the present invention;

[0049] Figure 5 A schematic diagram of a binary non-volatile resistive switching behavior of a memory with a four-terminal structure in an embodiment of the present invention;

[0050] Figure 6 It is a bidirectional scanning IV curve diagram of multi-valued conductivity state of a memory with a four-terminal structure in an embodiment of the present invention;

[0051] Figure 7 A schematic diagram of a synaptic behavior of a memory device with a four-terminal structure according to an embodiment of the present invention;

[0052] Figure 8 Schematic diagram of the second behavior mode of the memory synapse of the four-terminal structure in the embodiment of the present invention;

[0053] Fig. 9 Schematic diagram of the synaptic behavior of a memory with a four-terminal structure according to an embodiment of the present invention;

[0054] Fig.10 A schematic diagram of the structural design of a resistive memory controlling artificial synaptic gating in a four-terminal memory in an embodiment of the present invention;

[0055] Fig.11 A schematic diagram showing the relationship between the accuracy and training cycle of a four-terminal structure memory for MNIST digital image training based on artificial synaptic behavior in an embodiment of the present invention;

[0056] Fig.12 It is a schematic diagram of the logical function result of the memory "AND" device with a four-terminal structure in an embodiment of the present invention;

[0057] Fig.13 It is a schematic diagram of the logical function result of the memory "OR" device with a four-terminal structure in an embodiment of the present invention;

[0058] Fig.14 It is a schematic diagram of a process for preparing a memory having a four-terminal structure according to an embodiment of the present invention;

[0059] Fig.15 It is a schematic flow chart of a method for preparing a resistive random access memory in a memory with a four-terminal structure according to an embodiment of the present invention;

[0060] Fig.16 It is a schematic flow chart of a method for preparing a ferroelectric memory in a four-terminal structure memory according to an embodiment of the present invention.

[0061] Reference numerals:

[0062] 1-first terminal, 2-second terminal, 3-third terminal, 4-fourth terminal, 5-semiconductor material, 51-first semiconductor material, 52-second semiconductor material, 6-power supply voltage, 7-voltage-dividing resistor. DETAILED DESCRIPTION

[0063] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0064] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0065] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0066] The technical solution provided by the present invention, in view of the unique advantages of digital and analog storage, is expected to realize the free selection of analog and digital resistance switching behaviors in a single device, aiming to realize a highly integrated digital / analog storage unit and realize flexible storage applications in targeted storage scenarios. Next, the solution provided by the embodiment of this specification is described in detail in conjunction with the accompanying drawings:

[0067] Figure 1 The schematic diagram of the structure of a four-terminal memory provided by the present invention. Figure 1 As shown, a four-terminal memory provided by the present invention is a semiconductor device, which may include the following structure:

[0068] substrate;

[0069] A resistive memory and a ferroelectric memory are formed on the substrate; the resistive memory is a vertical structure, and the ferroelectric memory is a lateral structure;

[0070] The resistive memory and the ferroelectric memory are integrated into a single device; the memory includes four terminals.

[0071] It should be noted that, in practical applications, the fourth terminal in the memory is not a necessary structure, and the memory at least needs to include the first terminal 1, the second terminal 2, the third terminal 3 and the semiconductor material 5;

[0072] The first terminal 1 is formed on the semiconductor material 5 , and the semiconductor material 5 is formed between the third terminal 3 and the first terminal 1 .

[0073] As one optional implementation, Figure 1, the substrate can be used as the fourth terminal 4; at this time, a four-terminal structure memory can include a first terminal 1, a second terminal 2, a third terminal 3, a fourth terminal 4 and a semiconductor material 5; wherein the first terminal, the second terminal and the third terminal can be made of the same metal or different metals.

[0074] The third terminal 3 is formed on the fourth terminal 4 , the first terminal 1 is formed on the semiconductor material 5 , the semiconductor material 5 is formed between the third terminal 3 and the first terminal 1 , and the semiconductor material 5 is formed between the second terminal 2 and the fourth terminal 4 , and a portion of the semiconductor material 5 is located on the fourth terminal 4 .

[0075] Figure 1 The structure in the invention combines the vertical resistive memory and the lateral ferroelectric memory, and integrates the resistive memory and the ferroelectric memory into a single device. The prepared device has a simple structure and can freely switch between binary digital storage functions and multi-value analog resistive behaviors. The four-terminal memory provided by the invention can realize the free selection of digital and analog resistive switching behaviors in a single device, realize a highly integrated digital / analog storage unit, and realize flexible storage applications in targeted storage scenarios.

[0076] based on Figure 1 The embodiment of this specification also provides the specific structure of the resistive memory and the ferroelectric memory in the structure, which will be described below.

[0077] Figure 2 A schematic diagram of a resistive memory in a four-terminal memory provided by the present invention; Figure 2 As shown, the fourth terminal in the resistive memory is not a necessary structure. In practical applications, the resistive memory may at least include: a first terminal 1, a first semiconductor material 51 and a third terminal 3; the first terminal 1 is formed on the first semiconductor material 51; the first semiconductor material 51 is located between the first terminal 1 and the third terminal 3. It should be noted that those skilled in the art can understand that the "first" and "second" in the first semiconductor material and the second semiconductor material are only used to distinguish semiconductor materials in different memories, and neither limit their order nor their materials or functions. The words "first" and "second" are not necessarily different. For example, in the present invention, although the first semiconductor material and the second semiconductor material are used for the resistive memory and the ferroelectric memory respectively, the first semiconductor material and the second semiconductor material are the same.

[0078] As an optional implementation, Figure 3The structure of the resistive random access memory may also include a first terminal 1 , a first semiconductor material 51 , a third terminal 3 and a fourth terminal 4 . In this case, the third terminal 3 is formed on the fourth terminal 4 .

[0079] Figure 2 The resistive switching memory in the memory prepared by the four-terminal structure provided by the present invention exhibits a binary non-volatile resistive switching behavior, realizing switching between high and low resistance states. Figure 5 As shown, Figure 5 The left side of the figure shows the process of the device switching from a high resistance state to a low resistance state, and the right side shows the process of the device switching from a low resistance state to a high resistance state. The switching between high and low resistance states is a mutation process.

[0080] Figure 3 The schematic diagram of the structure of a ferroelectric memory in a four-terminal memory provided by the present invention. Figure 3 As shown, the fourth terminal in the ferroelectric memory is not a necessary structure. In practical applications, the ferroelectric memory may at least include: a first terminal 1, a second terminal 2, and a second semiconductor material 52; the first terminal 1 and the second terminal 2 are formed on the second semiconductor material 52.

[0081] As an optional implementation, Figure 4 The ferroelectric memory may also include: a first terminal 1, a second terminal 2, a second semiconductor material 52 and a fourth terminal 4. At this time, the second semiconductor material 52 is formed on the fourth terminal 4.

[0082] Based on the same idea, Figure 4 As shown, the present invention also provides a memory array with a four-terminal structure. The memory array is composed of Figure 1 The memory array of the four-terminal structure shown in FIG. 1 is specifically prepared by referring to Figure 4 , you can use the following methods:

[0083] Performing photolithography and development on the fourth terminal 4 of the substrate and preparing the third terminal 3 of the first array metal bottom electrode;

[0084] Transferring the prepared semiconductor material to a substrate, wherein the semiconductor material layer is placed on the first array of conductive electrodes;

[0085] Performing photolithography, development and reactive ion etching on the semiconductor material layer to prepare an array resistive switching layer; preparing a metal top electrode first terminal 1 on the array semiconductor material layer, the semiconductor material layer being located between the fourth terminal 4 and the first terminal 1;

[0086] A metal top electrode second terminal 2 is prepared on the array semiconductor material layer, and the semiconductor material layer is located between the fourth terminal 4 and the second terminal 2; thus a resistive memory array is obtained.

[0087] The present invention will Figure 2 The resistive memory shown is Figure 3 The ferroelectric memory shown is integrated into a single device, based on the combination of binary non-volatile resistive switching and multi-level conductance states driven by ferroelectric polarization, meeting the multifunctional requirements of digital / analog hybrid applications and non-volatile / volatile resistive switching behavior, realizing freely selectable analog and digital resistive switching behaviors, and demonstrating stable, freely selectable binary digital storage and multi-valued analog conductance states.

[0088] As an embodiment of the present invention, the ferroelectric memory in the memory prepared by the four-terminal structure provided by the present invention realizes the switching of the multi-valued conductivity state by flipping the ferroelectric polarization state under an external electric field. Specifically, the switching of the multi-valued conductivity state provided by the embodiment of the present invention shows that the multi-valued conductivity state realizes good artificial synaptic behavior. The bidirectional scanning IV curve of the device shows an "8"-shaped hysteresis characteristic, such as Figure 6 This indicates that it has the ability to change resistance under voltage excitation, further characterizing its performance in simulating artificial synaptic behavior.

[0089] As an embodiment of the present invention, the memory prepared by the four-terminal structure provided by the present invention realizes good artificial synaptic behavior by displaying a multi-valued conductance state through a ferroelectric memory. More specifically, the multi-valued artificial synaptic behavior provided in the embodiment of the present invention can be implemented in the following three ways for example:

[0090] Method 1: Activate the first terminal 1 and the second terminal 2, and read the current at any one of the first terminal 1 and the second terminal 2 as the post-synaptic current detection, which is defined as the post-synaptic terminal, and the other terminal is used as the input terminal to receive voltage excitation, which is defined as the pre-synaptic terminal. Specifically, Figure 7 As shown, Figure 7 The figure shows the enhancement and inhibition behaviors of the four-terminal memory when the first terminal 1 and the second terminal 2 are activated, where the black lines represent enhancement and the gray lines represent inhibition.

[0091] Method 2: The first terminal 1, the second terminal 2 and the fourth terminal 4 are activated, and the fourth terminal 4 is defined as the excitation terminal. The fourth terminal acts as the synaptic front end, receiving the electric pulse excitation, as the excitation terminal, one of the first terminal 1 and the second terminal 2 applies the reading voltage, and the other terminal is used to read the postsynaptic current, which is the synaptic back end. Figure 8 As shown, Figure 8The enhancement and inhibition behaviors of a four-terminal memory when the first terminal 1, the second terminal 2, and the fourth terminal 4 are activated and the fourth terminal 4 is used as an excitation terminal are shown, wherein the black line represents enhancement and the gray line represents inhibition.

[0092] Method 3: The first terminal 1, the second terminal 2 and the fourth terminal 4 are activated to form a back-gate field effect transistor structure with a ferroelectric semiconductor channel. The fourth terminal 4 is defined as a modulation terminal. The current response read out from any one of the first terminal 1 and the second terminal 2 is the synaptic back end; the other terminal is the synaptic front end; different voltage biases are applied to the modulation terminal fourth terminal 4, thereby modulating the artificial synaptic behavior of the device. Fig. 9 As shown, Fig. 9 The enhancement and inhibition behaviors of the memory with four terminals are shown when the first terminal 1, the second terminal 2, and the fourth terminal 4 are activated and the fourth terminal 4 is used as a modulation terminal. The black line represents enhancement and the gray line represents inhibition. Fig. 9 The device exhibits optimized linearity performance and good stability under gate modulation.

[0093] Furthermore, a four-terminal memory provided by an embodiment of the present invention controls the activation or shutdown of the artificial synapse part by utilizing the rapid change of the resistance of the resistive memory part, such as Fig.10 As shown, the structure includes a first terminal 1, a second terminal 2, a third terminal 3, a power supply voltage 6, a voltage dividing resistor 7, a first resistor and a second resistor, the first resistor is a first semiconductor material 51, and the second resistor is a second semiconductor material 52. The first resistor is located between the first terminal 1 and the third terminal 3, and the second resistor is located between the first terminal 1 and the second terminal 2. The voltage dividing resistor 7 is connected between the first terminal 1 and the power supply voltage 6, the second terminal 2 and the third terminal 3 are grounded, and the voltage at the first terminal 1 is used as a common input voltage for the storage and synapse parts, as shown in FIG. Fig.10 When the resistive memory is in a high-resistance state, the voltage at the first terminal 1 is large enough to ensure the normal operation of the artificial synapse. When the resistive memory enters a low-resistance state, the voltage at the first terminal 1 suddenly decreases, and the presynaptic excitation amplitude decreases rapidly, thereby closing the artificial synapse.

[0094] As an embodiment of the present invention, the memory prepared by the four-terminal structure provided by the present invention uses synaptic behavior to design and construct an artificial neural network, and uses it to simulate the handwritten digit recognition task on the MNIST data set. Fig.11 As shown, Fig.11The training results of hundreds of training cycles of a four-terminal memory based on artificial synaptic behavior for MNIST digital images are demonstrated. After hundreds of training cycles, the distribution of the training results of MNIST digital images is visualized. The results show that the neural network constructed based on the gate-regulated artificial synaptic behavior characteristics has high computational accuracy, demonstrating the application potential of this device in neuromorphic computing.

[0095] As an embodiment of the present invention, the memory prepared by the four-terminal structure provided by the present invention realizes the construction of a reconfigurable logic state through the ferroelectric polarization state of the ferroelectric memory. More specifically, the ferroelectric polarization state of the ferroelectric memory provided by the embodiment of the present invention realizes the construction of a reconfigurable logic state.

[0096] As an optional implementation, the fourth terminal 4 can be used as a control terminal and a first input terminal for reconstructing a logic function using a pre-written signal. The first terminal 1 is defined as a second input terminal, and the current at the second terminal 2 is used as an output. The reconfigurable logic function is achieved by controlling the pre-written signal of the fourth terminal 4, thereby realizing switchable logic functions of "AND" and "OR".

[0097] More specifically, when the write voltage signal of the control terminal is positive or negative, the device is set to the "AND" logic gate function, and the device logic function result is shown as follows: Fig.12 The logic function between the device input and output is shown in Figure 1. The black dotted line is the output threshold. The output current greater than the threshold is logic 1, and the output current less than the threshold is logic 0. Conversely, when the control terminal uses a negative or positive voltage signal to write to the device, the device is set to the "OR" logic gate function state, and the device logic function result is as follows: Fig.13 For example, when the write voltage signal of the control terminal is positive, the "OR" logic function can be realized, and when the write voltage signal of the control terminal is negative, the "AND" logic function can be realized;

[0098] When the write voltage signal of the control terminal is positive, an “AND” logic function can be realized, and when the write voltage signal of the control terminal is negative, an “OR” logic function can be realized.

[0099] Based on the same idea, the present invention also provides a method for preparing a memory with a four-terminal structure, such as Fig.14 As shown, the method may include:

[0100] Step 111: providing a substrate;

[0101] The substrate can be an insulating substrate, and the substrate forms a back gate, which can be used as the fourth terminal 4. It should be noted that it will only be activated when the synaptic behavior is realized in mode 1 and mode 2. When activated, the substrate is an electrode layer + an insulating layer; when not activated, the substrate only needs to be an insulating layer. That is, the form of the substrate can be set according to actual application requirements, and the present invention does not specifically limit this.

[0102] Step 112: forming a resistive random access memory on the substrate, and forming a ferroelectric random access memory on the substrate.

[0103] The resistive memory in step 112 may be a vertical structure, and the ferroelectric memory may be a lateral structure; the resistive memory and the ferroelectric memory are integrated into a single device.

[0104] Similar to the aforementioned four-terminal structure memory embodiment, in actual applications, the fourth terminal in the memory is not a necessary structure, and the memory at least needs to include a first terminal 1, a second terminal 2, a third terminal 3 and a semiconductor material 5; the first terminal 1 is formed on the semiconductor material 5, and the semiconductor material 5 is formed between the third terminal 3 and the first terminal 1.

[0105] based on Fig.14 In the steps of, a four-terminal device is constructed by using a vertical resistive memory and a lateral ferroelectric memory. In step 112, the preparation process of the resistive memory and the preparation process of the ferroelectric memory are described below respectively:

[0106] First, the preparation process of resistive memory can be combined with Fig.15 as well as Figure 2 To illustrate, the preparation process of the resistive random access memory may include the following steps:

[0107] Step 121: Prepare a third terminal 3 on the substrate.

[0108] like Figure 2 As shown, the third terminal 3 is a metal bottom electrode prepared on a substrate, and the substrate is a fourth terminal 4. The substrate may be an insulating substrate, specifically one of sodium chloride, mica, silicon oxide, aluminum oxide, hafnium oxide, boron nitride or strontium titanate. It should be noted that the contact portion between the third terminal and the second semiconductor material is an insulating layer, and when the two post-synaptic modes are realized, the substrate is an insulating layer + electrode layer. The form of the substrate here can also be set according to actual application requirements, and the present invention does not specifically limit this.

[0109] The metal of the third terminal 3 may be one of tungsten, titanium, aluminum, copper, aluminum-copper alloy, platinum, gold, silver, iron, chromium, nickel, tantalum, titanium nitride or tantalum nitride.

[0110] The third terminal 3 may be prepared by magnetron sputtering, thermal evaporation or electron beam evaporation, etc.

[0111] Step 122: Prepare semiconductor material 5, and transfer the semiconductor material 5 to the substrate.

[0112] The preparation method of the semiconductor material 5 nanosheet can be mechanical exfoliation, chemical vapor deposition, chemical vapor transport, physical vapor deposition, atomic layer deposition or molecular beam epitaxy, etc.

[0113] The semiconductor material 5 may be barium titanate, lead titanate, potassium niobate, titanium titanate, bismuth sulfide, bismuth selenide, molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, indium sulfide, indium selenide, tin sulfide or tin selenide, etc.;

[0114] The semiconductor material 5 may be transferred onto the substrate by dry transfer, wet transfer, or other methods.

[0115] Step 123: exposing and writing the electrode pattern onto the photoresist, and developing it in a developer for a preset time to obtain a photoresist layer with the electrode pattern, and preparing the first terminal 1.

[0116] The preset time may be 5-60 seconds. The electrode patterning method may be contact lithography, laser direct writing and electron beam lithography.

[0117] like Figure 2 As shown, the first terminal 1 is a metal top electrode, and the metal of the top electrode can be tungsten, titanium, aluminum, copper, aluminum-copper alloy, platinum, gold, silver, iron, chromium, nickel, tantalum, titanium nitride or tantalum nitride, etc.

[0118] The electrode preparation method can be: magnetron sputtering, thermal evaporation and electron beam evaporation.

[0119] Step 124: remove the glue and peel off the electrode to obtain a patterned first terminal 1.

[0120] When removing the glue in step 124, acetone, developer, or isopropyl alcohol may be used for removal.

[0121] Next, the preparation process of ferroelectric memory can be combined with Fig.16 and Figure 3 To illustrate, the preparation process of the ferroelectric memory may include the following steps:

[0122] Step 131: Prepare semiconductor material 5, and transfer the semiconductor material 5 to the substrate.

[0123] The substrate may be an insulating substrate, specifically one of sodium chloride, mica, silicon oxide, aluminum oxide, hafnium oxide, boron nitride or strontium titanate. It should be noted that the contact portion between the third terminal and the second semiconductor material is an insulating layer, and when the two post-synaptic modes are realized, the substrate is an insulating layer + electrode layer. The form of the substrate here can also be set according to actual application requirements, and the present invention does not specifically limit this.

[0124] like Figure 3 As shown, as an optional implementation, the substrate can be set as the fourth terminal 4, and the method for preparing the semiconductor material 5 can be mechanical stripping, chemical vapor deposition, chemical vapor transport, physical vapor deposition, atomic layer deposition, molecular beam epitaxy, etc.

[0125] The semiconductor material 5 can be barium titanate, lead titanate, potassium niobate, titanium titanate, graphene, boron nitride, bismuth sulfide, bismuth selenide, molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, indium sulfide, indium selenide, tin sulfide or tin selenide, etc.

[0126] Step 132: Expose and write the electrode pattern onto the photoresist, and develop it in a developer for a preset time to obtain a photoresist layer with the electrode pattern, and prepare the first terminal 1 and the second terminal 2.

[0127] like Figure 3 As shown, the metal top electrode is a first terminal 1 and a second terminal 2. The metal of the top electrode can be tungsten, titanium, aluminum, copper, aluminum-copper alloy, platinum, gold, silver, iron, chromium, nickel, tantalum, titanium nitride or tantalum nitride.

[0128] The top electrode can be prepared by magnetron sputtering, thermal evaporation, electron beam evaporation and other methods.

[0129] Step 133: remove the glue and peel off the electrodes to obtain the patterned first terminal 1 and the second terminal 2.

[0130] The glue can be removed by acetone, developer, or isopropyl alcohol.

[0131] It should be noted that the corresponding terminology definitions and various related contents about the four-terminal structure memory in this embodiment are consistent with the contents in the aforementioned embodiment of a four-terminal structure memory, and will not be repeated here.

[0132] Through the above embodiments, the present invention provides a four-terminal structure memory, memory array and memory preparation method. Compared with the prior art, the four-terminal structure memory provided by the present invention can realize freely switchable binary digital storage function and multi-value analog resistive switching behavior in a single device. Compared with the prior art, the four-terminal structure memory provided by the present invention realizes artificial synaptic behavior through multi-value analog resistive switching behavior. And an artificial neural network is constructed using artificial synaptic behavior.

[0133] Compared with the prior art, the memory of the four-terminal structure provided by the present invention constructs a reconfigurable logic state through multi-valued simulated resistive switching behavior.

[0134] Specifically, the present invention combines a vertically structured resistive memory with a laterally structured ferroelectric memory. The prepared device has a simple structure and can freely switch between binary digital storage functions and multi-value analog resistive behaviors. Relying on resistive memory devices and artificial synaptic behaviors based on ferroelectric memories, the design implements multifunctional storage applications, reconfigurable logic functions, artificial neural network calculations, and repeatedly switchable digital / analog storage behaviors. The four-terminal semiconductor device of the present invention can freely select digital and analog resistive switching behaviors, which gives it broad prospects in applications such as hybrid storage modes and new computing architectures. It provides a new idea for simplifying the structure and diversifying functions of storage-computing devices.

[0135] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0136] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A memory with a four-terminal structure, characterized in that: The memory comprises: substrate; A resistive memory and a ferroelectric memory are formed on the substrate; the resistive memory is a vertical structure, and the ferroelectric memory is a lateral structure; The resistive memory and the ferroelectric memory are integrated into a single device; the memory includes four terminals.

2. The four-terminal memory according to claim 1, characterized in that: The memory includes a first terminal, a second terminal, a third terminal and a semiconductor material; The first terminal is formed on a semiconductor material, and the semiconductor material is formed between the third terminal and the first terminal.

3. The four-terminal memory according to claim 2, characterized in that: The substrate serves as a fourth terminal, the third terminal is formed on the fourth terminal, the semiconductor material is formed between the second terminal and the fourth terminal, and a portion of the semiconductor material is located on the fourth terminal.

4. The four-terminal memory according to claim 3, characterized in that: The resistive memory at least comprises: a first terminal, a first semiconductor material and a third terminal; the first terminal is formed on the first semiconductor material; the first semiconductor material is located between the first terminal and the third terminal; The ferroelectric memory at least includes: a first terminal, a second terminal and a second semiconductor material; the first terminal and the second terminal are formed on the second semiconductor material.

5. The four-terminal memory according to claim 3, characterized in that: The memory has a binary non-volatile resistive switching behavior, and the memory realizes switching of multi-valued conductivity states; When the memory realizes artificial synaptic behavior through the multi-valued conductance state of the ferroelectric memory, the memory activates a first terminal and a second terminal, any one of the first terminal and the second terminal is a drain, the other terminal is a source, one end is a synaptic back end, and the other end is a synaptic front end; Alternatively, the first terminal, the second terminal and the fourth terminal are activated, the fourth terminal acts as a synaptic front end, receives electrical pulse stimulation, and is an excitation end, and any one of the first terminal and the second terminal can be a synaptic back end; Alternatively, the first terminal, the second terminal and the fourth terminal are activated to form a back-gate field effect transistor structure with a ferroelectric semiconductor channel, any one of the first terminal and the second terminal is a synaptic front end, the other terminal is a synaptic back end, and the fourth terminal is a modulation end.

6. The memory of the four-terminal structure according to claim 5, characterized in that: When the memory uses the resistance change of the resistive memory to control the activation or shutdown of the artificial synaptic behavior, a voltage dividing resistor is connected between the first terminal and the power supply voltage; the second terminal and the third terminal are grounded; and the fourth terminal is a modulation terminal applied to the second semiconductor material; The voltage at the first terminal is a common input voltage of the storage and synaptic parts. When the resistive random access memory is in a high-resistance state, the voltage at the first terminal is greater than a preset threshold voltage, and the artificial synapse works normally. When the resistive memory enters a low resistance state, the voltage at the first terminal is less than a preset threshold voltage, and the artificial synapse is closed.

7. The four-terminal memory according to claim 5, characterized in that: When the ferroelectric memory in the memory constructs a reconfigurable logic state, the fourth terminal serves as a control terminal and a first input terminal for reconstructing the logic function using a pre-written signal, the first terminal is defined as a second input terminal, and the current at the second terminal serves as an output, and the reconfigurable logic function is realized by controlling the pre-written signal of the fourth terminal, and the switching with the logic gate function or the logic gate function is realized; The first terminal is a first input terminal, the second terminal is a second input terminal, the current at the second terminal is used as an output, the third terminal is a control terminal, and the fourth terminal serves as a control terminal and an input terminal for reconstructing a logic function using a pre-written signal; the logic input corresponds to a voltage input of the first terminal and the fourth terminal, and the logic output is a current value at the second terminal.

8. A memory array with a four-terminal structure, characterized in that: The memory array is composed of a plurality of memories of a four-terminal structure as claimed in claim 1.

9. A method for preparing a memory with a four-terminal structure, characterized in that: Methods include: providing a substrate; forming a resistive memory on the substrate, and, forming a ferroelectric memory on the substrate; The resistive memory is a vertical structure, and the ferroelectric memory is a lateral structure; the resistive memory and the ferroelectric memory are integrated in a single device; and the memory includes four terminals.

10. The method for preparing a memory with a four-terminal structure according to claim 9, characterized in that: The memory includes a first terminal, a second terminal, a third terminal and a semiconductor material; The forming of a resistive random access memory on the substrate specifically includes: preparing a third terminal on the substrate; preparing a semiconductor material, and transferring the semiconductor material to the substrate; Expose and write the electrode pattern onto the photoresist, and develop it in a developer for a preset time to obtain a photoresist layer with the electrode pattern, and prepare a first terminal; The electrode is stripped and the patterned first terminal is obtained; the ferroelectric memory is formed on the substrate, specifically comprising: preparing a semiconductor material, and transferring the semiconductor material to the substrate; Expose and write the electrode pattern onto the photoresist, and develop it in a developer for a preset time to obtain a photoresist layer with the electrode pattern, and prepare a first terminal and a second terminal; The electrodes are stripped and the first and second patterned terminals are obtained.

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