SiCSBD diode capable of reducing electric leakage and preparation method thereof

Abstract

The invention discloses a SiC SBD diode capable of reducing electric leakage and a preparation method, and relates to the technical field of semiconductors. In the SiC SBD diode, a Poly electrode and an N-drift layer are insulated by using an oxide layer to form a planar capacitor, and the two sides of the Poly electrode repel surrounding electrons during reverse blocking, so that a depletion region of the upper N-drift layer is expanded, the electric field intensity at a Schottky interface is reduced, the Schottky effect is weakened, and electric leakage is reduced. And meanwhile, the P-type masking layer extends into the N-drift layer by utilizing an etched groove and is connected with the positive electrode at an equal potential, and when the device is reversely blocked, an electric field peak value moves downwards from the surface and is far away from a Schottky interface, so that electric leakage is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SiC SBD diode with reduced leakage and a preparation method thereof. Background Art

[0002] SiC can obtain a high-voltage diode of more than 600V with the SBD (Schottky barrier diode) structure of a high-frequency device structure. If SiC-SBD is used to replace the current mainstream product fast PN junction diode (FRD: fast recovery diode), the recovery loss can be significantly reduced, which is conducive to the high efficiency of the power supply, and the miniaturization of passive devices such as inductors can be achieved through high-frequency drive, and noise can be reduced. Therefore, it is widely used in power factor correction circuits (PFC circuits) and rectifier bridge circuits such as power conditioners in air conditioners, power supplies, photovoltaic power generation systems, and electric vehicle fast chargers.

[0003] The HTRB (High Temperature Reverse Bias) experiment is a reliability project that must be evaluated for SiC SBD diodes. In this experiment, SiC SBDs with high native leakage often fail first due to heat accumulation. The reason is that at 175°C and 80% VR bias voltage, the SiC SBD leakage will reach tens or hundreds of uA. During the test, the chip will generate heat due to the leakage current. If the heat cannot be dissipated quickly, the chip junction temperature will exceed 175°C, causing the SiC SBD failure rate to increase significantly. Therefore, it is particularly important to reduce the SiC SBD native leakage. Summary of the invention

[0004] In view of the above problems, the present invention proposes a SiC SBD diode with reduced leakage current and a preparation method thereof, which reduces the electric field strength and leakage current at the interface between the substrate and the substrate.

[0005] The technical solution of the present invention is: A method for preparing a SiC SBD diode with reduced leakage current comprises the following steps: S100, in N + The N-type buffer layer and N-type - drift layer; S200, in N - Etching a plurality of groove regions on the top surface of the drift layer; S300, forming a P-type shielding layer wrapped around the bottom surface and corners of the trench region by ion implantation at the bottom of the trench region, and performing high-temperature ion activation after the implantation is completed; S400, forming an oxide layer inside the trench region, and depositing polysilicon in the oxide layer to form a Poly layer, and leading out a Poly electrode; S500, in N -The drift layer, the oxide layer and the top surface of the Poly layer are formed into Schottky metal by sputtering; S600, a positive metal is formed on the top surface of the Schottky metal by sputtering to lead out a positive electrode; S700, N + The back side of the substrate layer is thinned, and a back side metal is formed to lead out a negative electrode.

[0006] Specifically, in step S100, N + The substrate layer is doped with N ions with a doping concentration of 1e 19 cm -2 ±10%.

[0007] Specifically, in step S100, the N-type buffer layer is doped with N ions at a doping concentration of 1e 18 cm -2 ±10%.

[0008] Specifically, in step S100, N - The drift layer is doped with N ions with a doping concentration of 8e 15 -1e 16 cm -2 , thickness is 5-15um.

[0009] Specifically, in step S200, the depth of the groove region is 0.8-1.2 um, and the spacing is 2.5-3 um.

[0010] Specifically, in step S300, the P-type shielding layer is doped with Al ions at a doping concentration of 1e 18 -1e 19 cm -2 , the doping depth is 0.5-1um, and the P-type masking layer completely wraps the bottom corner of the trench area.

[0011] Specifically, in step S400, the oxide layer is connected to two side walls of the trench region, the oxide layer growth temperature is 1250-1350° C., and the growth thickness is 40-60 nm.

[0012] Specifically, in step S500, the bottom of the Poly layer contacts the P-type masking layer, the side contacts the oxide layer, and the top contacts the N-type masking layer. - The drift layer surface is flush.

[0013] Specifically, in step S700, the back metal is laser annealed after Ni metal sputtering, and the laser energy is 2-4 mJ / cm 2 .

[0014] A SiC SBD diode with reduced leakage current includes a back metal, an N + Substrate layer, N-type buffer layer, N - Drift layer, Schottky metal, and front metal; The N - The drift layer is equipped with: Poly layer, with a plurality of, respectively spaced from the N - The top surface of the drift layer extends downward; Oxide layer, with a plurality of, respectively located between the Poly layer and N - Between the drift layers; the top surface of the oxide layer is flush with the top surface of the Poly layer, and the bottom surface of the oxide layer is flush with the bottom surface of the Poly layer; A P-type shielding layer is arranged at the bottom and corners of the oxide layer and the Poly layer, and the bottom surface of the P-type shielding layer is adjacent to the N - A gap is provided on the bottom surface of the drift layer.

[0015] Specifically, the Schottky metal is respectively - The drift layer, oxide layer and Poly layer are connected.

[0016] Beneficial effects of the present invention: Compared with the traditional SiC JBS diode, this case uses an oxide layer to separate the Poly electrode and N - The drift layer is insulated to form a planar capacitor. When reverse blocking occurs, the two sides of the Poly electrode will repel the surrounding electrons, making the upper N - The doping concentration of the drift layer is reduced, the depletion region is better expanded, the electric field strength at the Schottky interface is reduced, the Schottky effect is weakened, and leakage is reduced. At the same time, the P-type masking layer is extended from the surface to the N-type by using the groove. - The drift layer is connected to the positive electrode at the same potential. When the device is reverse blocked, N - The electric field distribution in the drift layer is changed, and the electric field peak moves downward from the surface, away from the Schottky interface, thereby reducing leakage. Therefore, lower reverse leakage and higher withstand voltage can be achieved in the same doped epitaxial layer.

[0017] There is often a forward current shock during the use of the diode. At this time, the Poly electrode can also be used as a leakage path. The forward current can not only flow out from the Schottky junction, but also flow into the P-type shielding layer through the Poly electrode, and then flow out from the P-type shielding layer. The current carrying capacity of the PN junction diode is greater than that of the Schottky diode, which greatly improves the forward surge capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural schematic diagram of step S100 of the present invention; Figure 2 It is a structural schematic diagram of step S200 of the present invention; Figure 3 It is a structural schematic diagram of step S300 of the present invention; Figure 4is a structural schematic diagram of step S400 of the present invention; Figure 5 is a schematic structural diagram of step S500 of the present invention; Figure 6 is a schematic structural diagram of step S600 of the present invention; Figure 7 is a schematic structural diagram of step S700 of the present invention; Figure 8 is a structural schematic diagram of step S800 of the present invention; Fig. 9 is a structural schematic diagram of step S900 of the present invention; In the figure, 1 is N + Substrate layer, 2 is N-type buffer layer, 3 is N - Drift layer, 4 is the trench region, 5 is the P-type masking layer, 6 is the oxide layer, 7 is the Poly layer, 8 is the Schottky metal, 9 is the front metal, and 10 is the back metal. DETAILED DESCRIPTION

[0019] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0020] A method for preparing a SiC SBD diode with reduced leakage current comprises the following steps: S100, refer to Figure 1 As shown, in N + An N-type buffer layer 2 is grown on the substrate layer 1; N in step S100 + Substrate layer 1 is doped with N ions, with a thickness of 360-400um and a doping concentration of 1e 19 cm -2 ±10%; The N-type buffer layer 2 is also doped with N ions, with a thickness of 0.8-1.2um and a doping concentration of 1e 18 cm -2 ±10%.

[0021] S200, refer to Figure 2 As shown, a layer of N is epitaxially grown on the N-type buffer layer 2. - Drift layer 3; In step S200, N - Drift layer 3 is doped with N ions at a doping concentration of 8e 15 -1e 16 cm -2 , thickness is 5-15um.

[0022] S300, refer to Figure 3 As shown, in N- The surface of the drift layer 3 is dry-etched to form a plurality of groove regions 4 extending downward; In step S300 , the depth of the trench region 4 is 0.8-1.2 um, and the spacing is 2.5-3 um.

[0023] S400, refer to Figure 4 As shown, a P-type masking layer 5 is formed at the bottom of the trench region 4 by ion implantation, and high-temperature ion activation is performed after the implantation is completed; The P-type shielding layer 5 in step S400 is doped with Al ions at a doping concentration of 1e 18 -1e 19 cm -2 , the doping depth is 0.5-1um, and the P-type masking layer 5 completely wraps the two right angles at the bottom of the trench area 4.

[0024] S500, refer to Figure 5 As shown, an oxide layer 6 is formed on the side wall of the trench region 4 by dry oxygen thermal oxidation and dry etching; The oxide layer 6 in step S500 is connected to the side wall of the trench region 4. The growth temperature of the oxide layer 6 is 1250-1350° C., and the growth thickness is 40-60 nm. It needs to be annealed in a NO atmosphere at a temperature of 1250° C. for 1 hour to improve the density of the gate oxide layer 6 and reduce defects.

[0025] S600, refer to Figure 6 As shown, polysilicon is deposited in the trench region 4 to form a Poly layer 7, and a Poly electrode is led out; In step S600, the bottom of the Poly layer 7 is in contact with the P-type masking layer 5, the two sides are in contact with the oxide layer 6, and the top is in contact with the N-type masking layer 5. - The surface of the drift layer 3 is flush.

[0026] S700, reference Figure 7 As shown, in N - The top surfaces of the drift layer 3, the oxide layer 6 and the Poly layer 7 are formed into a Schottky metal 8 by sputtering Ti or other metals; S800, reference Figure 8 As shown, a front metal 9 is formed on the top surface of the Schottky metal 8 by sputtering AlCu or other metals to lead out a positive electrode.

[0027] S900, refer to Fig. 9 As shown, in N + The back side of the substrate layer 1 is thinned to reduce N + The thickness of the substrate layer 1 is 2000 mm, and then Ni metal is sputtered and Ti / Ni / Ag metal is evaporated to form the back metal 10 to lead out the negative electrode.

[0028] In step S900, the back metal 10 needs to be laser annealed after Ni metal sputtering, and the laser energy is 2-4 mJ / cm 2 ; Later, multiple layers of metals such as Ti / Ni / Ag are evaporated, or other metals can be used, with a total thickness of 1.4-2um.

[0029] A SiC SBD diode with reduced leakage current includes a back metal 10, an N + Substrate layer 1, N-type buffer layer 2, N - Drift layer 3, Schottky metal 8 and front metal 9; The N - The drift layer 3 is provided with: Poly layer 7, with a plurality of, respectively spaced from the N - The top surface of the drift layer 3 extends downward; The Poly layer 7 extends downward to a depth of 0.5-1um and the spacing between adjacent Poly layers 7 is 2.5-3um to ensure the shielding effect of the Schottky junctions on both sides during reverse blocking and reduce leakage.

[0030] The oxide layer 6 is provided with a plurality of layers, which are respectively located between the Poly layer 7 and the N - Between the drift layers 3; the top surface of the oxide layer 6 is flush with the top surface of the Poly layer 7, and the bottom surface of the oxide layer 6 is flush with the bottom surface of the Poly layer 7; The P-type masking layer 5 is arranged on the bottom surface and corners of the oxide layer 6 and the Poly layer 7 .

[0031] The Schottky metal 8 is respectively - The drift layer 3 , the oxide layer 6 and the Poly layer 7 are connected.

[0032] The front metal 9 covers the Schottky metal 8 .

[0033] The present invention improves the reverse leakage of SiC SBD diodes. Compared with the conventional SiC JBS diode, the present invention uses an oxide layer 6 to connect the Poly layer (electrode) 7 with the N - The drift layer 3 is insulated to form a planar capacitor. When reverse blocking occurs, the two sides of the Poly electrode will repel the surrounding electrons, making the upper N - The doping concentration of the drift layer 3 is reduced, the depletion region is better expanded, the electric field strength at the Schottky interface is reduced, the Schottky effect is weakened, and the leakage is reduced. At the same time, the P-type shielding layer 5 is extended from the surface to the N - The drift layer 3 is connected to the positive electrode at the same potential. When the device is reverse blocked, N -The electric field distribution in the drift layer 3 is changed, and the electric field peak moves downward from the surface, away from the Schottky interface, thereby reducing leakage. Therefore, lower reverse leakage and higher withstand voltage can be achieved in the epitaxial layer with the same doping.

[0034] The present invention also improves the forward surge capability of the SiC SBD diode. During the use of the SiC SBD diode, there is often a forward current impact. At this time, the Poly electrode can also be used as a leakage path. The forward current can not only flow out from the Schottky junction, but also flow into the P-type shielding layer 5 through the Poly electrode, and then flow out from the P-type shielding layer 5. The PN junction diode is turned on, which greatly improves the forward surge capability of the device.

Claims

1. A method for preparing a SiC SBD diode with reduced leakage, characterized in that: The steps include: S100, in N + An N-type buffer layer (2) and an N-type buffer layer (2) are sequentially grown on the substrate layer (1). - Drift layer (3); S200, in N - A plurality of groove regions (4) are etched on the top surface of the drift layer (3); S300, forming a P-type shielding layer (5) wrapped around the bottom surface and corners of the trench region (4) by ion implantation at the bottom of the trench region (4), and performing high-temperature ion activation after the implantation is completed; S400, forming an oxide layer (6) inside the trench region (4), depositing polysilicon inside the oxide layer (6) to form a Poly layer (7), and leading out a Poly electrode; S500, in N - The drift layer (3), the oxide layer (6) and the top surface of the Poly layer (7) are formed into a Schottky metal (8) by sputtering; S600, forming a front metal (9) on the top surface of the Schottky metal (8) by sputtering, and leading out a positive electrode; S700, N + The back side of the substrate layer (1) is thinned and a back side metal (10) is formed to lead out a negative electrode.

2. A method for preparing a SiC SBD diode with reduced leakage according to claim 1, characterized in that: In step S100, N + The substrate layer (1) is doped with N ions at a doping concentration of 1e 19 cm -2 ±10%.

3. The method for preparing a SiC SBD diode with reduced leakage according to claim 1, characterized in that: In step S100, the N-type buffer layer (2) is doped with N ions at a doping concentration of 1e 18 cm -2 ±10%.

4. The method for preparing a SiC SBD diode with reduced leakage according to claim 1, characterized in that: In step S100, N - The drift layer (3) is doped with N ions at a doping concentration of 8e 15 -1e 16 cm -2 , thickness is 5-15um.

5. The method for preparing a SiC SBD diode with reduced leakage according to claim 1, characterized in that: In step S200, the depth of the groove region (4) is 0.8-1.2 um, and the spacing is 2.5-3 um.

6. The method for preparing a SiC SBD diode with reduced leakage according to claim 1, characterized in that: In step S300, the P-type shielding layer (5) is doped with Al ions at a doping concentration of 1e 18 -1e 19 cm -2 , the doping depth is 0.5-1um, and the P-type masking layer (5) completely wraps the bottom corner of the trench region (4).

7. The method for preparing a SiC SBD diode with reduced leakage according to claim 1, characterized in that: In step S400, the oxide layer (6) is connected to two side walls of the trench region (4), the oxide layer (6) is grown at a temperature of 1250-1350° C., and the growth thickness is 40-60 nm.

8. The method for preparing a SiC SBD diode with reduced leakage according to claim 1, characterized in that: In step S500, the bottom of the Poly layer (7) is in contact with the P-type masking layer (5), the side is in contact with the oxide layer (6), and the top is in contact with the N - The drift layer (3) has a flat surface.

9. The method for preparing a SiC SBD diode with reduced leakage according to claim 1, characterized in that: In step S700, the back metal (10) is laser annealed after Ni metal sputtering, and the laser energy is 2-4 mJ / cm 2 .

10. A SiC SBD diode with reduced leakage, prepared by the method for preparing a SiC SBD diode with reduced leakage according to any one of claims 1 to 9, characterized in that: The back metal (10), N + Substrate layer (1), N-type buffer layer (2), N - Drift layer (3), Schottky metal (8) and front metal (9); The N - The drift layer (3) is provided with: The poly layer (7) includes a plurality of layers, each spaced apart from the N - The top surface of the drift layer (3) extends downward; The oxide layer (6) is provided with a plurality of layers, which are respectively located between the Poly layer (7) and the N - Between the drift layers (3); the top surface of the oxide layer (6) is flush with the top surface of the Poly layer (7), and the bottom surface of the oxide layer (6) is flush with the bottom surface of the Poly layer (7); The P-type shielding layer (5) is arranged on the bottom surface and corners of the oxide layer (6) and the Poly layer (7), and the bottom surface of the P-type shielding layer (5) is adjacent to the N - A gap is provided on the bottom surface of the drift layer (3).

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