Diamond ring gate field effect transistor and preparation method thereof

Abstract

The invention discloses a diamond ring gate field effect transistor and a preparation method thereof, and relates to the technical field of semiconductor devices. The ring gate structure is suspended on the diamond substrate layer and comprises a nanowire, a gate electrode and a ring gate electrode coated by the gate electrode; the nanowire sequentially comprises a diamond core, a diamond terminal surface, a dielectric layer and a ring gate electrode from inside to outside, vertically penetrates through the gate electrode and is completely wrapped by the gate electrode; the source electrode and the drain electrode are located on the two sides of the gate electrode respectively, and ohmic contact is formed between the source electrode and the surface of the diamond terminal; two-dimensional hole gas is formed on the surface of the diamond terminal and the interface of the dielectric layer; according to the diamond ring gate field effect transistor and the preparation method thereof, the electrostatic problem caused by feature size reduction can be effectively relieved, meanwhile, the high performance of the transistor is ensured, and a solid foundation is laid for development of miniature devices in the future.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a diamond gate-all-around field effect transistor and a preparation method thereof. Background Art

[0002] As an ultra-wide bandgap semiconductor material, diamond has shown great potential in the field of high-temperature, high-frequency, and high-power electronic devices due to its unique physical and chemical properties. Its indirect bandgap width at room temperature is 5.47eV, which gives it a significant advantage in the design of electronic devices, especially in situations that can withstand high voltages and high power densities. Diamond's high breakdown electric field, high power capacity, and extremely high thermal conductivity provide electronic devices with better heat dissipation performance, thereby improving the stability and reliability of the devices. Diamond's high thermal conductivity is one of its most striking properties. Its thermal conductivity is about five times that of copper, which makes it perform well in applications with extremely high heat dissipation requirements. For example, in high-power electronic devices, diamond can quickly dissipate heat and effectively prevent the device from overheating and failure. In addition, diamond's high hardness and chemical stability keep its performance stable in harsh environments, which is of great value in industrial and military applications.

[0003] However, existing diamond field-effect transistors face many challenges in practical applications. First, due to the high activation energy of doped diamond field-effect transistors, the carrier concentration is low, which limits its performance improvement in microwave power devices. Secondly, hydrogen-terminated diamond field-effect transistors form carbon-hydrogen chemical bonds by treating the diamond surface with hydrogen plasma. Although this has promoted the development of diamond devices, photoresist contamination, excessive plasma energy, or deposition of oxygen-containing atmosphere media must be avoided during the process, which seriously limits the selection of gate dielectric materials and further optimization of device performance. In addition, as the size of transistors continues to shrink, traditional diamond field-effect transistors also face many problems caused by short channel effects (SCE). These problems include increased leakage current, decreased performance, and weakened gate control capabilities, resulting in limited device performance improvement. At the same time, further size miniaturization also causes electrostatic problems, which puts higher technical requirements on the overall performance of transistors. Therefore, the shortcomings of diamond field-effect transistors in doping activation energy, process adaptability, and size scaling are addressed. Summary of the invention

[0004] The object of the present invention is to provide a diamond ring-gate field effect transistor and a preparation method thereof, so as to solve the problems that the prior art diamond field effect transistor has deficiencies in doping activation energy, process adaptability and size scaling.

[0005] To achieve the above object, the present invention provides the following technical solution: a diamond ring gate field effect transistor, comprising:

[0006] Diamond substrate layer;

[0007] A ring-gate structure suspended above the diamond substrate layer, the ring-gate structure comprising a nanowire, a gate electrode and a ring-gate electrode coated thereon;

[0008] The nanowire includes a diamond core, a diamond terminal surface, a dielectric layer and a ring gate electrode from the inside to the outside, vertically passes through the gate electrode and is fully wrapped by it;

[0009] A source electrode and a drain electrode, the source electrode and the drain electrode are respectively located on both sides of the gate electrode and form an ohmic contact with the surface of the diamond terminal;

[0010] The interface between the diamond terminal surface and the dielectric layer forms a two-dimensional void.

[0011] Preferably, the thickness of the gate electrode is 50nm-500nm.

[0012] Preferably, the diamond terminal surface is hydrogen-terminated or silicon-terminated.

[0013] Preferably, the thickness of the dielectric layer is 3nm-50nm.

[0014] Preferably, the thickness of the ring gate electrode is 10nm-100nm.

[0015] Preferably, the thickness of the source electrode is 50nm-500nm.

[0016] Preferably, the cross-sectional shape of the nanowire is polygonal, circular, elliptical or irregularly circular.

[0017] A method for preparing a diamond-gate-all-around field effect transistor, using the diamond-gate-all-around field effect transistor, the method comprising:

[0018] S1, select a diamond substrate layer;

[0019] S2, forming a diamond core in the shape of a nanowire on the surface of the diamond substrate layer by photolithography, specifically comprising: coating a photoresist on the surface of the diamond substrate layer to form a mask; etching by a dry etching process to form a diamond core of the nanowire; removing the mask to retain the nanowire structure;

[0020] S3, pre-treating the surface of the diamond core and performing hydrogen termination or silicon termination treatment to form a two-dimensional hole gas (2DHG) terminal surface on the surface of the diamond core;

[0021] S4, depositing dielectric material on the terminal surface of the nanowire in all directions to form a dielectric layer, wherein the thickness of the dielectric layer is in the range of 3 nm to 50 nm;

[0022] S5, depositing metal material in all directions around the dielectric layer to form a ring gate electrode;

[0023] S6. forming a gate electrode on the diamond substrate layer by photolithography, so that the nanowire vertically passes through the gate electrode and is fully wrapped by it;

[0024] S7. Remove part of the dielectric layer, deposit the source electrode and the drain electrode on both sides of the gate electrode by photolithography to form an ohmic contact with the terminal surface of the nanowire.

[0025] It can be seen from the above technical solution that the present invention has the following beneficial effects:

[0026] The diamond ring-gate field effect transistor and its preparation method realize a conductive path with high carrier concentration by forming a two-dimensional hole gas (2DHG) on the surface of diamond nanowires, thus overcoming the problem of low carrier concentration caused by excessive activation energy of conventional doped diamond field effect transistors. This structure improves the performance of the device in high-frequency and high-power applications. The ring-gate structure is used to fully cover the nanowires, effectively alleviating the short channel effect (SCE) caused by the size reduction in conventional field effect transistors, while enhancing the gate's control over carriers, thereby improving the switching ratio and reliability of the transistor. The source electrode and the drain electrode form an ohmic contact with the surface of the diamond terminal, ensuring a low-impedance current channel for the device, optimizing the electron migration efficiency, and significantly improving the working performance and stability of the device. The diamond material itself has extremely high thermal conductivity. The heat dissipation path is further optimized by a reasonably designed ring-gate structure and the cross-sectional shape of the nanowires, thereby improving the heat dissipation efficiency and reliability of the device under high power density conditions. Standard photolithography and dry etching processes are used to ensure precise control of the shape and size of the nanowires while having high process repeatability. In addition, through the process design of omnidirectional deposition of dielectric layers and ring-gate electrodes, photoresist contamination and process limitations of high-energy plasma are avoided, thereby expanding the selection range of gate dielectric materials and improving device performance. In the scenario of further miniaturization, the ring-gate structure of the present invention can effectively alleviate the electrostatic problems caused by reducing the feature size, while ensuring the high performance of transistors, laying a solid foundation for the development of future miniaturized devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the overall structure of the present invention;

[0028] Figure 2 It is a top view of the overall structure of the present invention;

[0029] Figure 3 The figure is a flow chart of the method of the present invention.

[0030] In the figure: 1. Diamond substrate layer; 2. Ring gate structure; 21. Source electrode; 22. Drain electrode; 23. Gate electrode; 3. Nanowire; 31. Diamond terminal surface; 32. Dielectric layer; 33. Ring gate electrode; 34. Diamond core. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] like Figure 1 and Figure 2 As shown, the present invention provides a technical solution: a diamond ring-gate field effect transistor, comprising a diamond substrate layer 1; a ring-gate structure 2 suspended above the diamond substrate layer 1, the ring-gate structure 2 comprising a nanowire 3, a gate electrode 23 and a ring-gate electrode 33 coated thereon; the nanowire 3 comprises a diamond core 34, a diamond terminal surface 31, a dielectric layer 32 and a ring-gate electrode 33 from the inside to the outside, vertically passing through the gate electrode 23 and being fully wrapped therein; a source electrode 21 and a drain electrode 22, the source electrode 21 and the drain electrode 22 are respectively located on both sides of the gate electrode 23, and form ohmic contact with the diamond terminal surface 31; a two-dimensional hole gas is formed at the interface between the diamond terminal surface 31 and the dielectric layer 32.

[0033] The diamond substrate layer 1 provides high thermal conductivity and excellent insulation performance for the rectifier transistor, ensuring the high-frequency operation stability of the device. The ring gate structure 2 suspended above the diamond substrate layer 1 realizes precise electric field control of the transistor channel through its unique nanowire structure and ring gate design. The diamond core inside the nanowire 3 provides high conductivity and structural support, and its surface diamond terminal surface 31 forms a two-dimensional hole gas through the interface with the dielectric layer 32 to form the channel of the transistor. The gate electrode 23 is coated on the periphery of the nanowire 3, and the density of the two-dimensional hole gas is affected by regulating the gate voltage, thereby realizing the switching of the channel on and off. The source electrode 21 and the drain electrode 22 form ohmic contacts with the diamond terminal surface 31 respectively to ensure efficient transmission of electrons in the channel. Through the formation of two-dimensional hole gas, the carrier mobility of the channel is significantly improved, and efficient electron transmission is achieved. The diamond substrate layer 1 provides high thermal conductivity, significantly reduces heat accumulation during high-frequency operation, and ensures the stability of the device. The ring gate structure 2 improves the uniformity and control accuracy of the channel electric field and reduces the possibility of electric field runaway by fully wrapping the gate electrode 23. The vertical structure design of the nanowire 3 reduces the lateral size of the device, laying the foundation for achieving high integration and miniaturization.

[0034] In one possible implementation, the material of the gate electrode 23 is one or more of aluminum (Al), titanium (Ti), nickel (Ni), gold (Au), tungsten (W), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or cobalt (Co), with a thickness of 50-500nm. The gate electrode 23 adopts the above-mentioned high-performance conductive material, and its excellent conductivity and thermal stability ensure the effective regulation of the electric field. By selecting a single metal such as aluminum, titanium, nickel or a combination of materials, the physical and chemical properties of the gate electrode 23 can be optimized to adapt to different working environments or requirements. The thickness of the gate electrode ranges from 50-500nm, which can be optimized on the basis of taking into account resistance and manufacturing process: a smaller thickness reduces the amount of metal used and reduces the lateral size of the transistor. A larger thickness enhances the mechanical strength and durability of the electrode to avoid damage caused by thermal effects or mechanical stress. The high conductivity of the selected material significantly reduces the resistance of the gate electrode and improves the response speed and control accuracy of the transistor. A variety of materials are available, so that the design of the gate electrode can be optimized for specific application scenarios (such as high temperature, high frequency or harsh chemical environment). The good processability and moderate thickness range of the materials make it easy to prepare gate electrodes using conventional processes such as evaporation and sputtering. For example, materials such as tungsten (W) and titanium nitride (TiN) can provide excellent thermal stability and are suitable for use in high-power and high-temperature environments. For example, materials such as tantalum (Ta) and tantalum nitride (TaN) have good durability after thickness optimization, avoiding failure of the electrode layer due to mechanical fatigue.

[0035] In one possible embodiment, the root diamond terminal surface 31 is a hydrogen terminal or a silicon terminal. The treatment of the diamond terminal surface 31 is an important step to ensure the formation of two-dimensional hole gas. When hydrogen terminals are used, hydrogen atoms combine with carbon atoms on the diamond surface to form stable CH bonds, which significantly reduce the surface state density. At the same time, the band bending is induced by the surface electronegativity difference, which promotes the generation of two-dimensional hole gas. When silicon terminals are used, silicon atoms form C-Si bonds with the diamond surface, which not only stabilizes the surface structure, but also optimizes the density and distribution of channel carriers by adjusting the interface charge distribution. The selection of hydrogen terminals and silicon terminals can flexibly adjust device performance according to specific application requirements, such as improving carrier mobility or enhancing environmental adaptability. The diamond terminal surface using hydrogen terminals or silicon terminals has the following advantages: hydrogen terminals significantly reduce the surface scattering effect, ensuring that the two-dimensional hole gas has a higher mobility, thereby improving the conduction performance of the transistor. Compared with hydrogen terminals, silicon terminals are more stable to high temperatures and chemical environments, and are suitable for working in harsh environments. By choosing different terminal methods, the channel conductivity characteristics (such as carrier concentration and mobility) can be optimized to meet the needs of high-frequency, high-power or high-stability applications. Both hydrogen and silicon terminals can be achieved through mature processes such as plasma treatment or chemical modification. The preparation process is simple and easy to mass produce.

[0036] In a possible implementation, the material of the dielectric layer 32 is one or more combinations of aluminum oxide (Al2O3), molybdenum trioxide (MoO3), tungsten trioxide (WO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), rhenium dioxide (ReO2) or silicon nitride (SiNx), with a thickness of 3nm-50nm. The function of the dielectric layer 32 is to isolate the ring gate electrode 33 from the diamond terminal surface 31 in the nanowire 3, and optimize the interface characteristics to support the formation and stability of two-dimensional hole gas. The materials all have high dielectric constants (High-k), which can effectively enhance the gate control capability, reduce parasitic capacitance, and improve transistor performance. Aluminum oxide (Al2O3) and silicon nitride (SiNx) have excellent insulation properties and chemical stability, and are suitable for high-frequency and high-power scenarios. Molybdenum trioxide (MoO3) and tungsten trioxide (WO3) help to increase the charge density of the channel due to their high dielectric constants and electron affinity. Hafnium oxide (HfO2) and zirconium oxide (ZrO2) provide excellent dielectric properties and thermal stability, and are particularly suitable for applications in harsh environments. The thickness of the dielectric layer is controlled between 3-50nm, ensuring effective electric field coupling between the channel and the gate while meeting the insulation requirements. By adopting high dielectric constant materials, the control efficiency of the gate electrode on the two-dimensional hole gas in the channel is significantly improved, reducing leakage current. High dielectric materials and optimized thickness design effectively reduce parasitic capacitance, thereby reducing the power consumption of transistors, which is suitable for the development of high-efficiency electronic devices. The thermal stability and chemical corrosion resistance of materials such as hafnium oxide and zirconium oxide ensure long-term and reliable operation of transistors in high temperatures or harsh environments. The selectivity of multiple materials and their combinations enables the dielectric layer to adapt to different scenario requirements, such as high-frequency signal processing, high-power switching or miniaturized circuits. The above materials all support conventional deposition processes (such as ALD, CVD), are highly compatible with existing semiconductor manufacturing technologies, and are convenient for large-scale mass production.

[0037] In one possible implementation, the material of the ring gate electrode 33 is one or more of titanium nitride (TiN), platinum (Pt), aluminum (Al), nickel (Ni), gold (Au), tungsten (W), tantalum (Ta), tantalum nitride (TaN) or cobalt (Co), with a thickness of 10nm-100nm. As the core of the transistor control part, the material and thickness of the ring gate electrode 33 directly affect the electric field regulation capability, gate leakage current characteristics and device stability. The materials are all metals or metal compounds with high conductivity, corrosion resistance or high temperature stability, ensuring reliable performance under extreme conditions. Titanium nitride (TiN) and tantalum nitride (TaN) are suitable for high power and high temperature environments with their excellent thermal stability and chemical inertness; platinum (Pt) and gold (Au) provide high conductivity and low contact resistance, suitable for high frequency circuits; aluminum (Al), nickel (Ni), tungsten (W) and tantalum (Ta) have good processing performance and stability, and are suitable for a wide range of application scenarios. The thickness of the ring gate electrode ranges from 10nm to 100nm, ensuring that while meeting the conductivity and mechanical strength requirements, the device is not too large or performance degradation caused by uneven thickness is avoided. The ring gate electrode fully covers the gate structure, and precise electric field regulation is achieved through highly conductive materials to improve the switching performance of the transistor. The selected materials have good corrosion resistance and thermal stability, adapt to high temperature, high humidity or other harsh conditions, and extend the life of the device. The use of highly conductive materials such as gold (Au) or platinum (Pt) significantly reduces the resistance of the ring gate electrode and improves the response speed of the transistor. The above materials support common deposition processes such as sputtering and evaporation, and the thickness is easy to control, which is convenient for large-scale production. The optionality of different material combinations allows the ring gate electrode to be optimized according to the specific application scenario, adapting to a variety of device requirements from high frequency to high power.

[0038] In one possible embodiment, the material of the source electrode 21 and the drain electrode 22 is one or more of gold (Au), titanium (Ti), platinum (Pt), nickel (Ni) or tungsten (W), with a thickness of 50nm-500nm. The source electrode 21 and the drain electrode 22 directly form an ohmic contact with the diamond terminal surface 31, providing a key channel for carrier injection and extraction of the device. By selecting a metal material (such as Au, Pt, Ti, Ni or W) with high conductivity and good contact properties with the diamond material, the contact resistance can be effectively reduced and the carrier migration efficiency can be enhanced. In addition, the thickness of the source and drain electrodes ranges from 50 to 500nm to ensure a balance between performance optimization and mechanical stability: a smaller thickness (50-100nm) is suitable for miniaturized applications and reduces parasitic effects; a larger thickness (300-500nm) is suitable for high-power scenarios, improving heat dissipation and resistance to mechanical stress. The excellent properties of the metal materials are as follows: gold (Au) and platinum (Pt) provide excellent conductivity and chemical stability, suitable for high-frequency devices and high-humidity environments; titanium (Ti) and nickel (Ni) have good contact performance and mechanical strength, suitable for high-power, high-stress applications; tungsten (W) has a high melting point and high heat resistance, suitable for high-temperature environments.

[0039] The good interface properties between the selected metal material and the diamond surface significantly reduce the contact resistance, improve the carrier injection efficiency, and enhance the device performance. Appropriate electrode thickness design (such as 300nm-500nm) significantly improves the thermal conductivity and reduces the heat accumulation caused by high-power operation. The use of high-strength metals (such as W, Ti) combined with appropriate thickness can effectively improve the electrode's resistance to mechanical fatigue and extend the life of the device. Gold (Au) and platinum (Pt) significantly improve the high-frequency response capability of the device due to their low resistance and high conductivity, making them suitable for high-speed circuit applications. The above materials all support existing metal deposition processes (such as evaporation, sputtering, etc.), and the manufacturing process is mature and the cost is controllable.

[0040] In one possible embodiment, the cross-sectional shape of the nanowire 3 is polygonal or circular or elliptical or irregularly circular. The cross-sectional shape design of the nanowire 3 directly affects the electric field distribution, the carrier transmission path, and the interface characteristics with the surrounding materials. Specifically: providing a larger surface area, forming a stronger electric field coupling with the dielectric layer 32 and the ring gate electrode 33, suitable for enhancing the control of two-dimensional hole gas. The electric field distribution is more uniform, and the carrier transmission path is short and symmetrical, which helps to improve the mobility and signal response speed. Providing stronger electric field control ability in one-dimensional direction is suitable for the optimization needs of electron transmission in a specific direction. Through the irregularity of the surface shape, the influence of the surface state on the carrier can be increased to achieve special functions or performance adjustments, such as enhancing the scattering effect to adjust the mobility. Different cross-sectional shape designs can be flexibly adjusted according to actual application requirements to balance performance, cost and manufacturing difficulty. By adjusting the cross-sectional shape, the electric field distribution and carrier behavior can be optimized to meet the performance requirements of different scenarios, such as high frequency, high power or miniaturization applications. The polygonal and elliptical cross-sectional shapes improve the gate control capability and are particularly suitable for high-performance field effect transistors that require precise control. Circular or elliptical cross-sectional shapes are easier to achieve through conventional nanofabrication processes, reducing manufacturing difficulty and cost. Irregular circular cross-sections can be used to explore new functional devices, such as achieving special carrier transport or storage properties by designing surface states.

[0041] The specific structure includes from bottom to top: a diamond substrate layer 1, a ring gate structure 2; the ring gate structure 2 includes a gate electrode 23 and a nanowire 3; the nanowire 3 is a multilayer structure, including a diamond core 34, a diamond terminal surface 31, a dielectric layer 32, and a ring gate electrode 33 from the inside to the outside; the nanowire 3 is suspended above the diamond substrate layer 1 and vertically passes through the gate electrode 23, that is, the gate electrode 23 fully wraps the nanowire 3; the source electrode 21 and the drain electrode 22 are located on both sides of the gate electrode 23, and form ohmic contacts with the diamond terminal surface 31 respectively; near the interface between the diamond terminal surface 31 and the dielectric layer 32, a two-dimensional hole gas (2DHG) is formed as a conductive channel of the diamond ring gate field effect transistor, and is regulated by the gate electrode 23 and the ring gate electrode 33. The design of the ring gate electrode 33 makes the gate electrode 23 more effective in regulating the conductive channel, with higher transconductance, higher on-state current, and smaller off-state leakage. Among them, the material of the gate electrode 23 is Al, and the thickness is 300nm. The diamond termination surface 31 is a hydrogen termination. The dielectric layer 32 is made of Al2O3 with a thickness of 10 nm. The ring gate electrode 33 is made of TiN with a thickness of 50 nm. The source electrode or drain electrode is made of Au with a thickness of 200 nm.

[0042] It also includes a diamond substrate layer 1 and a ring gate structure 2; the ring gate structure 2 includes a source electrode 21, a drain electrode 22 and a gate electrode 23; the source electrode 21 and the drain electrode 22 constitute one or more nanowires 3, which are suspended above the diamond substrate layer 1 and vertically pass through the gate electrode 23, that is, the gate electrode 23 fully wraps the nanowire 3 composed of the source electrode 21 and the drain electrode 22; the nanowire 3 is a multi-layer structure, including a surface-modified terminal surface 31, a dielectric layer 32, and an electrode metal layer 33 from the inside to the outside; a two-dimensional hole gas 2DHG is formed inside the terminal surface 31; the electrode metal layer 33 is a metal layer of the source electrode 21 and the drain electrode 22; the nanowire etching depth is 50nm and the shape is a rhombus.

[0043] A method for preparing a diamond-ring-gate field effect transistor is also provided, using the diamond-ring-gate field effect transistor, the method comprising:

[0044] S1, select a diamond substrate layer 1;

[0045] S2, forming a diamond core 34 in the shape of a nanowire on the surface of the diamond substrate layer 1 by photolithography, specifically comprising: coating a photoresist on the surface of the diamond substrate layer 1 to form a mask; etching by a dry etching process to form a diamond core 34 of the nanowire; removing the mask to retain the nanowire structure;

[0046] S3, pre-treating the surface of the diamond core 34, and performing hydrogen termination or silicon termination treatment to form a terminal surface 31 of two-dimensional hole gas 2DHG on the surface of the diamond core;

[0047] S4, depositing dielectric material on the terminal surface 31 of the nanowire in all directions to form a dielectric layer 32, wherein the thickness of the dielectric layer is in the range of 3 nm to 50 nm;

[0048] S5, depositing metal material all around the periphery of the dielectric layer 32 to form a ring gate electrode 33;

[0049] S6, forming a gate electrode 23 on the diamond substrate layer 1 by photolithography, so that the nanowire 3 vertically passes through the gate electrode 23 and is fully wrapped by it;

[0050] S7 , removing part of the dielectric layer 32 , and depositing the source electrode 21 and the drain electrode 22 on both sides of the gate electrode 23 by photolithography to form ohmic contacts with the terminal surface 31 of the nanowire 3 .

[0051] This preparation method realizes the construction of high-performance diamond ring-gate field-effect transistors through precise process flow: Nanowire formation S2: Using photolithography and dry etching technology, the diamond core 34 of the nanowire is accurately constructed to ensure the controllability of its shape, size and arrangement, laying the foundation for subsequent processes. Terminal surface treatment S3: Through hydrogen terminal or silicon terminal treatment, the surface state of the diamond core is regulated to ensure the formation and stability of two-dimensional hole gas 2DHG. Ring-gate structure construction S4-S6: The dielectric layer and metal ring gate are uniformly deposited on the surface of the nanowire, and the all-round coating structure is used to achieve efficient control of the channel electric field and improve device performance. Electrode production S7: The source and drain electrodes are deposited through photolithography technology, and ohmic contact with the terminal surface is achieved to reduce contact resistance and ensure the efficiency of electron injection and extraction. Photolithography and dry etching technology are used to ensure the high precision of the size and shape of the nanowire and other structures, and improve the consistency and performance stability of the device. Through the comprehensive coating design of the ring-gate electrode, the precise control of the two-dimensional hole gas is achieved, which significantly improves the gate efficiency and transistor performance. The terminal surface treatment combined with optimized source and drain electrode materials and processes significantly reduces contact resistance and enhances carrier migration efficiency. This method is compatible with existing semiconductor manufacturing technology, suitable for large-scale production, and has scalability. Using diamond materials combined with optimized terminal treatment and electrode deposition processes, the device can operate stably in high-temperature, high-power environments.

[0052] Specifically, step 1: selecting a substrate, selecting a single crystal diamond substrate layer 1 prepared by a high temperature and high pressure (HPHT) method;

[0053] Step 2: Nanowire etching: After forming a rectangular shape on the surface of the diamond substrate layer 1 by steps such as coating, pre-baking, exposure, post-baking and development, the metal material Au is formed as a masking layer by electron beam evaporation with a thickness of 50-150nm, and ICP etching is used to form a groove with an etching depth of 100nm. Then the plasma bombardment angle is adjusted to etch out the inverted triangle shape of the nanowire 3, and finally the Au masking layer is removed by wet etching using a mixed solution of potassium iodide (KI) and iodine (I2).

[0054] Step 3: terminal surface treatment, pre-treatment of the nanowire 3, including screening, pickling and cleaning with acetone, anhydrous ethanol and deionized water, and then placing the sample in a MPCVD chamber in a hydrogen plasma atmosphere for 15 minutes, with a H2 flow rate of 600sccm, a power of 2kW, and a chamber temperature of 900°C, and then taking it out after cooling to room temperature in the hydrogen plasma atmosphere to form a terminal surface 31 with two-dimensional hole gas;

[0055] Step 4: dielectric layer deposition, using atomic layer deposition (ALD) method to deposit Al2O3 dielectric layer 32 at 120°C to fully wrap the nanowire 3, with a thickness of 20nm;

[0056] Step 5: electrode metal layer deposition: using atomic layer deposition (ALD) method, Au is deposited on the periphery of the dielectric layer 32 as the electrode metal layer 33 with a thickness of 100 nm.

[0057] Step 6: Gate electrode growth, coating, pre-baking, exposure, post-baking and development to form a gate metal pattern, and then use electron beam evaporation to evaporate a single layer of Al metal with a thickness of 120nm, and after a lift-off process (lift-off) to form a gate metal electrode.

[0058] S7. Fabrication of source and drain electrodes: using photolithography technology, using photoresist as a mask, using BOE to remove the dielectric layer 32 in some areas, depositing electrode source electrode metal Au and drain electrode metal Au, and peeling off to complete the fabrication of the source electrode 21 and the drain electrode 22.

[0059] The terminal surface 2 uses silicon terminals. After the diamond substrate layer 1 is hydrogen-terminated, the sample is placed in an ultra-high vacuum system equipped with a Si sublimation source. First, the sample is heated at 450°C for 45 minutes to remove adsorbents on the surface of the hydrogen-terminated diamond. When the sample temperature returns to room temperature, the Si sublimation source is electrically heated to achieve molecular beam deposition of Si on the diamond surface. The current is 50A and the deposition rate is The thickness of the deposited Si single substance is 0.5nm, which is equivalent to 1.85ML. After the deposition is completed, the sample is subjected to in-situ vacuum annealing at 920℃ for 12min. Through this treatment, the C-H structure on the surface of the entire diamond sample can be transformed into a C-Si structure. C-Si diamond has a lower interface state density, higher threshold voltage, and higher hole mobility than C-H diamond. After the sample is taken out and the surface Si is oxidized, it becomes a C-Si-O / SiO2 structure. In this embodiment, the dielectric layer 32 is a 20nm thick MoO3 layer deposited by the ALD method. The source electrode and drain electrode metals in this embodiment are Ti / Pt / Au with a thickness of 150nm. The gate metal in this embodiment is 80nm Al.

[0060] The preparation method further comprises step 1: selecting a substrate, selecting a single crystal diamond substrate layer 1 prepared by a high temperature and high pressure (HPHT) method;

[0061] Step 2: groove etching, after forming a groove shape on the surface of the diamond substrate layer 1 by steps such as coating, pre-baking, exposure, post-baking and development, electron beam evaporation is used to form a metal Au material masking layer with a thickness of 20nm, ICP etching is used to form a groove with an etching depth of 150nm and an inverted trapezoidal shape, and finally a mixed solution of potassium iodide (KI) and iodine (I2) is used to wet etch and remove Au;

[0062] Step 3: terminal surface treatment, pre-treating the diamond substrate 1, including screening, pickling, and cleaning with acetone, anhydrous ethanol, and deionized water, placing the diamond substrate 1 in a hydrogen plasma in an MPCVD reaction chamber, introducing H2 at a flow rate of 700 sccm into the reaction chamber, setting the pressure to 100 mbar, and leaving it at a temperature of 875° C. and a microwave power of 2 kW for 15 minutes to form a terminal surface 31 with two-dimensional cavitation gas;

[0063] Step 4: dielectric layer deposition, using atomic layer deposition (ALD) method to deposit MoO3 dielectric layer 32 at 120°C to fully wrap the nanowire 3, with a thickness of 20nm;

[0064] Step 5: Electrode metal layer deposition, using atomic layer deposition (ALD) method, Ti / Pt / Au is deposited as electrode metal layer 33 on the periphery of dielectric layer 32, with a thickness of 150nm. At this point, the nanowire 3 is prepared, and the source electrode 21 and the drain electrode 22 are formed;

[0065] Step 6: Gate electrode growth, coating, pre-baking, exposure, post-baking and development to form a gate metal pattern, and then use electron beam evaporation to evaporate Al single layer metal with a thickness of 80nm, and after a lift-off process (lift-off) to form a gate metal electrode.

[0066] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A diamond gate-all-around field effect transistor, characterized in that: include: A diamond substrate layer (1); A ring-gate structure (2) suspended above the diamond substrate layer (1), the ring-gate structure (2) comprising a nanowire (3), a gate electrode (23) and a ring-gate electrode (33) coated thereon; The nanowire (3) includes, from the inside to the outside, a diamond core (34), a diamond terminal surface (31), a dielectric layer (32), and a ring gate electrode (33), vertically passes through the gate electrode (23) and is fully wrapped by it; A source electrode (21) and a drain electrode (22), wherein the source electrode (21) and the drain electrode (22) are respectively located on both sides of the gate electrode (23) and form an ohmic contact with the diamond terminal surface (31); A two-dimensional void gas is formed at the interface between the diamond terminal surface (31) and the dielectric layer (32).

2. The diamond gate-all-around field effect transistor according to claim 1, characterized in that: The thickness of the gate electrode (23) is 50nm-500nm.

3. The diamond gate-all-around field effect transistor according to claim 1, characterized in that: The diamond terminal surface (31) is hydrogen-terminated or silicon-terminated.

4. The diamond gate-all-around field effect transistor according to claim 1, characterized in that: The thickness of the dielectric layer (32) is 3nm-50nm.

5. The diamond gate-all-around field effect transistor according to claim 1, characterized in that: The thickness of the ring gate electrode (33) is 10nm-100nm.

6. The diamond-gate-all-around field effect transistor according to claim 1, characterized in that: The thickness of the source electrode (21) is 50nm-500nm.

7. The diamond gate-all-around field effect transistor according to claim 1, characterized in that: The cross-sectional shape of the nanowire (3) is polygonal, circular, elliptical or irregularly circular.

8. A method for preparing a diamond-gated-all-around field effect transistor, using the diamond-gated-all-around field effect transistor according to any one of claims 1 to 7, characterized in that: The method comprises: S1, selecting a diamond substrate layer (1); S2, forming a diamond core (34) in the shape of a nanowire on the surface of the diamond substrate layer (1) by photolithography, specifically comprising: coating a photoresist on the surface of the diamond substrate layer (1) to form a mask; etching by a dry etching process to form a diamond core (34) of the nanowire; removing the mask to retain the nanowire structure; S3, pre-treating the surface of the diamond core (34), and performing hydrogen termination or silicon termination treatment to form a two-dimensional hole gas (2DHG) terminal surface (31) on the surface of the diamond core; S4, depositing dielectric material on the terminal surface (31) of the nanowire in all directions to form a dielectric layer (32), wherein the thickness of the dielectric layer is in the range of 3 nm to 50 nm; S5, depositing metal material in all directions around the dielectric layer (32) to form a ring gate electrode (33); S6, forming a gate electrode (23) on the diamond substrate layer (1) by photolithography, so that the nanowire (3) vertically passes through the gate electrode (23) and is fully wrapped by it; S7, removing part of the dielectric layer (32), and depositing a source electrode (21) and a drain electrode (22) on both sides of the gate electrode (23) by photolithography to form an ohmic contact with the terminal surface (31) of the nanowire (3).

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