A Fin FET device and a manufacturing method thereof

Abstract

The present application discloses a Fin FET device and a manufacturing method thereof, relating to the technical field of semiconductor devices. The Fin FET device includes: a semiconductor substrate; a fin structure located on the semiconductor substrate, the fin structure extending in a first direction; a well region located at the lower part of the fin structure; an STI structure located on the semiconductor substrate and between adjacent well regions; a gate stack structure extending in a second direction intersecting the first direction, the gate stack structure spanning across the upper part of the fin structure and contacting the sidewalls and the top of the upper part of the fin structure respectively; and a source region and a drain region located at the upper part of the fin structure and on both sides of the gate stack structure. Among them, there is an air gap in the STI structure, the air gap extends in the second direction, and the part of the gate stack structure located on the surface of the STI structure is opposite to the air gap in the STI structure. By providing an air gap in the STI structure, the present application reduces the parasitic capacitance of the Fin FET device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a FinFET device and a manufacturing method thereof. Background Art

[0002] A FinFET (Fin Field-Effect Transistor) is a new type of complementary metal-oxide-semiconductor (CMOS) transistor, which is developed to address the short-channel effect encountered by traditional planar transistors at the nanoscale. A FinFET is a three-dimensional transistor structure, and its design allows maintaining the performance and switching characteristics of the transistor at smaller sizes.

[0003] The basic structure of a FinFET includes a vertical silicon fin similar to a "fin", and the two sides and the top of the silicon fin are surrounded by a gate. This fin forms the channel of the transistor, and the source and drain are located on both sides of the fin. Compared with traditional planar transistors, the gate of a FinFET surrounds more areas of the channel, providing better gate control and enabling more effective opening and closing of the current.

[0004] With the continuous progress of FinFET technology, reducing the resistance-capacitance delay (RC delay) is the key to improving the speed and efficiency of circuits. In traditional technologies, copper (Cu) metal interconnection is usually used to reduce the resistance-capacitance delay problem, but the effect is not obvious. Summary of the Invention

[0005] In view of the above problems, the purpose of the present application is to provide a FinFET device and a manufacturing method thereof, by setting an air gap in the STI structure to reduce the parasitic capacitance of the FinFET device, thereby effectively solving the resistance-capacitance delay problem.

[0006] According to an aspect of the present invention, there is provided a FinFET device, comprising: a semiconductor substrate; a fin-shaped structure located on the semiconductor substrate, wherein the fin-shaped structure extends in a first direction; a well region located at the lower part of the fin-shaped structure; an STI structure located on the semiconductor substrate and between adjacent well regions; a gate stack structure extending in a second direction intersecting with the first direction, the gate stack structure straddling the upper part of the fin-shaped structure and contacting the sidewalls and the top of the upper part of the fin-shaped structure respectively; and a source region and a drain region located at the upper part of the fin-shaped structure and on both sides of the gate stack structure; wherein, there is an air gap in the STI structure, the air gap extends in a second direction intersecting with the first direction, and the part of the gate stack structure located on the surface of the STI structure is opposite to the air gap in the STI structure.

[0007] Optionally, the air gap extending in the second direction is blocked by the fin-shaped structure extending in the first direction.

[0008] Optionally, the gate dielectric layer, the STI structure, and the air gap in the STI structure form a first isolation dielectric between the gate conductor and the substrate; the gate conductor, the first isolation dielectric, and the substrate form a first parasitic capacitance.

[0009] Optionally, the fin structure extends in a first direction with a length of L, the air gap has a width of W1 in the first direction, the gate stack structure has a width of W2 in the first direction, and W2 ≤ W1 ≤ L / 3.

[0010] Optionally, it further includes a dielectric layer located between adjacent gate conductors; an air gap is formed in the dielectric layer, and the air gap in the dielectric layer is located between the gate conductors arranged in the first direction and / or between the gate conductors arranged in the second direction.

[0011] Optionally, the dielectric layer and the air gap in the dielectric layer form a second isolation dielectric, and adjacent gate conductors and the second isolation dielectric form a second parasitic capacitance.

[0012] According to another aspect of the present invention, a manufacturing method of a Fin FET device is provided, including: forming a fin structure in a semiconductor substrate, where the fin structure extends in a first direction; forming a hard mask layer on the upper part of the fin structure, and doping the lower part of the fin structure through the hard mask layer to form a well region; forming an STI structure on the semiconductor substrate, the STI structure is located between adjacent fin structures and exposes the upper part of the fin structure; forming an air gap in the STI structure; forming a gate stack structure and source and drain regions, the gate stack structure extends in a second direction intersecting with the first direction, the gate stack structure straddles the upper part of the fin structure, and is in contact with the side walls and the top of the upper part of the fin structure respectively, and the source and drain regions are located at the upper part of the fin structure and on both sides of the gate stack structure; where the air gap extends in a second direction intersecting with the first direction, and the part of the gate stack structure located on the surface of the STI structure is opposite to the air gap.

[0013] Optionally, the method of forming an air gap in the STI structure includes: forming a trench in the STI structure, the trench extends from the surface of the STI structure into its interior, the trench extends in a second direction intersecting with the first direction and is blocked by the fin structure extending in the first direction; quickly filling a dielectric layer at the top of the trench to quickly seal the trench and form an air gap.

[0014] Optionally, it further includes: forming a dielectric layer between adjacent gate conductors; using a CMP process to planarize the surface of the dielectric layer; forming a trench extending from the surface of the dielectric layer into its interior in the dielectric layer; and quickly filling a dielectric layer at the top of the trench to quickly seal the trench and form an air gap.

[0015] Optionally, the air gap in the dielectric layer is located between the gate conductors arranged in the first direction and / or between the gate conductors arranged in the second direction.

[0016] The unexpected technical effect of this application is:

[0017] In the embodiment of this application, by forming an air gap in the STI structure, the overall dielectric constant of the first isolation medium is reduced, thereby reducing the first parasitic capacitance and effectively solving the resistance-capacitance delay (RC delay) problem.

[0018] In a preferred embodiment, by aligning the gate stack structure with the air gap in the STI structure and setting the size of the air gap, while minimizing the first parasitic capacitance as much as possible, the lateral size of the air gap is reduced to prevent the size of the air gap from being too large and affecting the firmness and stability of the Fin FET device.

[0019] In a preferred embodiment, the air gap extends in a second direction intersecting the first direction, but the air gap is only located in the STI structure and not in the fin structure, but is blocked by the fin structure to prevent the air gap from affecting the fin structure and the well region formed by the fin structure, thereby affecting the conductivity of the Fin FET device.

[0020] In a preferred embodiment, by forming an air gap in the dielectric layer, the overall dielectric constant of the second isolation medium is reduced, thereby reducing the second parasitic capacitance and effectively solving the resistance-capacitance delay (RC delay) problem of the Fin FET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Through the following description of the embodiments of this application with reference to the drawings, the above and other objects, features, and advantages of this application will become clearer. In the drawings:

[0022] Figure 1a A schematic diagram of a Fin FET device provided by an embodiment of this application is shown;

[0023] Figure 1b Shown is Figure 1a A cross-sectional view along the AA direction;

[0024] Figure 1c Shown is Figure 1a A schematic diagram with the dielectric layer omitted;

[0025] Figure 1d Shown is Figure 1c A cross-sectional view along the AA direction;

[0026] Figures 2a to 2s It is a schematic diagram of each step of a manufacturing method of an exemplary Fin FET device provided by an embodiment of this application, where:

[0027] Figure 2aShows a schematic diagram of forming a first hard mask layer on a semiconductor substrate and forming an auxiliary structure on the first hard mask layer in an embodiment of the present application;

[0028] Figure 2b Shows a schematic diagram of forming a second hard mask layer in an embodiment of the present application;

[0029] Figure 2c Shows a schematic diagram of forming a sidewall structure in an embodiment of the present application;

[0030] Figure 2d Shows a schematic diagram of removing the auxiliary structure in an embodiment of the present application;

[0031] Figure 2e Shows a schematic diagram of forming a fin structure in a semiconductor substrate in an embodiment of the present application;

[0032] Figure 2f Shows a schematic diagram of removing the sidewall structure in an embodiment of the present application;

[0033] Figure 2g Shows a schematic diagram of forming a first dielectric layer in an embodiment of the present application;

[0034] Figure 2h Shows a schematic diagram of re-etching the first dielectric layer in an embodiment of the present application;

[0035] Figure 2i Shows a schematic diagram of removing the first hard mask layer on the top of the fin structure in an embodiment of the present application;

[0036] Figure 2j Shows a schematic diagram of forming a third hard mask layer in an embodiment of the present application;

[0037] Figure 2k Shows a schematic diagram of removing the first dielectric layer in an embodiment of the present application;

[0038] Figure 2l Shows a schematic diagram of forming a well region in the lower part of the fin structure in an embodiment of the present application;

[0039] Figure 2m Shows a schematic diagram of removing the third hard mask layer on the upper part of the fin structure in an embodiment of the present application;

[0040] Figure 2n Shows a schematic diagram of forming an STI structure in an embodiment of the present application;

[0041] Figure 2o Shows a schematic diagram of forming a trench in the STI structure in an embodiment of the present application;

[0042] Figure 2p Shows a schematic diagram of forming an air gap in an embodiment of the present application;

[0043] Figure 2qA schematic diagram showing the formation of a gate dielectric layer and a gate conductor layer in an embodiment of the present application is shown;

[0044] Figure 2r A schematic diagram showing the formation of a gate stack structure and source and drain regions in an embodiment of the present application is shown;

[0045] Figure 2s A schematic diagram showing the formation of a dielectric layer and the formation of an air gap in the dielectric layer in an embodiment of the present application is shown. Detailed implementation manners

[0046] The present application will be described in more detail below with reference to the accompanying drawings. In the respective drawings, like elements are denoted by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0047] When describing the structure of a device, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the device is flipped, this layer or this region will be "below" or "beneath" the other layer or the other region.

[0048] If it is for describing the case of being directly above another layer or another region, the expressions "directly on... above" or "above and adjacent to..." will be used herein.

[0049] Unless otherwise specifically indicated below, the various parts of a semiconductor device may be made of materials well known to those skilled in the art. Semiconductor materials include, for example, III-V group semiconductors such as gallium arsenide (GaAs), gallium nitride (GaN), etc., IV-IV group semiconductors such as silicon carbide (SiC), etc., II-VI group compound semiconductors such as cadmium sulfide (CdS), cadmium telluride (CdTe), etc., and IV group semiconductors such as silicon (Si), germanium (Ge), etc. The gate conductor can be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric layer may be made of SiO2 or a material with a dielectric constant greater than that of SiO2, for example, including oxides, nitrides, oxynitrides, silicates, aluminates, titanates. And the gate dielectric layer can not only be formed of materials well known to those skilled in the art, but also materials developed in the future for gate dielectric layers can be used.

[0050] This application can be presented in various forms, and some examples will be described below.

[0051] Figure 1a A schematic diagram of a Fin FET device provided by an embodiment of this application is shown. Figure 1b Shows Figure 1a A cross-sectional view along the AA direction. Figure 1c Shows Figure 1a A schematic diagram omitting the dielectric layer. Figure 1d Shows Figure 1c A cross-sectional view along the AA direction.

[0052] As Figures 1a to 1d Shown, the Fin FET device includes a semiconductor substrate 101, a fin structure, an STI (Shallow Trench Isolation) structure 108, a gate stack structure, and a dielectric layer 115.

[0053] The fin structure is located on the semiconductor substrate 101 and extends in a first direction (such as Figures 1a to 1d the Y-axis direction in). In this embodiment, the semiconductor substrate 101 is etched to form a fin structure on the semiconductor substrate 101, that is, the semiconductor substrate 101 and the fin structure are made of the same material, and the semiconductor substrate 101 and the fin structure can be selected from any one of a semiconductor layer, a doped well region, a doped epitaxial semiconductor layer, or a combination thereof.

[0054] The lower part of the fin structure is doped to form a well region 107, and a dielectric layer is filled between adjacent well regions 107 to form an STI structure 108, that is, adjacent well regions 107 are isolated via the STI structure 108. The gate stack structure extends in a second direction (such as Figures 1a to 1d the X-axis direction in) intersecting the first direction, and the gate stack structure straddles the upper part of the fin structure and contacts the sidewalls and the top of the upper part of the fin structure respectively. The upper part of the fin structure surrounded by the gate stack structure forms the channel region 113 of the device, and the upper parts of the fin structures on both sides of the channel region 113 are doped to form a source region 111 and a drain region 112. Among them, the doping types of the source region 111 and the drain region 112 are opposite to the doping type of the well region 107. For example, for an N-type MOSFET, the well region 107 is P-type doped, and the source region 111 and the drain region 112 are N-type doped; for a P-type MOSFET, the well region 107 is N-type doped, and the source region 111 and the drain region 112 are P-type doped. The gate stack structure includes a gate dielectric 109 and a gate conductor 110, and the gate dielectric 109 separates the gate conductor 110 from the fin structure. The lower surface of the gate stack structure contacts the STI structure 108. Specifically, the gate dielectric 109 on the lower surface of the gate stack structure contacts the STI structure 108.

[0055] Further, an air gap 108a is also formed in the STI structure 108. In this embodiment, the fin structure extends in a first direction (e.g., Figures 1a to 1d the Y-axis direction in Figures 1a to 1d ). The air gap 108a extends in a second direction intersecting the first direction (e.g., Figure 1b the X-axis direction in

[0056] ). However, it should be noted that the air gap 108a is only located in the STI structure 108, not in the fin structure, but is blocked by the fin structure, as Figure 1b shown.

[0056] The dielectric layer 115 covers the surface of the gate stack structure (specifically, the surface of the gate conductor 110), covers the surface of the fin structure, fills the space between adjacent gate stack structures, and fills the space between adjacent fin structures. Further, an air gap 115a is also formed in the dielectric layer 115. The air gap 115a can be provided as one or more, and the air gap 115a is located between adjacent gate conductors 110. Figure 1b In the embodiment shown in Figures 1a to 1d , the air gap 115a is located between the gate conductors 110 arranged in the second direction (e.g., Figure 1b the X-axis direction in Figures 1a to 1d ). Although not shown in Figure 1b , it is worth noting that the air gap 115a can also be provided between the gate conductors 110 arranged in the first direction (e.g., Figures 1a to 1d the Y-axis direction in

[0057] Refer to Figure 1b and Figure 1d , the gate dielectric 109, the STI structure 108, and the air gap 108a in the STI structure 108 constitute the first isolation dielectric between the gate conductor 110 and the semiconductor substrate 101. A first parasitic capacitance C1 is formed between the gate conductor 110, the first gate isolation dielectric, and the semiconductor substrate 101. In this embodiment, by forming the air gap 108a in the STI structure 108, the overall dielectric constant of the first isolation dielectric is reduced, thereby reducing the first parasitic capacitance C1. The dielectric layer 115 and the air gap 115a in the dielectric layer 115 constitute the second isolation dielectric between adjacent gate conductors 110. The adjacent gate conductors 110 and the second isolation dielectric between the gate conductors 110 constitute a second parasitic capacitance C2. In this embodiment, by forming the air gap 115a in the dielectric layer 115, the overall dielectric constant of the second isolation dielectric is reduced, thereby reducing the second parasitic capacitance C2. The reduction of the first parasitic capacitance C1 and the second parasitic capacitance C2 helps to solve the problem of resistance-capacitance delay (RC delay) of the Fin FET device.

[0058] Further, the portion of the gate stack structure located on the surface of the STI structure 108 is opposite to the air gap 108a in the STI structure 108. In one embodiment, the length of the fin structure extending in the first direction is L, the width of the air gap 108a in the first direction is W1, the width of the gate stack structure in the first direction is W2, and W2 ≤ W1 ≤ L / 3.

[0059] In the embodiment of the present application, by making the gate stack structure opposite to the air gap in the STI structure and setting the size of the air gap, while minimizing the first parasitic capacitance as much as possible, the lateral size of the air gap is reduced to prevent the size of the air gap from being too large, which affects the firmness and stability of the Fin FET device.

[0060] Corresponding to the Fin FET device provided in the above embodiment, the present application also provides a manufacturing method of the Fin FET device, and the manufacturing method includes:

[0061] Step S10: Form a fin structure in the semiconductor substrate, wherein the fin structure extends in the first direction;

[0062] Step S20: Form a hard mask layer on the upper part of the fin structure, and dope the lower part of the fin structure through the hard mask layer to form a well region;

[0063] Step S30: Form an STI structure between the fin structures;

[0064] Step S40: Form an air gap in the STI structure;

[0065] Step S50: Form a gate stack structure and source and drain regions;

[0066] Wherein, the air gap and the gate stack structure extend in a second direction intersecting the first direction, and the portion of the gate stack structure located on the surface of the STI structure is opposite to the air gap.

[0067] Figures 2a to 2s It is a schematic diagram of each step of an exemplary manufacturing method of a Fin FET device provided in the embodiment of the present application. The following combines Figures 2a to 2r to describe in detail the manufacturing method of the Fin FET device provided in the embodiment of the present application.

[0068] As Figures 2a to 2f shown, in step S10, a fin structure 101a is formed in the semiconductor substrate 101, wherein the fin structure 101a extends in the first direction.

[0069] Refer to Figure 2a, a first hard mask layer 102 is formed on a semiconductor substrate 101, and an auxiliary structure 103 is formed on the first hard mask layer 102. Specifically, the first hard mask layer 102 is formed on the semiconductor substrate 101, and the first hard mask layer 102 covers the surface of the semiconductor substrate 101. In this embodiment, the semiconductor substrate 101 is single-crystalline silicon or silicon-on-insulator (SOI), and the first hard mask layer 102 is a nitride layer (such as a silicon nitride layer). Then, an auxiliary layer is formed on the first hard mask layer 102, a patterned photoresist is formed on the auxiliary layer by a lithography process, and the auxiliary layer is etched through the patterned photoresist to form the auxiliary structure 103. Among them, the auxiliary structure 103 is used to define the position of a subsequent formed sidewall structure 104a, so as to finally define the position of the fin structure 101a. In this embodiment, the material of the auxiliary structure 103 is, for example, polysilicon.

[0070] Refer to Figure 2b , a second hard mask layer 104 is formed. Specifically, the second hard mask layer 104 is formed by a deposition process, and the second hard mask layer 104 conformally covers the surface of the first hard mask layer 102, as well as the top surface and sidewalls of the auxiliary structure 103. In this embodiment, the second hard mask layer 104 is, for example, an oxide layer.

[0071] Refer to Figure 2c , a sidewall structure 104a is formed. Specifically, the second hard mask layer 104 is etched by an etching process. Among them, the second hard mask layer 104 on the surface of the first hard mask layer 102 and the second hard mask layer 104 on the top surface of the auxiliary structure 103 are removed, while the second hard mask layer 104 on the sidewalls of the auxiliary structure 103 is retained to form the sidewall structure 104a. In this embodiment, for example, a dry etching process is used to etch the second hard mask layer 104. During the dry etching process, the first hard mask layer 102 serves as a protective layer for the semiconductor substrate 101 to prevent over-etching from damaging the surface of the semiconductor substrate 101.

[0072] Refer to Figure 2d , after the sidewall structure 104a is formed, the auxiliary structure 103 is removed.

[0073] Refer to Figure 2e , the first hard mask layer 102 and the semiconductor substrate 101 are etched through the sidewall structure 104a to form a fin structure 101a in the semiconductor substrate 101. Among them, the fin structure 101a includes an upper part 101a-1 and a lower part 101a-2. The upper part 101a-1 is used to form the source region, drain region, and channel region between the source region and the drain region of the device; the lower part 101a-2 is used to form the well region of the device. Further, the fin structure 101a extends in a first direction, and the first direction is, for example, Figure 2e the Y-axis direction in

[0074] Refer to Figure 2f, remove the sidewall structure 104a.

[0075] Further, as Figures 2g to 2m shown, in step S20, a hard mask layer is formed on the upper portion of the fin structure 101a, and the lower portion of the fin structure 101a is doped through the hard mask layer to form the well region 107;

[0076] Refer to Figure 2g , a first dielectric layer 105 is formed. The first dielectric layer 105 fills the gap between the fin structures 101a and covers the top of the first hard mask layer 102. Then, a CMP (Chemical Mechanical Planarization) process is used to remove the first dielectric layer 105 on the top of the first hard mask layer 102 and make the top of the first dielectric layer 105 flush with the top of the first hard mask layer 102.

[0077] Refer to Figure 2h , the first dielectric layer 105 is re-etched to remove the first dielectric layer 105 between the upper portions 101a-1 of the fin structures 101a, while the first dielectric layer 105 between the lower portions 101a-2 of the fin structures 101a is retained. In this step, for example, dry etching is used to re-etch the first dielectric layer 105. Among them, the first hard mask layer 102 serves as a protective layer for the fin structure 101a to prevent damage to the fin structure 101a during the re-etching process.

[0078] Refer to Figure 2i , remove the first hard mask layer 102 on the top of the fin structure 101a.

[0079] Refer to Figure 2j , a third hard mask layer 106 is formed on the top and sidewalls of the upper portion 101a-1 of the fin structure 101a. Specifically, the third hard mask layer 106 is formed. The third hard mask layer 106 conformally covers the surface of the first dielectric layer 105 and the exposed top and sidewalls of the fin structure 101a (i.e., the top and sidewalls of the upper portion 101a-1 of the fin structure 101a). Then, the third hard mask layer 106 on the surface of the first dielectric layer 105 is selectively removed, and the remaining third hard mask layer 106 covers the top and sidewalls of the upper portion 101a-1 of the fin structure 101a.

[0080] Refer to Figure 2k , remove the first dielectric layer 105 to expose the surface of the semiconductor substrate 101 and the sidewalls of the lower portion 101a-2 of the fin structure 101a.

[0081] Refer to Figure 2l, ion implantation is performed on the lower part 101a-2 of the fin structure 101a through the third hard mask layer 106 to form a well region 107 in the lower part 101a-2 of the fin structure 101a. Further, while performing ion implantation on the exposed surface of the semiconductor substrate 101, the well region 107 is also formed on the surface of the semiconductor substrate 101 and extends a certain depth from the surface of the semiconductor substrate 101 into its interior. It should be noted that for different types of MOS devices, such as PMOS devices and NMOS devices, the doping type of the well region 107 is different, and the doping type of the well region 107 can be set according to the type of MOS device to be formed. For example Figure 2l the doping types of the well regions 107 of the two fin structures 101a shown can be set to be the same or different.

[0082] Refer to Figure 2m , the third hard mask layer 106 on the upper part 101a-1 of the fin structure 101a is removed to expose the top and sidewalls of the upper part 101a-1 of the fin structure 101a.

[0083] Further, refer to Figure 2n , in step S30, an STI structure 108 is formed between the fin structures 101a.

[0084] In this step, a second dielectric layer is formed. The second dielectric layer fills the gap between the fin structures 101a and covers the top of the fin structures 101a. Then, the second dielectric layer on the top of the fin structures 101a is removed by using a CMP process, and the top of the second dielectric layer is made flush with the top of the fin structures 101a. Then, the second dielectric layer is etched back to remove the second dielectric layer between the upper parts 101a-1 of the fin structures 101a, while retaining the second dielectric layer between the lower parts 101a-2 of the fin structures 101a. The second dielectric layer between the lower parts 101a-2 of the fin structures 101a forms the STI structure 108. The STI structure 108 is located between the lower parts 101a-2 of adjacent fin structures 101a, exposing the upper parts 101a-1 of the fin structures 101a.

[0085] Further, refer to Figure 2o and Figure 2p , in step S40, an air gap 108a is formed in the STI structure.

[0086] Refer to Figure 2o , a trench 108a-1 is formed in the STI structure 108.

[0087] In this step, for example, a patterned mask layer is formed on the surface of the semiconductor structure formed above, and the surface of the STI structure 108 is etched through the patterned mask layer to form a trench 108a-1 extending from the surface of the STI structure 108 into its interior. Among them, on the surface of the STI structure 108, the trench 108a-1 extends in a second direction intersecting the first direction, and the second direction is, for example, Figure 2o the X-axis direction in

[0088] As Figure 2p shown, a third dielectric layer is rapidly deposited on the top of the trench 108a-1 to rapidly seal the trench 108a-1. After depositing the third dielectric layer, the top of the trench 108a-1 is covered by the third dielectric layer, and the trench 108a-1 forms an air gap 108a whose top is blocked by the third dielectric layer.

[0089] Referring to Figures 2q to 2r , in step S50, a gate stack structure and source and drain regions are formed.

[0090] Referring to Figure 2q , a gate dielectric layer 109a and a conductor layer 110a are sequentially formed on the above semiconductor structure. The gate dielectric layer 109a conformally covers the surface of the above semiconductor structure, and the conductor layer 110a covers the surface of the gate dielectric layer 109a.

[0091] Referring to Figure 2r , the conductor layer 110a is etched to form a gate conductor 110. Further, the gate dielectric layer 109a is etched to form a gate dielectric 109. The gate dielectric 109 is located between the gate conductor 110 and the fin structure 101a and between the gate conductor 110 and the STI structure 108. Among them, the gate dielectric 109 and the gate conductor 110 constitute a gate stack structure.

[0092] Furthermore, the gate stack structure located on the STI structure 108 is opposite to the air gap 108a in the STI structure 108. The width of the air gap 108a in the first direction is W1, the length of the fin structure 101a extending in the first direction is L, the width of the gate stack structure in the first direction is W2, and W2 ≤ W1 ≤ L / 3.

[0093] Then, the fin structure 101a is ion-implanted to form a source region 111 and a drain region 112 in the fin structure 101a.

[0094] Referring to Figure 2s , a dielectric layer 115 is formed, and an air gap 115a is formed in the dielectric layer 115.

[0095] Specifically, for example, a dielectric layer 115 is formed by a deposition process, and the dielectric layer 115 is planarized by a CMP process. Then, a trench is formed in the dielectric layer 115, and the trench is rapidly filled with a dielectric layer at the top thereof so that the trench is rapidly sealed to form an air gap 115a in the dielectric layer 115.

[0096] The air gap 115a is located between the gate conductors 110 arranged in the first direction and / or between the gate conductors 110 arranged in the second direction.

[0097] The unexpected technical effect of this application is:

[0098] By forming an air gap in the STI structure in the embodiment of this application, the overall dielectric constant of the first isolation medium is reduced, thereby reducing the first parasitic capacitance and effectively solving the resistance-capacitance delay (RC delay) problem.

[0099] In a preferred embodiment, by opposing the gate stack structure to the air gap in the STI structure and setting the size of the air gap, while minimizing the first parasitic capacitance as much as possible, the lateral size of the air gap is reduced to prevent the size of the air gap from being too large and affecting the firmness and stability of the Fin FET device.

[0100] In a preferred embodiment, the air gap extends in a second direction intersecting the first direction, but the air gap is only located in the STI structure and not in the fin structure, but is blocked by the fin structure to prevent the air gap from affecting the fin structure and the well region formed by the fin structure, thereby affecting the conductivity of the Fin FET device.

[0101] In a preferred embodiment, by forming an air gap in the dielectric layer, the overall dielectric constant of the second isolation medium is reduced, thereby reducing the second parasitic capacitance and effectively solving the resistance-capacitance delay (RC delay) problem of the Fin FET device.

[0102] As described above in the embodiments of this application, these embodiments do not describe all the details in detail, nor limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of this application, so that those skilled in the art can make good use of this application and its modifications based on this application. This application is only limited by the claims and their full scope and equivalents.

Claims

1. A Fin FET device, characterized in that, Comprising: A semiconductor substrate; A fin structure located on the semiconductor substrate, wherein the fin structure extends in a first direction; A well region located at the lower part of the fin structure; An STI structure located on the semiconductor substrate and between adjacent well regions; A gate stack structure extending in a second direction intersecting the first direction, the gate stack structure spanning the upper part of the fin structure and contacting the sidewalls and the top of the upper part of the fin structure respectively; and A source region and a drain region located at the upper part of the fin structure and on both sides of the gate stack structure; Wherein, an air gap is formed in the STI structure, the air gap extends in a second direction intersecting the first direction, and the part of the gate stack structure located on the surface of the STI structure is opposite to the air gap in the STI structure; the length of the fin structure extending in the first direction is L, the width of the air gap in the first direction is W1, the width of the gate stack structure in the first direction is W2, and W2≤W1≤L / 3.

2. The Fin FET device according to claim 1, wherein The air gap extending in the second direction is blocked by the fin structure extending in the first direction.

3. The Fin FET device according to claim 1, wherein The gate dielectric layer, the STI structure and the air gap in the STI structure constitute the first isolation medium between the gate conductor and the substrate; The gate conductor, the first isolation medium and the substrate constitute the first parasitic capacitance.

4. The Fin FET device according to claim 1, wherein, It further includes a dielectric layer located between adjacent gate conductors; Wherein, an air gap is formed in the dielectric layer, and the air gap in the dielectric layer is located between the gate conductors arranged in the first direction and / or between the gate conductors arranged in the second direction.

5. The Fin FET device according to claim 4, wherein The dielectric layer and the air gap in the dielectric layer constitute the second isolation medium, and adjacent gate conductors and the second isolation medium constitute the second parasitic capacitance.

6. A manufacturing method of a Fin FET device, characterized in that, Comprising: Forming a fin structure in the semiconductor substrate, wherein the fin structure extends in a first direction; Forming a hard mask layer on the upper part of the fin structure, and doping the lower part of the fin structure through the hard mask layer to form a well region; Forming an STI structure on the semiconductor substrate, the STI structure is located between adjacent fin structures and exposes the upper part of the fin structure; Forming a trench in the STI structure, the trench extends from the surface of the STI structure to its interior, the trench extends in a second direction intersecting the first direction and is blocked by the fin structure extending in the first direction; Rapidly filling a dielectric layer at the top of the trench to quickly seal the trench and form an air gap; Forming a gate stack structure and a source region and a drain region, the gate stack structure extends in a second direction intersecting the first direction, the gate stack structure spans the upper part of the fin structure and contacts the sidewalls and the top of the upper part of the fin structure respectively, the source region and the drain region are located at the upper part of the fin structure and on both sides of the gate stack structure; Wherein, the air gap extends in a second direction intersecting the first direction, and the part of the gate stack structure located on the surface of the STI structure is opposite to the air gap.

7. The manufacturing method according to claim 6, characterized in that, It further includes: Forming a dielectric layer between adjacent gate conductors; Making the surface of the dielectric layer flat by using a CMP process; Forming a trench in the dielectric layer that extends from the surface of the dielectric layer to its interior; And Rapidly filling a dielectric layer at the top of the trench to quickly seal the trench and form an air gap.

8. The manufacturing method according to claim 7, characterized in that, The air gap in the dielectric layer is located between the gate conductors arranged in the first direction and / or between the gate conductors arranged in the second direction.

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