Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate; the epitaxial layer is located on the surface of one side of the substrate; the cellular structure comprises a plurality of active regions and grids, the active regions are arranged in the epitaxial layer at intervals, each active region comprises an injection region, a base region and a source region, the injection region and the base region are adjacent, the source region is located in the base region, the source region is in contact with the injection region, the side face, close to the other active region, of the active region is the side face of the base region, and each grid comprises a common part and a plurality of split grids. The common part and the split gates are located on the side, away from the substrate, of the epitaxial layer, the split gates surround the common part and are all connected with the common part, the orthographic projection of one split gate on the epitaxial layer covers part of the surface, away from the substrate, of one base region, the doping type of the base region and the doping type of the injection region are the first doping type, and the doping type of the injection region is the second doping type. The doping type of the source region, the epitaxial layer and the substrate is a second doping type. The problem that in the prior art, a plane split gate type semiconductor structure is poor in reliability is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular, to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Silicon carbide (SiC) is a landmark product of the third generation of semiconductor materials. Compared with the first generation of silicon materials, it has significantly improved the bandgap width, breakdown field strength, thermal conductivity, etc., which can meet the market demand for high temperature resistance, high voltage, and high frequency characteristics of power devices to the greatest extent. The reliability and performance of gate oxide (Gox), as a barrier restricting the large-scale application of silicon carbide MOSFET, has attracted widespread attention from scholars at home and abroad.

[0003] In order to improve the reliability of gate oxide and the switching speed of devices, researchers have proposed planar split-gate SiC MOSFET, such as Figure 1 and Figure 2 As shown, the structure includes: substrate 10', epitaxial layer 11', gate 12', implantation region 13' and base region 14', source region 15' and gate oxide layer 17'. In this structure, Gate Poly (polysilicon gate) is divided into two long strips, the ends of which are directly connected to Gate Bus (gate bus), and the two Gate Polys are separated. At the same time, the cell design (implantation of active area) is also long strip (see Figure 2 ). However, with the development of the application market, the size requirements of the cell pitch (pitch) are getting smaller and smaller, which leads to the continuous compression of the width of the Gate Poly. Too narrow Gate poly makes the process more difficult. The narrower the Gate poly, the higher the risk of fracture. At the same time, it will also weaken the gate's turn-off ability. Figure 2 In the structural design shown, failure at just one position will result in a turn-off failure of the entire gate, causing a serious electric field imbalance problem and deteriorating the reliability of the device. Summary of the invention

[0004] The main purpose of the present application is to provide a semiconductor structure and a manufacturing method thereof, so as to at least solve the problem of poor reliability of the planar split-gate semiconductor structure in the prior art.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor structure is provided, comprising: a substrate; an epitaxial layer, located on a side surface of the substrate; a cellular structure, comprising a plurality of active regions and a gate, wherein the plurality of active regions are arranged at intervals in the epitaxial layer, the active region comprises an adjacent injection region and a base region, and a source region located in the base region, the source region is in contact with the injection region, and a side of the active region close to another active region is a side of the base region, the gate comprises a common portion and a plurality of split gates, the common portion and the plurality of split gates are located on a side of the epitaxial layer away from the substrate, the plurality of split gates surround the common portion and are all connected to the common portion, the orthographic projection of one split gate on the epitaxial layer covers a partial surface of the base region away from the substrate, the doping type of the base region and the injection region is a first doping type, and the doping type of the source region, the epitaxial layer and the substrate is a second doping type.

[0006] Optionally, the two split gates correspond to one base region, the orthographic projection of one of the two split gates in the epitaxial layer covers a portion of the surface of the base region away from the substrate, and the orthographic projection of the other of the two split gates in the epitaxial layer covers the remaining portion of the surface of the base region away from the substrate.

[0007] Optionally, the cell structure also includes: a JFET region located in the epitaxial layer, the JFET region being located between any two adjacent base regions and respectively contacting each of the base regions, and the orthographic projection of the split gate on the epitaxial layer covering a portion of the surface of the base region away from the substrate, a portion of the surface of the JFET region away from the substrate, and a portion of the surface of the source region away from the substrate.

[0008] Optionally, the cell structure further includes: a gate oxide layer located between the gate and the epitaxial layer, and the gate oxide layer is located on a surface of the JFET region away from the substrate.

[0009] Optionally, the semiconductor structure also includes: a dielectric layer, located on the surface of the gate away from the epitaxial layer, on the side wall of the gate, and on the surface of the gate oxide layer away from the epitaxial layer; a source metal layer, located on the surface of the injection region away from the substrate, on the partial surface of the source region away from the substrate, on the surface of the dielectric layer away from the epitaxial layer, and on the side wall of the dielectric layer; a drain metal layer, located on the surface of the substrate away from the epitaxial layer.

[0010] Optionally, the cellular structure is a square cell.

[0011] According to another aspect of the present application, a method for manufacturing the semiconductor structure is provided, comprising: providing a substrate; forming an initial epitaxial layer on a surface of one side of the substrate; forming a plurality of active regions at least in the initial epitaxial layer, the remaining initial epitaxial layer forming an epitaxial layer, the plurality of active regions being arranged at intervals in the epitaxial layer, the active region comprising an adjacent implantation region and a base region, and a source region located in the base region, the source region being in contact with the implantation region, the side of the active region close to another active region being the side of the base region, the doping types of the base region and the implantation region being a first doping type, the doping types of the source region, the epitaxial layer and the substrate being a second doping type; forming a gate on a side of the epitaxial layer away from the substrate, the gate comprising a common portion and a plurality of split gates, the common portion and the plurality of split gates being located on a side of the epitaxial layer away from the substrate, the plurality of split gates surrounding the common portion and being connected to the common portion, the orthographic projection of one split gate on the epitaxial layer covering a partial surface of the base region away from the substrate.

[0012] Optionally, a plurality of active regions are formed at least in the initial epitaxial layer, including: forming a plurality of active regions in the initial epitaxial layer; stacking a first mask plate and a second mask plate on a side of the initial epitaxial layer away from the substrate, and using a double-layer mask technology to form a first barrier layer on the surface of the initial epitaxial layer away from the substrate, the first barrier layer exposes the initial epitaxial layer between any two adjacent base regions, the first mask plate is a mask plate used in the process of forming the base region, and the second mask plate is a mask plate used in the process of forming the gate; using the first barrier layer as a mask, ion implantation is performed on the initial epitaxial layer formed with the active regions to form a JFET region in the initial epitaxial layer, the initial epitaxial layer formed with the JFET region forms the epitaxial layer, and the orthographic projection of the split gate on the epitaxial layer covers a portion of the surface of the base region away from the substrate, a portion of the surface of the JFET region away from the substrate, and a portion of the surface of the source region away from the substrate; and removing the first barrier layer.

[0013] Optionally, a plurality of active regions are formed in the initial epitaxial layer, including: setting the first mask on a side of the initial epitaxial layer away from the substrate, and using the first mask to form a second barrier layer on the surface of the initial epitaxial layer away from the substrate, the second barrier layer exposes part of the surface of the initial epitaxial layer; using the second barrier layer as a mask, ion implanting the initial epitaxial layer to obtain a plurality of initial base regions spaced apart; ion implanting a portion of the initial base region away from an adjacent initial base region to form an implantation region in the initial base region; ion implanting the initial base region to form a source region adjacent to the implantation region in the initial base region, the remaining initial base region forming the base region, the source region being on a side of the implantation region close to the adjacent active region; and removing the second barrier layer.

[0014] Optionally, after removing the first barrier layer and before forming a gate on a side of the epitaxial layer away from the substrate, the method further includes: annealing the structure formed with the JFET region; and forming a gate oxide layer on a portion of the surface of the epitaxial layer away from the substrate, the gate oxide layer being located on the surface of the JFET region away from the substrate.

[0015] By applying the technical solution of the present application, a mesh gate structure composed of a split gate and a common part is adopted. When a split gate is broken, other split gates can still be connected to the gate bus through the common part, thereby receiving the control signal of the gate, and the problem of the entire gate failing will not occur. It avoids the problems of cracking and degradation of effective shutdown capability caused by the size reduction of the split gate. In other words, the present application can greatly overcome the dilemma of the existing planar split gate technology that the cell pitch cannot be further reduced due to the minimum process line width limitation of the gate; at the same time, the present application can retain the low impedance and high switching speed performance of the planar split gate semiconductor structure, ensuring the reliability of the semiconductor structure and good device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A schematic diagram of the cross-sectional structure of a planar split-gate MOSFET in the prior art is shown;

[0018] Figure 2 Shows Figure 1 A top view of a mid-plane split-gate MOSFET;

[0019] Figure 3A schematic cross-sectional structure diagram of a semiconductor structure provided in an embodiment of the present application is shown;

[0020] Figure 4 Shows Figure 3 A schematic top view of a semiconductor structure;

[0021] Figure 5 Shows Figure 3 Another schematic top view of the semiconductor structure;

[0022] Figure 6 A schematic cross-sectional structure diagram of another semiconductor structure provided in an embodiment of the present application is shown;

[0023] Figure 7 A schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0024] Figure 8 A cross-sectional view of a structure obtained after an initial epitaxial layer is formed on a substrate according to an embodiment of the present application is shown;

[0025] Fig. 9 A cross-sectional view of a structure obtained after an active region is formed in an initial epitaxial layer according to an embodiment of the present application is shown;

[0026] Fig.10 Shows Fig. 9 Schematic diagram of top view;

[0027] Fig.11 A cross-sectional view of a structure obtained after forming a first barrier layer on an initial epitaxial layer according to an embodiment of the present application is shown;

[0028] Fig.12 Shows Fig.11 Schematic diagram of top view;

[0029] Fig.13 shows a cross-sectional view of a structure obtained after forming a JFET region according to an embodiment of the present application;

[0030] Fig.14 Shows Fig.13 Schematic diagram of top view;

[0031] Fig.15 A cross-sectional view of a structure obtained after forming an initial gate according to an embodiment of the present application is shown;

[0032] Fig.16 Shows Fig.15 Schematic diagram of top view;

[0033] Fig.17A cross-sectional view of a structure obtained after forming a gate according to an embodiment of the present application is shown;

[0034] Fig.18 A cross-sectional view of a structure obtained after forming an initial dielectric layer according to an embodiment of the present application is shown;

[0035] Fig.19 Shows Fig.18 Schematic diagram of top view;

[0036] Fig. 20 A cross-sectional view of a structure obtained after forming a dielectric layer according to an embodiment of the present application is shown;

[0037] Fig.21 Shows Fig. 20 Schematic diagram of top view;

[0038] Fig. 22 A schematic cross-sectional structure diagram of another semiconductor structure provided in an embodiment of the present application is shown.

[0039] The above drawings include the following reference numerals:

[0040] 10. Substrate; 11. Epitaxial layer; 12. Gate; 121. Common part; 122. Split gate; 13. Injection region; 14. Base region; 15. Source region; 16. JFET region; 17. Gate oxide layer; 18. Dielectric layer; 19. Source metal layer; 20. Drain metal layer; 21. Initial epitaxial layer; 22. First barrier layer; 23. Initial gate oxide layer; 24. Initial gate; 25. Initial dielectric layer. DETAILED DESCRIPTION

[0041] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0042] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0043] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0044] As introduced in the background technology, the prior art has the problem of poor reliability of planar split-gate semiconductor structures. To solve the above technical problems, an embodiment of the present application provides a semiconductor structure and a method for manufacturing the same.

[0045] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0046] The embodiment of the present application provides a semiconductor structure, such as Figure 3 and Figure 4 As shown, or as Figure 3 and Figure 5 As shown, the semiconductor structure comprises:

[0047] Substrate 10;

[0048] An epitaxial layer 11 is located on one side surface of the substrate 10;

[0049] A cell structure includes a plurality of active regions and a gate 12, wherein the plurality of active regions are arranged at intervals in the epitaxial layer 11, the active region includes an adjacent injection region 13 and a base region 14, and a source region 15 located in the base region 14, the source region 15 is in contact with the injection region 13, and the side of the active region close to another active region is the side of the base region 14, the gate 12 includes a common portion 121 and a plurality of split gates 122, the common portion 121 and the plurality of split gates 122 are located on a side of the epitaxial layer 11 away from the substrate 10, the plurality of split gates 122 surround the common portion 121 and are all connected to the common portion 121, the orthographic projection of one of the split gates 122 on the epitaxial layer 11 covers a partial surface of the base region 14 away from the substrate 10, the doping type of the base region 14 and the injection region 13 is a first doping type, and the doping type of the source region 15, the epitaxial layer 11 and the substrate 10 is a second doping type.

[0050] Specifically, the side surface of the source region 15 contacts the side surface of the injection region 13. The side surface of the base region 14 away from the injection region 13 serves as the side surface of the active region to which it belongs, and the side surfaces of two adjacent active regions are opposite. The common portion 121 is located in the middle of the plurality of split gates 122, and serves to connect any two of the split gates 122. There are multiple base regions 14 in the cellular structure, and there are multiple split gates 122. The corresponding relationship between the base region 14 and the split gates 122 can be: the orthographic projection of the split gate 122 can cover the surface of the base region 14 away from the substrate 10 one by one; the corresponding relationship between the base region 14 and the split gate 122 can also be: the orthographic projections of multiple split gates 122 cover the surface of one base region 14 away from the substrate 10, for example, the orthographic projections of two split gates 122 correspondingly cover the surface of one base region 14; the corresponding relationship between the base region 14 and the split gate 122 can also be: the partial surface of the base region 14 away from the substrate 10 is covered by the orthographic projection of the split gate 122, and the partial surface of the base region 14 away from the substrate 10 is not covered by the orthographic projection of the split gate 122.

[0051] Through the embodiment, a plurality of spaced active regions are arranged in the epitaxial layer, and the active regions include adjacent injection regions, base regions, and source regions located in the base regions. A gate is arranged on the side of the epitaxial layer away from the substrate, and the gate includes a common portion and a plurality of split gates. The plurality of split gates surround the common portion and are all connected to the common portion, forming a mesh-type gate structure, and the positive projection of a split gate on the epitaxial layer covers a portion of the surface away from the base region. The present application adopts a mesh-type gate structure composed of split gates and common portions. When a split gate is broken, other split gates can still be connected to the gate bus through the common portion, thereby receiving the control signal of the gate, and the problem of the entire gate failing will not occur, which avoids the problems of cracking and degradation of effective shutoff capability caused by the size reduction of the split gate. In other words, the present application can greatly overcome the dilemma that the cell pitch cannot be further reduced due to the minimum process line width limitation of the gate in the existing planar split gate technology; at the same time, the present application can retain the low impedance and high switching speed performance of the planar split gate semiconductor structure, ensuring the reliability of the semiconductor structure and good device performance.

[0052] It should be noted that Figure 3 It is along Figure 4 and Figure 5 A cross-sectional view of the semiconductor structure is obtained by taking the dotted line AA' in FIG.

[0053] At least some of the ends of the plurality of split gates are connected to the gate bus, and since the common portion connects all the split gates, all the split gates can be connected to the gate bus.

[0054] The width of the common portion 121 in a predetermined direction is greater than the width of the split gate 122 in the predetermined direction, and the predetermined direction is perpendicular to the extending direction of the split gate 122 .

[0055] A person skilled in the art can select any suitable material as the substrate material of the present application according to the actual device requirements, such as a silicon substrate, a silicon carbide substrate, a silicon germanium substrate, an SOI substrate or a GOI substrate. Similarly, a person skilled in the art can select any suitable material as the epitaxial layer material of the present application according to the actual device requirements, such as silicon, silicon germanium, silicon carbide, silicon nitride or gallium nitride. The thickness of the epitaxial layer can be 7 to 14 μm, and the doping concentration of the epitaxial layer can be 1e 14 ~1e 18 cm -3 .

[0056] Exemplarily, the base region is a square injection region, and the doping concentration of the base region can be 1e 14 ~1e 17 cm -3 The injection region is a square injection region, and the doping concentration of the injection region can be 1e 16 ~1e 19 cm -3 The source region is a square injection region, and the doping concentration of the source region can be 1e 16 ~1e 19 cm -3 The longitudinal and lateral spacing between the injection region and the base region can be flexibly adjusted according to actual load requirements.

[0057] In some embodiments, the materials of the substrate and the epitaxial layer are both silicon carbide (SiC). The semiconductor structure is a planar gate SiC MOSFET device. The material of the gate may be polysilicon or other semiconductor materials. The split gate is made of the same material as the common portion.

[0058] Exemplarily, the thickness of the gate is 0.3-0.6 μm.

[0059] In actual application, the cell shape of the cell structure can be square, circular, hexagonal, 8-shaped, etc. In the semiconductor structure of the present application, there can be multiple cell structures. The layout of multiple cell structures can be a field-shaped layout, a herringbone-shaped layout, a honeycomb-shaped layout, etc. The spacing between adjacent cells can be adjusted according to the requirements of the actual load, which has great flexibility.

[0060] In the exemplary embodiment of the present application, Figure 4 and Figure 5 As shown in , the cell structure is a square cell. Figure 4 and Figure 5 As shown, the source region 15 at least half surrounds the periphery of the implantation region 13 .

[0061] In the present application, the cell injection adopts a square structure design, and the load capacity of the device can be adjusted by adjusting the spacing between the cells, which has great flexibility in application.

[0062] The present application adopts a combination design of square cells and split gate structures, where the split gate surrounds the square cells. This structure retains the low impedance and high switching speed characteristics of the planar split-gate SIC MOSFET to the greatest extent, while further solving the problem of poor gate reliability caused by the smaller cell pitch and narrower gate.

[0063] Some options include Figure 4 As shown, two split gates 122 correspond to one base region 14, and the orthographic projection of one of the two split gates 122 on the epitaxial layer 11 covers a portion of the surface of the base region 14 away from the substrate 10, and the orthographic projection of the other of the two split gates 122 on the epitaxial layer 11 covers the remaining portion of the surface of the base region 14 away from the substrate 10. In this embodiment, both split gates are connected to a common portion, and when one of the split gates has a problem, the gate control signal can be received through the other split gate, and the problem of all gates corresponding to the channel of the base region failing will not occur, further ensuring the good reliability of the semiconductor structure.

[0064] In some optional solutions, the cell structure further includes: a gate oxide layer 17, which is located on the surface of the epitaxial layer 11 away from the substrate 10, on at least a portion of the surface of the base region 14 away from the substrate 10, and on a portion of the surface of the source region 15 away from the substrate 10, and the gate 12 is located on at least a portion of the surface of the gate oxide layer 17 away from the epitaxial layer 11. That is, the gate oxide layer 17 at most exposes the surface of the injection region 13 away from the substrate 10, the portion of the surface of the base region 14 away from the substrate 10, and the portion of the surface of the source region 15 away from the substrate 10, for example, Figure 4 As shown, the gate oxide layer 17 only exposes the surface of the injection region 13 away from the substrate 10 and the surface of the source region 15 away from the substrate 10. Figure 5 As shown, the gate oxide layer 17 makes the injection region 13 away from the surface of the substrate 10 , the source region 15 away from a portion of the surface of the substrate 10 , and the base region 14 away from a portion of the surface of the substrate 10 exposed.

[0065] According to some other optional embodiments of the present application, Figures 3 to 5As shown, the cell structure further includes: a JFET region 16 located in the epitaxial layer 11, the JFET region 16 is located between any two adjacent base regions 14 and is in contact with each base region 14, and the orthographic projection of the split gate 122 on the epitaxial layer 11 covers a portion of the surface of the base region 14 away from the substrate 10, a portion of the surface of the JFET region 16 away from the substrate 10, and a portion of the surface of the source region 15 away from the substrate 10. In this embodiment, by providing a JFET region between adjacent base regions, the resistance of the JFET region can be effectively reduced, thereby achieving the effect of optimizing the on-resistance of the semiconductor structure.

[0066] In a specific application, the doping types of the JFET region 16 and the epitaxial layer 11 may be the same or different; the doping concentration of the JFET region 16 may be greater than the doping concentration of the epitaxial layer 11 , or less than or equal to the doping concentration of the epitaxial layer 11 .

[0067] Specifically, a channel is formed in a portion of the base region 14 between the source region 15 and the JFET region 16 away from the substrate, and the length of the channel is 0.2-0.8 μm. The doping concentration of the JFET region 16 can be 7.5e 12 ~1.5e 12 cm -3 .

[0068] like Figure 4 and Figure 5 As shown, the gate 12 presents a "mesh" type routing, the split gate 122 between the two lateral source regions 15 (located above the JFET region 16) is separated, the spacing between the split gates 122 is smaller than the width of the JFET region 16, and the total length of the width of the two split gates 122 plus the spacing between them shall not be less than the spacing between the left and right source regions 15. The split gate 122 between the two longitudinal source regions 15 is separated, the spacing between the split gates 122 is smaller than the width of the JFET region 16, and the total length of the width of the two split gates 122 plus the spacing between them shall not be less than the spacing between the upper and lower source regions 15. The thickness of the split gate 122 is adjusted by the longitudinal height between the two injection regions 13 and the base region 14.

[0069] Alternatively, if Figures 3 to 5As shown, the cell structure further includes: a gate oxide layer 17, which is located between the gate 12 and the epitaxial layer 11, and the gate oxide layer 17 is located on the surface of the JFET region 16 away from the substrate 10. The gate oxide layer isolates the gate from the active region, preventing the current from flowing directly from the gate into the active region, and ensuring the normal operation of the semiconductor structure; a capacitor structure is formed between the gate oxide layer, the gate and the active region. When the gate voltage changes, the capacitor will store charge. This capacitor effect makes the semiconductor structure have a faster response speed, which helps to improve the performance of the semiconductor structure; another important function of the gate oxide layer is to control the conductive channel of the semiconductor structure through an electric field. When a sufficient voltage is applied to the gate, a conductive channel will be formed under the gate oxide layer, allowing current to flow from the source to the drain. By adjusting the gate voltage, the conductivity of the channel can be controlled, thereby realizing the switch control of the semiconductor structure.

[0070] In a specific embodiment, the thickness of the gate oxide layer is 300 to 800 angstroms.

[0071] The material of the gate oxide layer includes but is not limited to: silicon oxide, high-K dielectric layer, silicon nitride, aluminum oxide and the like.

[0072] like Figures 3 to 5 As shown, the orthographic projection of the gate 12 on the epitaxial layer 11 is located in the orthographic projection of the gate oxide layer 17 on the epitaxial layer 11, that is, the gate oxide layer 17 is also located at least on the partial surface of the base region 14 away from the substrate 10 and on the partial surface of the source region 15 away from the substrate 10.

[0073] The thickness of the gate oxide layer located on the surface of the JFET region 16 away from the substrate 10 may be greater than the thickness of the gate oxide layer at other locations, which can further increase the reliability of the gate oxide layer.

[0074] Alternatively, if Figure 6 As shown, the semiconductor structure also includes: a dielectric layer 18, located on the surface of the gate 12 away from the epitaxial layer 11, on the side wall of the gate 12, and on the surface of the gate oxide layer 17 away from the epitaxial layer 11; a source metal layer 19, located on the surface of the injection region 13 away from the substrate 10, on the partial surface of the source region 15 away from the substrate 10, on the surface of the dielectric layer 18 away from the epitaxial layer 11, and on the side wall of the dielectric layer 18; a drain metal layer 20, located on the surface of the substrate 10 away from the epitaxial layer 11.

[0075] In the described embodiment, the dielectric layer serves to isolate the gate and source metal layers, and the dielectric layer also serves to protect the gate, gate oxide layer and active area; the source metal layer contacts the source area and the injection area respectively to form an ohmic contact, which can reduce the contact resistance of the semiconductor structure, reduce the power loss of the semiconductor structure and improve the efficiency of the semiconductor structure.

[0076] Specifically, the thickness of the dielectric layer may be 0.7-1.4 μm. The material of the dielectric layer includes but is not limited to low dielectric constant materials such as SIOF, TEOS, MSQ, BPSG, or a combination thereof. In the present application, a combination of BPSG and TEOSD is used as the material of the dielectric layer.

[0077] The materials of the source metal layer and the drain metal layer are independently selected from one or more alloys of titanium, nickel, silver, aluminum, copper, palladium and gold. The thickness of the source metal layer can be 3 to 6 μm. The thickness of the drain metal layer can be 1 to 3 μm.

[0078] The semiconductor structure of the present application may be a silicon carbide MOSFET power device, specifically a planar silicon carbide MOSFET power device.

[0079] Figure 7 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application. Figure 7 As shown, the method comprises the following steps:

[0080] Step S201, as Figure 8 As shown, a substrate 10 is provided;

[0081] Step S202, forming an initial epitaxial layer 21 on one side surface of the substrate 10, and obtaining Figure 8 The structure shown;

[0082] Step S203, as Fig.13 and Fig.14 As shown, a plurality of active regions are formed at least in the initial epitaxial layer 21, and the remaining initial epitaxial layer 21 forms an epitaxial layer 11, wherein the plurality of active regions are arranged at intervals in the epitaxial layer 11, wherein the active regions include adjacent implantation regions 13 and base regions 14 and a source region 15 located in the base region 14, wherein the side of the active region close to another active region is the side of the base region 14, the doping type of the base region 14 and the implantation region 13 is a first doping type, and the doping type of the source region 15, the epitaxial layer 11 and the substrate 10 is a second doping type;

[0083] Specifically, the side surface of the source region 15 contacts the side surface of the injection region 13. The side surface of the base region 14 away from the injection region 13 serves as the side surface of the active region to which it belongs, and the side surfaces of two adjacent active regions are opposite to each other.

[0084] Step S204, as Fig.17 As shown, a gate 12 is formed on the side of the epitaxial layer 11 away from the substrate 10, and the orthographic projection of the gate on the epitaxial layer is as shown in FIG. Figure 4 or Figure 5 As shown, the gate 12 includes a common portion 121 and a plurality of split gates 122, the common portion 121 and the plurality of split gates 122 are located on a side of the epitaxial layer 11 away from the substrate 10, the plurality of split gates 122 surround the common portion 121 and are all connected to the common portion 121, and the orthographic projection of a split gate 122 on the epitaxial layer 11 covers a portion of the surface of the base region 14 away from the substrate 10.

[0085] Specifically, the common portion 121 is located in the middle of the plurality of split gates 122, and serves to connect any two of the split gates 122. There are a plurality of base regions 14 in the cell structure, and a plurality of split gates 122. The corresponding relationship between the base region 14 and the split gates 122 may be: the orthographic projections of the split gates 122 may cover the surface of the base region 14 away from the substrate 10 one by one; the corresponding relationship between the base region 14 and the split gates 122 may also be: the orthographic projections of a plurality of the split gates 122 cover the surface of one base region 14 away from the substrate 10, for example, the orthographic projections of two split gates 122 cover the surface of one base region 14 correspondingly; the corresponding relationship between the base region 14 and the split gates 122 may also be: the partial surface of the base region 14 away from the substrate 10 is covered by the orthographic projection of the split gates 122, and the partial surface of the base region 14 away from the substrate 10 is not covered by the orthographic projection of the split gates 122.

[0086] According to the embodiment, a substrate is first provided, and then an initial epitaxial layer is formed on a surface of one side of the substrate, and a plurality of spaced active regions are formed in the initial epitaxial layer, and an initial epitaxial layer having active regions is formed to form an epitaxial layer, wherein the active regions include adjacent injection regions, a base region, and a source region located in the base region, and a gate is formed on a side of the epitaxial layer away from the substrate, wherein the gate includes a common portion and a plurality of split gates, wherein the plurality of split gates surround the common portion and are all connected to the common portion, forming a mesh-type gate structure, and the positive projection of a split gate on the epitaxial layer covers a portion of the surface of the base region away from the said portion. The present application adopts a mesh gate structure composed of a split gate and a common part. When a split gate is broken, other split gates can still be connected to the gate bus through the common part, thereby receiving the control signal of the gate, and the problem of the entire gate failing will not occur. It avoids the problems of cracking and degradation of effective shutdown capability caused by the size reduction of the split gate. In other words, the present application can greatly overcome the dilemma of the existing planar split gate technology that the cell pitch cannot be further reduced due to the minimum process line width limitation of the gate; at the same time, the present application can retain the low impedance and high switching speed performance of the planar split gate semiconductor structure, ensuring the reliability of the semiconductor structure and good device performance.

[0087] In an optional solution, a plurality of active regions are formed at least in the initial epitaxial layer, including: Figure 8 , Fig. 9 and Fig.10 As shown, a plurality of active regions are formed in the initial epitaxial layer 21; Fig. 9 , Fig.10 , Fig.11 and Fig.12 As shown, a first mask and a second mask are stacked on a side of the initial epitaxial layer 21 away from the substrate 10, and a first barrier layer 22 is formed on the surface of the initial epitaxial layer 21 away from the substrate 10 using a double-layer mask technology. The first barrier layer 22 exposes the initial epitaxial layer 21 between any two adjacent base regions 14. The first mask is a mask used in the process of forming the base region 14, and the second mask is a mask used in the process of forming the gate 12. Fig.11 , Fig.12 , Fig.13 and Fig.14As shown, with the first barrier layer 22 as a mask, ion implantation is performed on the initial epitaxial layer 21 having the active region formed therein to form a JFET region 16 in the initial epitaxial layer 21, the initial epitaxial layer 21 having the JFET region 16 forms the epitaxial layer 11, and the orthographic projection of the split gate 122 on the epitaxial layer 11 covers a portion of the surface of the base region 14 away from the substrate 10, a portion of the surface of the JFET region 16 away from the substrate 10, and a portion of the surface of the source region 15 away from the substrate 10; the first barrier layer 22 is removed.

[0088] In the described embodiment, the gate mask and the base mask are reused to achieve precise ion implantation in the JFET region through double-layer mask technology, which can effectively reduce the resistance of the JFET region without affecting the carrier concentration in other regions, thereby optimizing the on-resistance of the device and reducing the power consumption of the device. While achieving the above effects, there is no need to add additional masks, saving the cost of the manufacturing process.

[0089] In the process of forming the first barrier layer, the first sub-barrier layer can be formed on the base region by using the first mask, and then the second sub-barrier layer can be formed on the gate region by using the second mask. The first sub-barrier layer and the second sub-barrier layer constitute the first barrier layer, and the injection window left by the first barrier layer is the window of the JFET region. The total thickness of the first barrier layer is between 2.5 and 5 μm.

[0090] In addition, multi-gradient implantation is used in the process of ion implantation to form the JFET region.

[0091] In an optional embodiment, a plurality of active regions are formed in the initial epitaxial layer, comprising: setting the first mask on the side of the initial epitaxial layer away from the substrate, and using the first mask to form a second barrier layer on the surface of the initial epitaxial layer away from the substrate, the second barrier layer exposing part of the surface of the initial epitaxial layer; using the second barrier layer as a mask, ion implanting the initial epitaxial layer to obtain a plurality of initial base regions arranged at intervals; ion implanting a part of the initial base region away from the adjacent initial base region to form the implantation region in the initial base region; ion implanting the initial base region to form the source region adjacent to the implantation region in the initial base region, the remaining initial base region forming the base region, the source region being on the side of the implantation region close to the adjacent active region; removing the second barrier layer. The first mask can realize accurate ion implantation of the initial base region to ensure the position accuracy of the initial base region, and then by implanting ions into the initial base region, an implantation region and a source region are obtained, and the remaining initial base region forms the base region.

[0092] Specifically, both the process of forming the implantation region and the process of forming the source region can be achieved by forming a blocking layer through a mask.

[0093] According to some further embodiments of the present application, after removing the first barrier layer and before forming the gate on the side of the epitaxial layer away from the substrate, the method further includes: annealing the structure formed with the JFET region; forming a gate oxide layer on the surface of the epitaxial layer away from the substrate, the gate oxide layer being located on the surface of the JFET region away from the substrate. In the embodiment, the high temperature annealing can activate the injected ions and repair the lattice damage during the ion implantation process. The gate is isolated from the active area by forming the gate oxide layer to prevent the current from flowing directly from the gate into the active area, thereby ensuring the normal operation of the semiconductor structure; a capacitor structure is formed between the gate oxide layer and the gate and the active area. When the gate voltage changes, the capacitor will store charge. This capacitor effect makes the semiconductor structure have a faster response speed, which helps to improve the performance of the semiconductor structure; another important function of the gate oxide layer is to control the conductive channel of the semiconductor structure through an electric field. When a sufficient voltage is applied to the gate, a conductive channel will be formed under the gate oxide layer, allowing current to flow from the source to the drain. By adjusting the gate voltage, the conductivity of the channel can be controlled, thereby realizing the switch control of the semiconductor structure.

[0094] Specifically, the annealing temperature can be controlled between 1700° C. and 1800° C., and the annealing time can be controlled between 30 and 60 minutes.

[0095] In some embodiments, the gate oxide layer may be formed by thermally oxidizing the epitaxial layer, or by a deposition method.

[0096] In addition, after forming a gate oxide layer on a portion of the surface of the epitaxial layer away from the substrate, the method further comprises: annealing the structure formed with the gate oxide layer in a nitrogen-containing atmosphere, wherein the annealing temperature is between 1000° C. and 1100° C., and the time is between 30 and 60 minutes. The nitrogen-containing atmosphere helps to reduce interface state defects between the epitaxial layer and the gate oxide layer.

[0097] After forming a gate on the side of the epitaxial layer away from the substrate, the method further comprises: forming an initial dielectric layer on the exposed surface of the gate, the exposed surface of the gate oxide layer, and the exposed surface of the active region away from the substrate by a deposition method; etching the initial dielectric layer so that the surface of the injection region away from the substrate and a portion of the surface of the source region away from the substrate are exposed, and the remaining initial dielectric layer forms a dielectric layer; Fig. 20 , Fig.21 and Fig. 22As shown, metal deposition is performed on the exposed surface of the dielectric layer 18, the surface of the injection region 13 away from the substrate 10, and the partial surface of the source region 15 away from the substrate 10 to form a source metal layer 19; metal deposition is performed on the surface of the substrate 10 away from the epitaxial layer 11 to form a drain metal layer 20.

[0098] Specifically, the gate oxide layer and the dielectric layer can be formed simultaneously or in steps. Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22 As shown, first, an initial gate oxide layer 23 is formed on the surface of the active region away from the substrate 10 and on the surface of the JFET region 16 away from the substrate 10; an initial gate 24 is formed on the surface of the initial gate oxide layer 23 away from the epitaxial layer 11 using the second mask; a portion of the initial gate 24 is removed to obtain the gate 12; an initial dielectric layer 25 is formed on the exposed surface of the gate 12 and on the exposed surface of the initial gate oxide layer 23; a portion of the initial gate oxide layer 23 and the initial dielectric layer 25 are removed to expose the surface of the injection region 13 away from the substrate 10 and a portion of the surface of the source region 15 away from the substrate 10, and the remaining initial dielectric layer 25 forms the dielectric layer 18, and the remaining initial gate oxide layer 23 forms the gate oxide layer 17.

[0099] In an exemplary embodiment, the first doping type is P type, and the second doping type is N type. The injected N type carriers are mainly elements of group V, such as N, P, As, etc., and the injected P type carriers are mainly elements of group III, such as B, Al, In, etc. At the same time, the injection of N type carriers and P type carriers can be injected once or in batches, and the energy and dosage of each injection can be the same or different.

[0100] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0101] From the above description, it can be seen that the embodiments described in this application achieve the following technical effects:

[0102] 1) In the semiconductor structure of the present application, a plurality of spaced active regions are arranged in the epitaxial layer, and the active regions include adjacent injection regions, base regions, and source regions located in the base regions. A gate is arranged on the side of the epitaxial layer away from the substrate, and the gate includes a common portion and a plurality of split gates. The plurality of split gates surround the common portion and are all connected to the common portion, forming a mesh-type gate structure, and the positive projection of a split gate on the epitaxial layer covers a portion of the surface away from the base region. The present application adopts a mesh-type gate structure composed of split gates and common portions. When a split gate is broken, other split gates can still be connected to the gate bus through the common portion, thereby receiving the control signal of the gate, and the problem of the entire gate failing will not occur, which not only avoids the problems of cracking and degradation of effective shutoff capability caused by the size reduction of the split gate, but also avoids the problems of cracking and degradation of effective shutoff capability caused by the size reduction of the split gate. In other words, the present application can greatly overcome the dilemma that the cell pitch cannot be further reduced due to the minimum process line width limitation of the gate in the existing planar split gate technology; at the same time, the present application can retain the low impedance and high switching speed performance of the planar split gate semiconductor structure, ensuring the reliability of the semiconductor structure and good device performance.

[0103] 2) In the manufacturing method of the semiconductor structure of the present application, a substrate is first provided, and then an initial epitaxial layer is formed on the surface of one side of the substrate, and a plurality of spaced active regions are formed in the initial epitaxial layer, and an initial epitaxial layer with active regions is formed to form an epitaxial layer, the active region includes an adjacent injection region, a base region and a source region located in the base region, and a gate is formed on the side of the epitaxial layer away from the substrate, the gate includes a common portion and a plurality of split gates, the plurality of split gates surround the common portion and are all connected to the common portion, forming a mesh-type gate structure, and a split gate is positively projected on the epitaxial layer to cover a portion of the surface of the base region away from the said portion. The present application adopts a mesh gate structure composed of a split gate and a common part. When a split gate is broken, other split gates can still be connected to the gate bus through the common part, thereby receiving the control signal of the gate, and the problem of the entire gate failing will not occur. It avoids the problems of cracking and degradation of effective shutdown capability caused by the size reduction of the split gate. In other words, the present application can greatly overcome the dilemma of the existing planar split gate technology that the cell pitch cannot be further reduced due to the minimum process line width limitation of the gate; at the same time, the present application can retain the low impedance and high switching speed performance of the planar split gate semiconductor structure, ensuring the reliability of the semiconductor structure and good device performance.

[0104] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that: include: substrate; An epitaxial layer, located on one side surface of the substrate; A cell structure includes a plurality of active regions and a gate, wherein the plurality of active regions are arranged at intervals in the epitaxial layer, the active region includes an adjacent injection region and a base region, and a source region located in the base region, the source region is in contact with the injection region, the side of the active region close to another active region is the side of the base region, the gate includes a common portion and a plurality of split gates, the common portion and the plurality of split gates are located on a side of the epitaxial layer away from the substrate, the plurality of split gates surround the common portion and are all connected to the common portion, the orthographic projection of one split gate on the epitaxial layer covers a partial surface of the base region away from the substrate, the doping type of the base region and the injection region is a first doping type, and the doping type of the source region, the epitaxial layer and the substrate is a second doping type.

2. The semiconductor structure according to claim 1, characterized in that: The two split gates correspond to one base region, the orthographic projection of one of the two split gates in the epitaxial layer covers a portion of the surface of the base region away from the substrate, and the orthographic projection of the other of the two split gates in the epitaxial layer covers the remaining portion of the surface of the base region away from the substrate.

3. The semiconductor structure according to claim 1, characterized in that: The cellular structure also includes: A JFET region is located in the epitaxial layer, the JFET region is located between any two adjacent base regions and is in contact with each base region respectively, and the orthographic projection of the split gate on the epitaxial layer covers a partial surface of the base region away from the substrate, a partial surface of the JFET region away from the substrate, and a partial surface of the source region away from the substrate.

4. The semiconductor structure according to claim 3, characterized in that: The cellular structure also includes: A gate oxide layer is located between the gate and the epitaxial layer, and the gate oxide layer is located on a surface of the JFET region away from the substrate.

5. The semiconductor structure according to claim 4, characterized in that: The semiconductor structure further comprises: A dielectric layer is located on a surface of the gate away from the epitaxial layer, on a sidewall of the gate, and on a surface of the gate oxide layer away from the epitaxial layer; A source metal layer is located on the surface of the implantation region away from the substrate, on a portion of the surface of the source region away from the substrate, on the surface of the dielectric layer away from the epitaxial layer, and on the sidewall of the dielectric layer; The drain metal layer is located on the surface of the substrate away from the epitaxial layer.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The cell structure is a square cell.

7. A method for manufacturing a semiconductor structure according to any one of claims 1 to 6, characterized in that: include: providing a substrate; forming an initial epitaxial layer on a surface of one side of the substrate; A plurality of active regions are formed at least in the initial epitaxial layer, and the remaining initial epitaxial layer forms an epitaxial layer, wherein the plurality of active regions are arranged at intervals in the epitaxial layer, wherein the active region comprises an adjacent implantation region and a base region, and a source region located in the base region, wherein the source region contacts the implantation region, and a side of the active region close to another active region is a side of the base region, the base region and the implantation region are doped with a first doping type, and the source region, the epitaxial layer and the substrate are doped with a second doping type; A gate is formed on a side of the epitaxial layer away from the substrate, the gate comprising a common portion and a plurality of split gates, the common portion and the plurality of split gates are located on a side of the epitaxial layer away from the substrate, the plurality of split gates surround the common portion and are all connected to the common portion, and the orthographic projection of a split gate on the epitaxial layer covers a partial surface of the base region away from the substrate.

8. The method according to claim 7, characterized in that A plurality of active regions are formed at least in the initial epitaxial layer, including: forming a plurality of active regions in the initial epitaxial layer; A first mask and a second mask are stacked on a side of the initial epitaxial layer away from the substrate, and a first barrier layer is formed on a surface of the initial epitaxial layer away from the substrate using a double-layer mask technology, wherein the first barrier layer exposes the initial epitaxial layer between any two adjacent base regions, the first mask is a mask used in the process of forming the base region, and the second mask is a mask used in the process of forming the gate; Using the first barrier layer as a mask, ion implantation is performed on the initial epitaxial layer having the active region formed therein to form a JFET region in the initial epitaxial layer, wherein the initial epitaxial layer having the JFET region formed therein forms the epitaxial layer, and the orthographic projection of the split gate on the epitaxial layer covers a portion of the surface of the base region away from the substrate, a portion of the surface of the JFET region away from the substrate, and a portion of the surface of the source region away from the substrate; The first barrier layer is removed.

9. The method according to claim 8, characterized in that Forming a plurality of active regions in the initial epitaxial layer comprises: Disposing the first mask on a side of the initial epitaxial layer away from the substrate, and using the first mask to form a second barrier layer on a surface of the initial epitaxial layer away from the substrate, wherein the second barrier layer exposes a portion of the surface of the initial epitaxial layer; Using the second barrier layer as a mask, ion implantation is performed on the initial epitaxial layer to obtain a plurality of initial base regions spaced apart from each other; Performing ion implantation on a partial region of the initial base region away from the adjacent initial base region to form the implantation region in the initial base region; Performing ion implantation on the initial base region to form the source region adjacent to the implantation region in the initial base region, and the remaining initial base region forms the base region, wherein the source region is located on a side of the implantation region close to the adjacent active region; The second barrier layer is removed.

10. The method according to claim 8, characterized in that After removing the first barrier layer and before forming a gate on a side of the epitaxial layer away from the substrate, the method further includes: performing an annealing process on the structure having the JFET region formed therein; A gate oxide layer is formed on a portion of the surface of the epitaxial layer away from the substrate, and the gate oxide layer is located on a surface of the JFET region away from the substrate.

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