Integrated circuit chip and its manufacturing method and application
By setting up a spaced dielectric layer and an upper dielectric layer in the integrated circuit chip, selective removal is used to utilize the etch resistance of different materials, the problem of increasing parasitic capacitance caused by the large thickness of the passivation layer is solved, and the noise characteristics and overall performance of the device are improved.
Patent Information
- Application Number
- CN202411773475.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-04-08
AI Technical Summary
The passivation layer used in the prior art in integrated circuit chips has a large thickness, resulting in an increase in parasitic capacitance and an increase in noise coefficient, which limits the improvement of device performance.
By setting a spaced dielectric layer and an upper dielectric layer in the integrated circuit chip, selective removal is performed using the etch resistance of different materials, reducing the dielectric layer thickness of the active region and reducing parasitic capacitance.
It effectively reduces the parasitic capacitance between the gate and source and drain electrodes, and improves the noise characteristics and overall performance of the device.
Smart Images
Figure CN119789508A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an integrated circuit chip and a manufacturing method and application thereof. Background Art
[0002] As the main component of 5G RF chips, the GaAs pseudomorphic high electron mobility transistor (pHEMT) low noise amplifier (LNA) has low noise characteristics. The gate (Gate), which plays a decisive role, needs a passivation layer to protect the reliability of the transistor device due to the characteristics of the small line width structure. However, with the deposition of the passivation layer, parasitic capacitance will be formed between the gate and the source and drain (Source & Drain), resulting in a decrease in the dielectric frequency (Ft) of the current gain, and ultimately an increase in the noise factor of the amplifier.
[0003] At present, the industry uses plasma enhanced chemical vapor deposition (PECVD) technology to cover the entire surface with a passivation layer film such as silicon nitride after metal evaporation to protect the epitaxial layer and the metal from oxidation and corrosion by external environmental factors such as water vapor. Due to the accumulation of processes of common devices such as capacitors and inductors in the production of integrated circuit chips, a thicker silicon nitride film will eventually be formed near the gate, resulting in a larger noise coefficient. However, for multi-layer accumulations of the same material, the etching removal method cannot achieve uniform thinning of the material, resulting in uneven thickness of the remaining passivation layer material, and even damaged locations, causing reliability failure of the integrated circuit. Therefore, the passivation layer produced by the prior art is usually not thinned, and the thickness is relatively large, which limits the improvement of device performance. Summary of the invention
[0004] The object of the present invention is to provide an integrated circuit chip and a manufacturing method and application thereof, so as to improve the performance of the device.
[0005] In order to achieve the above purpose, the technical solution of the present invention is:
[0006] An integrated circuit chip comprises a semiconductor structure, wherein the semiconductor structure has an active region and a capacitor region, wherein the active region is provided with a source electrode, a drain electrode and a gate electrode, wherein the gate electrode is located between the source electrode and the drain electrode; a first dielectric layer, a first metal layer, a spacer dielectric layer, an upper dielectric layer and a second metal layer are sequentially arranged on the semiconductor structure, wherein the spacer dielectric layer and the upper dielectric layer are made of different dielectric materials, wherein
[0007] The first dielectric layer covers the source, drain, gate and the surface of the semiconductor structure; the first metal layer includes a first connection metal located in the active area and a lower plate located in the capacitor area; the spacing dielectric layer is arranged on the first metal layer and the first dielectric layer; the upper dielectric layer is arranged on the spacing dielectric layer and is open to the active area, and the edge of the opening is located outside the source and drain; the second metal layer includes a second connection metal located in the active area and an upper plate located in the capacitor area, and the capacitor dielectric layer between the upper plate and the lower plate includes a stack of spacing dielectric layer / upper dielectric layer.
[0008] Optionally, the materials of the spacer dielectric layer and the upper dielectric layer have different etching resistances.
[0009] Optionally, the material of the first dielectric layer is silicon nitride with a thickness of 10 to 100 nm. The contact between silicon nitride and the gate can effectively protect the gate from oxidation while suppressing the increase of surface defects. Silicon nitride has high hardness and strength. When the film thickness is too thin, it is prone to brittle fracture and loses its protective effect. Therefore, a thickness of more than 10 nm is selected to ensure the toughness and uniformity of the silicon nitride film. In addition, the first layer of silicon nitride does not require too strong protection capabilities. In order to reduce the parasitic capacitance value, a thinner thickness is generally used. Therefore, the upper limit positioning of 100 nm is selected here.
[0010] Optionally, the material of the spacer dielectric layer is silicon oxide, aluminum oxide or phosphosilicate glass, with a thickness of 5-100nm. Taking aluminum oxide as an example, it is necessary to ensure uniform coverage of the spacer dielectric layer to ensure that the upper dielectric layer and the lower dielectric layer can be effectively separated during the etching process. The spacer dielectric layer preferably uses a material with a relatively high dielectric constant, so it is preferred to have a film thickness as thin as possible under the premise of ensuring coverage. Here, 5-100nm is selected. Dielectric layers such as aluminum oxide can ensure coverage in a thinner state, so a lower lower limit value will be selected.
[0011] Optionally, the material of the upper dielectric layer is silicon nitride with a thickness of 100 to 800 nm. This layer of silicon nitride is mainly used as a capacitor dielectric layer, so it needs to be thick enough to ensure that the capacitance per unit area of the capacitor meets the use requirements and ensures that the capacitance uniformity is good and the capacitance value is stable. Therefore, the thickness is selected to be above 100 nm.
[0012] Optionally, the first connection metal includes a first source connection metal and a first drain connection metal, and the first source connection metal and the first drain connection metal respectively penetrate the first dielectric layer and are connected to the source and the drain; the second connection metal is used for leading out the first source connection metal and / or the first drain connection metal, and when leading out, the second connection metal penetrates the spacing dielectric layer and is connected to the first source connection metal and / or the first drain connection metal.
[0013] In one embodiment, the second connection metal includes a second source connection metal and a second drain connection metal, and the second source connection metal and the second drain connection metal respectively penetrate the spacing dielectric layer and are connected to the first source connection metal and the first drain connection metal.
[0014] In one embodiment, the active area has multiple gates, multiple sources and a common drain located between the gates, and the second connection metal includes a second source connection metal and a source bridge metal. The source bridge metal connects two adjacent second source connection metals to form a bridge structure.
[0015] Optionally, a second dielectric layer is further included, and the second dielectric layer is arranged between the first dielectric layer and the spacing dielectric layer. The capacitor dielectric layer between the upper plate and the lower plate includes a stack of separated second dielectric layer / spacer dielectric layer / upper dielectric layer.
[0016] Optionally, the second dielectric layer is made of silicon nitride and has a thickness of 10-100 nm.
[0017] Optionally, the first connection metal includes a first source connection metal and a first drain connection metal, and the first source connection metal and the first drain connection metal respectively penetrate the first dielectric layer and are connected to the source and the drain; the second connection metal is used for leading out the first source connection metal and / or the first drain connection metal, and when leading out, the second connection metal penetrates the spacing dielectric layer and the second dielectric layer and is connected to the first source connection metal and / or the first drain connection metal.
[0018] In one embodiment, the second connection metal includes a second source connection metal and a second drain connection metal, and the second source connection metal and the second drain connection metal respectively penetrate the spacing dielectric layer and the second dielectric layer to connect with the first source connection metal and the first drain connection metal.
[0019] Optionally, the semiconductor structure further has a resistance region, on which a thin film resistor located on the first dielectric layer is disposed; the first metal layer further includes a first lead-out structure located in the resistance region, and the first lead-out structure is in contact with the thin film resistor.
[0020] Optionally, the second metal layer further includes a second lead-out structure located in the resistance region, and the second lead-out structure penetrates the upper dielectric layer, the second dielectric layer and the spacing dielectric layer and is connected to the first lead-out structure.
[0021] Optionally, the active region forms a pHEMT device or a HEMT device.
[0022] A method for manufacturing an integrated circuit chip, comprising the following steps:
[0023] 1) providing a semiconductor structure, the semiconductor structure having an active region and a capacitor region, wherein a source electrode, a drain electrode and a gate electrode are disposed on the active region, and the gate electrode is located between the source electrode and the drain electrode; depositing a first dielectric layer covering the surface of the semiconductor structure, the source electrode, the drain electrode and the gate electrode, and etching openings in the first dielectric layer on the source electrode and the drain electrode;
[0024] 2) forming a patterned first metal layer, wherein the first metal layer includes a first connection metal located in the active area and a lower electrode located in the capacitor area;
[0025] 3) depositing a spacer dielectric layer;
[0026] 4) depositing an upper dielectric layer, wherein the upper dielectric layer and the spacer dielectric layer are made of different materials;
[0027] 5) etching the upper dielectric layer to form an opening in the active area, with the edge of the opening being located outside the source and drain electrodes;
[0028] 6) etching a hole in the dielectric layer on the first metal layer outside the capacitor region; the dielectric layer refers to the dielectric material covering the first metal layer; for the active region, the dielectric layer here includes the first dielectric layer; for other component placement regions outside the active region, the dielectric layer here includes the upper dielectric layer and the first dielectric layer;
[0029] 7) Forming a patterned second metal layer, the second metal layer includes a second connection metal located in the active area and an upper plate located in the capacitor area, and the capacitor dielectric layer between the upper plate and the lower plate includes a stack of a spacer dielectric layer / an upper dielectric layer.
[0030] Optionally, the materials of the spacer dielectric layer and the upper dielectric layer have different etching resistances, and in step 6), the upper dielectric layer is selectively removed.
[0031] Optionally, between step 2) and step 3), a step of depositing a second dielectric layer is also included; in step 6), the capacitor dielectric layer between the upper plate and the lower plate includes a stack of second dielectric layer / spacer dielectric layer / upper dielectric layer.
[0032] Optionally, the semiconductor structure further has a resistance region, and between step 1) and step 2), a step of forming a thin film resistor on the resistance region is also included; in step 3), the first metal layer further includes a first lead-out structure located in the resistance region.
[0033] Optionally, in step 5), the upper dielectric layer above the first lead-out structure is etched simultaneously to form a lead-out hole; in step 6), the second metal layer also includes a second lead-out structure located in the resistance area, and the second lead-out structure is connected to the first lead-out structure through the lead-out hole.
[0034] A radio frequency module comprises the above-mentioned integrated circuit chip, wherein the active area is used for a low noise amplifier in the radio frequency module.
[0035] The beneficial effects of the present invention are:
[0036] 1) In an integrated circuit chip, the thickness of the dielectric layer in the active area is reduced without affecting the performance requirements of the passive area device, the parasitic capacitance between the gate and the source and drain electrodes is reduced, and the noise characteristics of the device and other performance are improved;
[0037] 2) Since the thickness of the capacitor dielectric layer is closely related to the capacitance, its thickness cannot be reduced. By isolating the thick dielectric layer serving as the capacitor dielectric layer from the previous layer with a spacing dielectric layer made of different materials, the difference in material properties is utilized to facilitate the removal of subsequent dielectric layers in the active area, thereby preventing the thickness of the dielectric layer in the active area from being affected by other processes and increasing.
[0038] Other features and advantages of the present invention will be set forth in the following description, and in part will be apparent from the description, or may be learned by practicing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 is a schematic structural diagram of the integrated circuit chip of Example 1;
[0040] Figure 2(a) to Figure 2(f) It is a schematic diagram of the structure obtained by each step of the method for manufacturing the integrated circuit chip of Example 1;
[0041] Figure 3 is a schematic structural diagram of an integrated circuit chip of Example 2;
[0042] Figure 4(a) to Figure 4(g) A schematic diagram of the structure obtained by each step of the method for manufacturing an integrated circuit chip of Example 2;
[0043] Figure 5 is a schematic structural diagram of an integrated circuit chip of Example 3;
[0044] Figure 6 Schematic diagram of the structure of the active area A of the integrated circuit chip of Example 4. DETAILED DESCRIPTION
[0045] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The various drawings of the present invention are only for illustration to make it easier to understand the present invention, and the specific proportions can be adjusted according to design requirements. The upper and lower relationships of the relative elements and the definitions of the front / back in the figures described in the text should be understood by those skilled in the art to refer to the relative positions of the components, so they can all be flipped to present the same components, which should all fall within the scope disclosed in this specification.
[0046] Example 1
[0047] refer to Figure 1 The integrated circuit chip of embodiment 1 includes a semiconductor structure 1, which has an active area A and a capacitor area B. The active area A is provided with a source S, a drain D and a gate G, and the gate G is located between the source S and the drain D. A first dielectric layer 2, a first metal layer 3, a spacing dielectric layer 4, an upper dielectric layer 5 and a second metal layer 6 are sequentially provided on the semiconductor structure 1. The first dielectric layer 2 covers the source S, the drain D, the gate G and the exposed surface of the semiconductor structure 1. The first metal layer 3 includes a first connection metal (specifically including a first source connection metal 31 and a first drain connection metal 32) located in the active area A and a lower electrode 33 located in the capacitor area B. The spacing dielectric layer 4 covers the first metal layer 3 and the first dielectric layer 2. The upper dielectric layer 5 covers the spacing dielectric layer 4 and is open to the active area A, and the edge of the opening a is located outside the source S and the drain D, so that the upper dielectric layer 5 covers other areas including the capacitor area B but does not cover the active area A. The second metal layer 6 includes a second connection metal (specifically including a second source connection metal 61 and a second drain connection metal 62) located in the active area A and an upper plate 63 located in the capacitor area B. In the capacitor area B, the capacitor structure formed by the upper plate 33, the lower plate 63 and the dielectric layer sandwiched therebetween is located on the first dielectric layer 2, and the capacitor dielectric layer is a stack of the spacer dielectric layer 4 / upper dielectric layer 5; in the active area A, the dielectric layer covering the surface of the gate G and the area between the gate G and the source S and the drain D is a stack of the first dielectric layer 2 / spacer dielectric layer 4.
[0048] Among them, the spacing dielectric layer 4 and the upper dielectric layer 5 and the first dielectric layer 2 are made of different dielectric materials. Silicon nitride has the advantages of strong barrier ability to water vapor and ions, good packaging protection performance, and can provide a good dielectric constant for capacitor devices. Therefore, the first dielectric layer 2 is preferably made of silicon nitride, and the thickness is 10-100nm (preferably 50nm) to meet the effect that the epitaxial layer and the metal are not oxidized and corroded by environmental factors such as external water vapor. As the main material of the capacitor dielectric, the upper dielectric layer 5 is preferably made of silicon nitride, and its thickness determines the size of the capacitor. The thickness is 100-800nm (preferably 165nm) to meet the performance requirements of the capacitor device. The materials selected for the spacing dielectric layer 4 include silicon oxide, aluminum oxide or phosphorus silicon glass, etc., and the thickness is 5-100nm (preferably 8nm, 5nm, etc.) to meet the requirements of isolating the upper dielectric layer 5 and the first dielectric layer 2. Taking the spacer dielectric layer 4 as aluminum oxide as an example, aluminum oxide has different etching resistance from silicon nitride, so the upper dielectric layer 5 of the active area A can be removed by utilizing the etching selectivity between different materials, and the total thickness of the dielectric layer covering the gate G and the nearby surface can be controlled to be about within the range.
[0049] The semiconductor structure of this embodiment may include a plurality of semiconductor layers disposed on a substrate. In a specific embodiment, the integrated circuit chip includes a high electron mobility transistor structure, and the semiconductor layer may include a buffer layer, a channel layer, a barrier layer, a barrier layer (e.g., a Schottky barrier layer), an isolation layer, a cap layer, any suitable layer or a combination of the foregoing, but is not limited thereto. A two-dimensional electron gas (two-dimensional electron gas, referred to as 2DEG) may be present approximately at the interface between the channel layer and the isolation layer. The material of the semiconductor layer may include one or more III-V semiconductors (e.g., GaAs, GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, GaSb, AlGaAsP, InAlGaAs, InGaP, InGaPAs, AlInGaP, or a combination of the foregoing or a combination of the foregoing). The semiconductor layer can be formed by a deposition process including molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), metal organic chemical vapor deposition (MOCVD), metal organic vapor phase epitaxy (MOVPE), similar processes or combinations thereof. In a specific embodiment, the semiconductor structure is a gallium arsenide-based pHEMT epitaxial structure, and its basic structure can be, for example, n+AlGaAs / i-InGaAs / i-GaAs, with a double heterojunction, which not only improves the temperature stability of the device threshold voltage, but also improves the output volt-ampere characteristics of the device, so that the device has a larger output resistance, a higher transconductance, a larger current handling capacity, and a higher operating frequency. The source electrode S and the drain electrode D can include Ti, Al, W, Au, Pd, Au, Ge, Ni, Mo, Pt, other suitable metals, alloys thereof, or combinations thereof. The source electrode S and the semiconductor structure 1 may form an ohmic contact therebetween, and the drain electrode D and the semiconductor structure 1 may form an ohmic contact therebetween.
[0050] The materials of the first metal layer 3 and the second metal layer 6 are, for example, Co, W, Ru, Al, Mo, Ti, Cu, Au, Pt, metal alloys, other suitable conductive materials, or a combination of the above. The first source connection metal 31 and the first drain connection metal 32 respectively penetrate the first dielectric layer 2 (by opening holes at corresponding positions of the first dielectric layer 2, etc.) and are connected to the source S and the drain D. The second source connection metal 61 and the second drain connection metal 62 respectively penetrate the spacing dielectric layer 4 and are connected to the first source connection metal 31 and the first drain connection metal 32, so as to serve as thickened metal of the source S and the drain D and realize lead-out, thereby improving the current carrying capacity.
[0051] In this embodiment, the dielectric layer covering the gate G and the surrounding area is SiN / AlO X The thin stacked structure can avoid the influence of the thick upper dielectric layer 5, reduce the parasitic capacitance between the gate and the source and drain, and reduce the noise of the LNA; on the other hand, SiN / AlO X The dielectric layer of the stacked structure can improve the chip's resistance to the hydrogen effect and is more suitable for hydrogen-rich environments.
[0052] The method for manufacturing the integrated circuit chip of the first embodiment is described below with reference to FIG. 2 .
[0053] 2(a), a first dielectric layer 2 is entirely covered on the surface of the integrated circuit chip after the metal electrode process is completed by plasma enhanced chemical vapor deposition (PECVD). The first dielectric layer 2 is etched to form a first connection hole 21 on the source S and the drain D.
[0054] Referring to Figure 2(b), a patterned first metal layer 3 is formed on the first dielectric layer 2 through a metal process. The first metal layer 3 includes a first source connection metal 31, a first drain connection metal 32 and a lower electrode plate 33. The first source connection metal 31 and the first drain connection metal 32 are respectively in contact with the source S and the drain D through the first connection hole 21, and the lower electrode plate 33 is located on the first dielectric layer 2 of the capacitor area B.
[0055] Referring to FIG. 2( c ), a spacer dielectric layer 4 is entirely covered on the surface of the aforementioned structure by a plasma enhanced chemical vapor deposition (PECVD) process;
[0056] 2( d ), a dielectric layer 5 is entirely covered on the surface of the aforementioned structure by a plasma enhanced chemical vapor deposition (PECVD) process;
[0057] Referring to FIG. 2( e ), a photolithography process is used to define an etching window, and the upper dielectric layer 5 is etched to form an opening a in the active area A, and the edge of the opening a is located outside the source electrode S and the drain electrode D; taking the case where the material of the upper dielectric layer 5 is silicon nitride and the material of the spacer dielectric layer 4 is aluminum oxide as an example, wet BOE etching is used, which has a large selective etching ratio for aluminum oxide and silicon nitride, and can remove silicon nitride and maintain the integrity of the aluminum oxide material layer;
[0058] Referring to 2(f), the spacing dielectric layer 4 is etched to form second connection holes 41 on the first source connection metal 31 and the first drain connection metal 32, respectively, and a patterned second metal layer 6 is formed through a metal process. The second metal layer 6 includes a second source connection metal 61, a second drain connection metal 62 and an upper plate 63. The second source connection metal 61 and the second drain connection metal 62 are in contact with the first source connection metal 31 and the first drain connection metal 32 through the second connection holes 41, respectively, and the upper plate 63 is located above the lower plate 33 of the capacitor region B. In addition, in other areas, the first metal layer 3 and the second metal layer 6 can be separated by insulation of the spacing dielectric layer 4 and / or the upper dielectric layer 5 to meet wiring requirements.
[0059] The noise characteristics of gallium arsenide pHEMT are sensitive to the thickness of the silicon nitride film. The noise characteristics of the pHEMT device are reduced by reducing the number of silicon nitride deposition layers. The obtained integrated circuit chip can be used in a radio frequency module, wherein the pHEMT device is applied to a low noise amplifier (LNA) in the radio frequency module. By controlling the thickness of the silicon nitride film in the active area of the HEMT device in the integrated circuit process, the noise coefficient of the amplifier is reduced to obtain better performance. The above-mentioned radio frequency module is applied to base stations, radars, communications or remote sensing and other fields. After testing, under the same other conditions, compared with the structure in which the spacer dielectric layer 4 is not provided, the silicon nitride first dielectric layer and the silicon nitride upper dielectric layer are directly superimposed on the active area, the embodiment adopts The structure formed by the aluminum oxide spacer dielectric layer 4 with a thickness of 1000 nm has an Ft increase of 10 GHz, a Gain max (maximum gain) increase of 1.5 dB, and a noise index reduction of nearly 10% in a noise test.
[0060] Example 2
[0061] refer to Figure 3The integrated circuit chip of embodiment 2 includes a semiconductor structure 1, which has an active area A, a capacitor area B and a resistor area C. The active area A is provided with a source S, a drain D and a gate G, and the gate G is located between the source S and the drain D. A first dielectric layer 2, a first metal layer 3, a second dielectric layer 7, a spacing dielectric layer 4, an upper dielectric layer 5 and a second metal layer 6 are sequentially provided on the semiconductor structure 1. The first dielectric layer 2 covers the source S, the drain D, the gate G and the exposed surface of the semiconductor structure 1. A thin film resistor 8 is provided on the first dielectric layer 2 of the resistor area C. The first metal layer 3 includes a first connection metal (specifically including a first source connection metal 31 and a first drain connection metal 32) located in the active area A, a lower plate 33 located in the capacitor area B and a first lead-out structure 34 located in the resistor area C. The second dielectric layer 7 covers the first metal layer 3, the first dielectric layer 2 and the thin film resistor 3. The spacing dielectric layer 4 covers the second dielectric layer 7. The upper dielectric layer 5 covers the spacing dielectric layer 4 and opens to the active area A, and the edge of the opening a is located outside the source S and the drain D, so that the upper dielectric layer 5 covers other areas including the capacitor area B and the resistor area C but does not cover the active area A. The second metal layer 6 includes a second connection metal located in the active area A (specifically including a second source connection metal 61 and a second drain connection metal 62), an upper plate 63 located in the capacitor area B, and a second lead-out structure 64 located in the resistor area C. In the capacitor area B, the capacitor structure formed by the upper plate 33, the lower plate 63 and the dielectric layer sandwiched therebetween is located on the first dielectric layer 2, and the capacitor dielectric layer is a stack of the second dielectric layer 7 / spacing dielectric layer 4 / upper dielectric layer 5; in the active area A, the dielectric layer covering the surface of the gate G and the area between the gate G and the source S and the drain D is a stack of the first dielectric layer 2 / the second dielectric layer 7 / the spacing dielectric layer 4; in the resistor area C, the two ends of the thin film resistor 8 are led out through the first lead-out structure 34 and the second lead-out structure 64.
[0062] The difference between Example 2 and Example 1 is that the integrated circuit chip further includes a resistor element, and a second dielectric layer 7 is provided for protecting the resistor element. The second dielectric layer 7 is preferably silicon nitride with a thickness of 10 to 100 nm (for example, ) to achieve the passivation effect. Similarly, the total thickness of the dielectric layer covering the gate G and the nearby surface can be reduced by removing the dielectric layer thickness above the spacer dielectric layer 4.
[0063] The method for manufacturing the integrated circuit chip of the second embodiment is described below with reference to FIG. 4 .
[0064] Referring to FIG4(a), a first dielectric layer 2 is entirely covered on the surface of an integrated circuit chip after a metal electrode process is completed by a plasma enhanced chemical vapor deposition (PECVD) process; the first dielectric layer 2 is etched to form a first connection hole 21 on the source S and the drain D; a thin film resistor 8 is formed on the first dielectric layer 2 in the resistor region C, and a patterned first metal layer 3 is formed on the first dielectric layer 2 by a metal process, the first metal layer 3 includes a first source connection metal 31, a first drain connection metal 32, a lower electrode plate 33 and a first lead-out structure 34, the first source connection metal 31 and the first drain connection metal 32 are respectively in contact with the source S and the drain D through the first connection hole 21, the lower electrode plate 33 is located on the first dielectric layer 2 in the capacitor region B, and the first lead-out structure 34 is located in the resistor region C and is disposed at both ends of the thin film resistor 8 and in contact with it;
[0065] 4( b ), a second dielectric layer 7 is entirely covered on the surface of the aforementioned structure by a plasma enhanced chemical vapor deposition (PECVD) process;
[0066] 4( c ), a spacer dielectric layer 4 is entirely covered on the surface of the aforementioned structure by a plasma enhanced chemical vapor deposition (PECVD) process;
[0067] 4 (d), a dielectric layer 5 is entirely covered on the surface of the aforementioned structure by a plasma enhanced chemical vapor deposition (PECVD) process;
[0068] 4(e), a photolithography process is used to define an etching window, and the upper dielectric layer 5 is etched to form an opening a in the active area A and a third connection hole 51 is formed above the first lead-out structure 34, wherein the edge of the opening a is located outside the source S and the drain D, and the etching method is the same as in Example 1;
[0069] 4( f ), the spacer dielectric layer 4 and the second dielectric layer 7 are sequentially etched to form fourth connection holes b on the first source connection metal 31 , the first drain connection metal 32 , and the first lead-out structure 34 ;
[0070] Referring to FIG. 4(g), a graphic second metal layer 6 is formed by a metal process, and the second metal layer 6 includes a second source connection metal 61, a second drain connection metal 62, an upper plate 63 and a second lead structure 64. The second source connection metal 61 and the second drain connection metal 62 are respectively in contact with the first source connection metal 31 and the first drain connection metal 32 through the corresponding fourth connection hole b. The upper plate 63 is located above the lower plate 33 of the capacitor region B, and the second lead structure 64 is in contact with the first lead structure 34 through the corresponding fourth connection hole b and the third connection hole 51. In addition, in other areas, the first metal layer 3 and the second metal layer 6 can be separated by insulation through one or a combination of the second dielectric layer 7, the spacing dielectric layer 4, and the upper dielectric layer 5 to achieve wiring requirements. Through the setting of the above dielectric layer, the dielectric layer thickness requirements of different regions can be flexibly controlled to optimize the performance of each device and component, thereby improving the overall performance.
[0071] Example 3
[0072] The difference between the third embodiment and the second embodiment is that the connection mode of some resistors in the circuit is to connect in series in the circuit using only the first metal layer. Therefore, in the resistor area C, the first lead structure 34 can realize the connection of the circuit, and the second metal layer does not need to set up a second lead structure in the resistor area C, and the dielectric layer above the first lead structure 34 does not need to open a connection hole. Figure 5 The manufacturing process thereof refers to Example 2, and it can be understood that the difference is that, compared with the steps of FIG. 4(e) and FIG. 4(f) of Example 2, this embodiment does not need to open the third connection hole 51, nor does it need to form the fourth connection hole b on the first lead-out structure 34, and compared with the step of FIG. 4(g) of Example 2, this embodiment does not need to form the second lead-out structure 64.
[0073] Example 4
[0074] The difference between Example 4 and Example 2 is that the structure of the active area A is different. In this embodiment, the active area A has multiple gates G, multiple source electrodes S, and a common drain electrode D located between the gate electrodes G. The second connection metal in the active area A includes a second source connection metal 61 and a source bridge metal 65. The source bridge metal 65 connects two adjacent second source connection metals 61 to form a bridge structure. The common drain electrode D does not have a connection structure of the second connection metal. The structure of the active area A is as follows: Figure 6 As shown, the capacitor region B and the resistor region C are the same as those in Example 2. The manufacturing process thereof is referred to Example 2, and it can be understood that the difference is that, compared with the step of FIG. 4(f) of Example 2, when the spacing dielectric layer 4 and the second dielectric layer 7 are sequentially etched, it is not necessary to etch a hole on the first drain connection metal 32; compared with the step of FIG. 4(g) of Example 2, this embodiment does not need to form the second drain connection metal 62, and a source bridge metal 65 is additionally formed to achieve bridging.
[0075] The above embodiments are only used to further illustrate an integrated circuit chip and its manufacturing method and application of the present invention, but the present invention is not limited to the embodiments. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention fall within the protection scope of the technical solution of the present invention.
Claims
1. An integrated circuit chip, characterized in that: The invention comprises a semiconductor structure, wherein the semiconductor structure has an active region and a capacitor region, wherein the active region is provided with a source, a drain and a gate, and the gate is located between the source and the drain; a first dielectric layer, a first metal layer, a spacer dielectric layer, an upper dielectric layer and a second metal layer are sequentially arranged on the semiconductor structure, and the spacer dielectric layer and the upper dielectric layer are made of different dielectric materials, wherein The first dielectric layer covers the source, drain, gate and the surface of the semiconductor structure; the first metal layer includes a first connection metal located in the active area and a lower plate located in the capacitor area; the spacing dielectric layer is arranged on the first metal layer and the first dielectric layer; the upper dielectric layer is arranged on the spacing dielectric layer and is open to the active area, and the edge of the opening is located outside the source and drain; the second metal layer includes a second connection metal located in the active area and an upper plate located in the capacitor area, and the capacitor dielectric layer between the upper plate and the lower plate includes a stack of spacing dielectric layer / upper dielectric layer.
2. The integrated circuit chip according to claim 1, characterized in that: The materials of the spacer dielectric layer and the upper dielectric layer have different etching resistances.
3. The integrated circuit chip according to claim 1, characterized in that: The material of the first dielectric layer is silicon nitride, and the thickness is 10-100 nm.
4. The integrated circuit chip according to claim 1, characterized in that: The material of the spacing dielectric layer is silicon oxide, aluminum oxide or phosphorus silicon glass, and the thickness is 5-100nm.
5. The integrated circuit chip according to claim 1, characterized in that: The material of the upper dielectric layer is silicon nitride, and the thickness is 100-800nm.
6. The integrated circuit chip according to claim 1, characterized in that: The first connection metal includes a first source connection metal and a first drain connection metal, and the first source connection metal and the first drain connection metal respectively penetrate the first dielectric layer and are connected to the source and the drain; the second connection metal is used for leading out the first source connection metal and / or the first drain connection metal, and when leading out, the second connection metal penetrates the spacing dielectric layer and is connected to the first source connection metal and / or the first drain connection metal.
7. The integrated circuit chip according to claim 1, characterized in that: It also includes a second dielectric layer, which is arranged between the first dielectric layer and the spacing dielectric layer. The capacitor dielectric layer between the upper plate and the lower plate includes a stack of separated second dielectric layer / spacer dielectric layer / upper dielectric layer.
8. The integrated circuit chip according to claim 7, characterized in that: The material of the second dielectric layer is silicon nitride, and the thickness is 10-100 nm.
9. The integrated circuit chip according to claim 7, characterized in that: The first connection metal includes a first source connection metal and a first drain connection metal, and the first source connection metal and the first drain connection metal respectively penetrate the first dielectric layer and are connected to the source and the drain; the second connection metal is used for leading out the first source connection metal and / or the first drain connection metal, and when leading out, the second connection metal penetrates the spacing dielectric layer and the second dielectric layer and is connected to the first source connection metal and / or the first drain connection metal.
10. The integrated circuit chip according to claim 7, characterized in that: The semiconductor structure further comprises a resistance region, on which a thin film resistor located on the first dielectric layer is disposed; the first metal layer further comprises a first lead-out structure located in the resistance region, and the first lead-out structure is in contact with the thin film resistor.
11. The integrated circuit chip according to claim 10, characterized in that: The second metal layer further includes a second lead-out structure located in the resistance region, and the second lead-out structure penetrates the upper dielectric layer, the second dielectric layer and the spacing dielectric layer and is connected to the first lead-out structure.
12. The integrated circuit chip according to claim 1, characterized in that: The active region forms a pHEMT device or a HEMT device.
13. A method for manufacturing an integrated circuit chip, characterized in that: The following steps are involved: 1) Providing a semiconductor structure, the semiconductor structure having an active region and a capacitor region, wherein a source electrode, a drain electrode and a gate electrode are disposed on the active region, and the gate electrode is located between the source electrode and the drain electrode; Depositing a first dielectric layer covering the semiconductor structure, the source electrode, the drain electrode and the gate electrode, wherein the first dielectric layer is etched with holes on the source electrode and the drain electrode; 2) forming a patterned first metal layer, wherein the first metal layer includes a first connection metal located in the active area and a lower electrode located in the capacitor area; 3) depositing a spacer dielectric layer; 4) depositing an upper dielectric layer, wherein the upper dielectric layer and the spacer dielectric layer are made of different materials; 5) etching the upper dielectric layer to form an opening in the active area, with the edge of the opening being located outside the source and drain electrodes; 6) etching a hole in the dielectric layer on the first metal layer outside the capacitor region; 7) Forming a patterned second metal layer, the second metal layer includes a second connection metal located in the active area and an upper plate located in the capacitor area, and the capacitor dielectric layer between the upper plate and the lower plate includes a stack of a spacer dielectric layer / an upper dielectric layer.
14. The method for manufacturing an integrated circuit chip according to claim 13, characterized in that: The materials of the spacer dielectric layer and the upper dielectric layer have different etching resistances. In step 6), the upper dielectric layer is selectively removed.
15. The method for manufacturing an integrated circuit chip according to claim 13, characterized in that: Between step 2) and step 3), a step of depositing a second dielectric layer is also included; in step 6), the capacitor dielectric layer between the upper plate and the lower plate includes a stack of second dielectric layer / spacer dielectric layer / upper dielectric layer.
16. The method for manufacturing an integrated circuit chip according to claim 15, characterized in that: The semiconductor structure also has a resistance region, and between step 1) and step 2), a step of forming a thin film resistor on the resistance region is also included; in step 3), the first metal layer also includes a first lead-out structure located in the resistance region.
17. The method for manufacturing an integrated circuit chip according to claim 16, wherein: In step 5), the upper dielectric layer above the first lead-out structure is etched simultaneously to form a lead-out hole; in step 6), the second metal layer also includes a second lead-out structure located in the resistance area, and the second lead-out structure is connected to the first lead-out structure through the lead-out hole.
18. A radio frequency module, characterized in that: The integrated circuit chip comprises any one of claims 1 to 12, wherein the active area is used for a low noise amplifier in a radio frequency module.