Self-aligned gate end cap (SAGE) architecture with gate-all-around device

Abstract

A self-aligned gate end cap (SAGE) architecture with gate-all-around devices. A self-aligned gate end cap (SAGE) architecture with a gate-all-around device, and a method of manufacturing a self-aligned gate end cap (SAGE) architecture with a gate-all-around device, are described. In an example, an integrated circuit structure includes a semiconductor fin over a substrate and having a length in a first direction. The nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, the second direction being perpendicular to the first direction. A semiconductor device includes a pair of gate end cap isolation structures, where a first one of the pair of gate end cap isolation structures is equidistantly spaced from a first side of a semiconductor fin while a second one of the pair of gate end cap isolation structures is spaced from a second side of the semiconductor fin.

Description

Technical Field

[0001] Embodiments of the present disclosure are in the field of semiconductor devices and processing, and in particular, a self-aligned gate endcap (SAGE) architecture with a gate-all-around device, and a method of fabricating the self-aligned gate endcap (SAGE) architecture with a gate-all-around device. Background Art

[0002] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the evolving semiconductor industry. Scaling to smaller and smaller features enables the density of increased functional units in the limited real estate of a semiconductor chip. For example, shrinking transistor size allows an increased number of memory or logic devices to be incorporated on a chip, resulting in the manufacture of products with increased capacity. However, the drive for greater capacity is not without problems. The necessity to optimize the performance of each device becomes increasingly important.

[0003] In the manufacture of integrated circuit devices, as device sizes continue to shrink, multi-gate transistors (such as tri-gate transistors) have become more common. In conventional processes, tri-gate transistors are typically manufactured on bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred because of their lower cost and because they enable less complex tri-gate manufacturing processes. On the other hand, when microelectronic device sizes shrink to below the 10 nanometer (nm) node, maintaining mobility improvements and short channel control provides challenges in device manufacturing. Nanowires used to manufacture devices provide improved short channel control.

[0004] Scaling multi-gate and nanowire transistors is not without consequence, however. As the size of these basic building blocks of microelectronic circuits decreases, and as the absolute number of basic building blocks that can be fabricated in a given area increases, the constraints on the photolithographic processes used to pattern these building blocks have become overwhelming. In particular, there can be a tradeoff between the minimum size of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between these features. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 Illustrated are plan views of adjacent integrated circuit structures of a conventional architecture having relatively wide spacing (left) relative to adjacent integrated circuit structures of a self-aligned gate end cap (SAGE) architecture having relatively tight spacing (right) according to embodiments of the present disclosure.

[0006] Figure 2 A plan view of a conventional layout is illustrated, including accommodating fin-based and / or nanowire-based semiconductor devices with end-to-end spacing.

[0007] Figure 3 Illustrated are cross-sectional views taken through nanowires and fins of a conventional architecture (left) versus a self-aligned gate end cap (SAGE) architecture (right) in accordance with an embodiment of the present disclosure.

[0008] Figure 4 The diagram illustrates a cross-sectional view and a corresponding plan view of an integrated circuit structure manufactured according to an embodiment of the present disclosure, the integrated circuit structure (a) having no SAGE isolation structure, (b) having a SAGE isolation structure manufactured after a fin cutting process, and (c) having a SAGE isolation structure manufactured before a fin cutting process.

[0009] Figure 5 Illustrated are cross-sectional views representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure having a gate-all-around device in accordance with an embodiment of the present disclosure.

[0010] Fig. 6A A three-dimensional cross-sectional view of a nanowire-based semiconductor structure according to an embodiment of the present disclosure is illustrated.

[0011] Figure 6B FIG. 1 shows a diagram of an embodiment of the present disclosure taken along the a-a' axis. Fig. 6A A cross-sectional source or drain view of a nanowire-based semiconductor structure.

[0012] Figure 6C FIG. 1 shows a diagram of a structure according to an embodiment of the present disclosure as taken along the bb' axis. Fig. 6A Cross-sectional channel view of a nanowire-based semiconductor structure.

[0013] Fig. 7A Illustrated is a cross-sectional source or drain view of another nanowire-based semiconductor structure according to an embodiment of the present disclosure.

[0014] Figure 7B The embodiment according to the present disclosure is illustrated Fig. 7A Cross-sectional channel view of a nanowire-based semiconductor structure.

[0015] Fig. 8A Illustrated is a cross-sectional source or drain view of another nanowire-based semiconductor structure according to an embodiment of the present disclosure.

[0016] Figure 8B The embodiment according to the present disclosure is illustrated Fig. 8A Cross-sectional channel view of a nanowire-based semiconductor structure.

[0017] Figures 9A-9E Illustrated are three-dimensional cross-sectional views representing various operations in a method of fabricating a nanowire portion of a fin / nanowire structure, in accordance with an embodiment of the present disclosure.

[0018] Fig. 10A Illustrated is a cross-sectional view of a nanowire-based integrated circuit structure with self-aligned gate end cap isolation according to an embodiment of the present disclosure.

[0019] Fig. 10B The diagram shows an embodiment according to the present disclosure. Fig. 10A A plan view of a semiconductor device taken along the a-a' axis.

[0020] Fig.11 A computing device according to one implementation of an embodiment of the present disclosure is illustrated.

[0021] Fig.12 An inserter including one or more embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0022] A self-aligned gate end cap (SAGE) architecture with a full-all-around gate device and a method of manufacturing a self-aligned gate end cap (SAGE) architecture with a full-all-around gate device are described. In the following description, many specific details are set forth, such as specific integration and material methods, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be implemented without these specific details. In other cases, well-known features, such as integrated circuit design layouts, are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. In addition, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0023] Certain terms may also be used in the following description for reference purposes only, and thus are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions referenced in the accompanying drawings. Terms such as "front," "rear," "rear," and "side" describe the orientation and / or position of parts of a component within a consistent but arbitrary frame of reference, which becomes clear by reference to the text and associated figures describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0024] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically covers everything up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0025] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding points for chip-to-package connections. In the BEOL portion of the manufacturing stage contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added in BEOL.

[0026] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although FEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to BEOL processing. Likewise, although BEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to FEOL processing.

[0027] One or more embodiments of the present disclosure relate to a semiconductor structure or device having one or more gate end cap structures (e.g., as a gate isolation region) of a gate electrode of the semiconductor structure or device. In addition, a method for manufacturing a gate end cap isolation structure in a self-aligned manner is described. In one or more embodiments, the self-aligned gate end cap structure is manufactured to have a full ring gate feature. The embodiments described herein can solve the problems associated with scaling diffusion end-to-end spacing in super-scaling process technology.

[0028] Particular embodiments may involve CMOS integration of multi-width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture. In an embodiment, NMOS and PMOS nanowires / nanoribbons are integrated with multiple Wsi in a front-end process flow based on the SAGE architecture. Such a process flow may involve integration of nanowires and nanoribbons of different Wsi to provide robust functionality of next generation transistors with low power and high performance.

[0029] To provide context, prior art approaches have relied on lithographic scaling of gate end-to-end (polysilicon cut) to define the minimum technical gate overlap of the diffusion. The minimum technical gate overlap of the diffusion is a key component of the diffusion end-to-end spacing. The associated gate line (polysilicon cut) process has typically been limited by lithography, registration, and etch bias considerations, and ultimately sets the minimum diffusion end-to-end distance. Other approaches such as contact on active gate (COAG) architectures have been dedicated to improving such diffusion spacing capabilities. However, improvements in this technical area remain highly sought after.

[0030] Advantages of the self-aligned gate end cap (SAGE) architecture over conventional approaches may include enabling higher layout density, and in particular diffusion to diffusion spacing scaling. As an example, Figure 1 Illustrated are plan views of adjacent integrated circuit structures of a conventional architecture having relatively wide spacing (left side) relative to adjacent integrated circuit structures of a SAGE architecture having relatively tight spacing (right side) according to embodiments of the present disclosure. Figure 1 Illustrated are plan views of adjacent integrated circuit structures of a conventional architecture having relatively wide spacing (left) relative to adjacent integrated circuit structures of a self-aligned gate end cap (SAGE) architecture having relatively tight spacing (right) according to embodiments of the present disclosure.

[0031] refer to Figure 1 , the layout 100 includes first 102 and second 104 integrated circuit structures based on semiconductor fins and / or nanowires 106 and 108, respectively. Each device 102 and 104 has a gate electrode 110 or 112, respectively. In addition, each device 102 and 104 has a trench contact (TCN) 114 or 116, respectively, at the source and drain regions of the fins 106 and 108, respectively. Gate vias 118 and 120 and trench contact vias 119 and 121 are also depicted.

[0032] Reference again Figure 1 , gate electrodes 110 and 112 have relatively wide end cap regions 122, which are respectively located outside the corresponding fins 106 and 108. TCNs 114 and 116 each have a relatively large end-to-end spacing 124, which are also respectively located outside the corresponding fins 106 and 108.

[0033] In contrast, reference Figure 1 1 , in an embodiment, the layout 150 includes first 152 and second 154 integrated circuit structures based on semiconductor fins and / or nanowires 156 and 158, respectively. Each device 152 and 154 has a gate electrode 160 or 162, respectively. In addition, each device 152 and 154 has a trench contact (TCN) 164 or 166, respectively, at the source and drain regions of the fins 156 and 158, respectively. Gate vias 168 and 170 and trench contact vias 169 and 171 are also depicted.

[0034] Reference again Figure 1 , gate electrodes 160 and 162 have relatively tight end cap regions that are located outside of the corresponding fins 156 and 158, respectively. TCNs 164 and 166 each have relatively tight end-to-end spacing 174 that are also located outside of the corresponding fins and / or nanowires 156 and 158, respectively.

[0035] To provide further context, the scaling of the gate endcap and trench contact (TCN) endcap areas is an important factor in improving transistor layout area and density. The gate and TCN endcap areas refer to the gate and TCN overlap of the diffusion region / fin / nanowire of a semiconductor device. As an example, Figure 2 A plan view of a conventional layout 200 is illustrated, including fin-based and / or nanowire-based semiconductor devices accommodating end-to-end spacing.

[0036] refer to Figure 2 , the first 202 and second 204 semiconductor devices are based on semiconductor fins and / or nanowires 206 and 208, respectively. Each device 202 and 204 has a gate electrode 210 or 212, respectively. In addition, each device 202 and 204 has a trench contact (TCN) 214 or 216, respectively, at the source and drain regions of the fins and / or nanowires 206 and 208, respectively. The gate electrodes 210 and 212 and the TCNs 214 and 216 each have an end cap region, which is located outside the corresponding fins and / or nanowires 206 and 208, respectively.

[0037] Reference again Figure 2 , typically, the gate and TCN end cap dimensions must include tolerance for mask registration errors to ensure robust transistor operation for worst case mask misalignment, leaving an end-to-end spacing of 218. Therefore, another important design rule that is critical to improving transistor layout density is the spacing between two adjacent end caps facing each other. However, the parameter of "2*end cap + end-to-end spacing" is becoming increasingly difficult to scale using photolithography patterning to meet the scaling requirements of new technologies. In particular, due to the longer overlap length between the TCN and the gate electrode, the additional end cap length required to allow for mask registration errors also increases the gate capacitance value, thereby increasing product dynamic energy consumption and reducing performance. Previous solutions have focused on improving the registration budget and patterning or resolution improvements to enable reductions in both end cap size and end cap to end cap spacing.

[0038] According to embodiments of the present disclosure, methods are described for providing self-aligned gate end caps and TCN overlap of semiconductor fins and / or nanowires without any need to allow mask registration. In one such embodiment, a disposable spacer is fabricated on the sidewalls of the semiconductor fin that determines the gate end cap and contact overlap dimensions. The spacer-defined end cap process enables the gate and TCN end cap regions to be self-aligned with the semiconductor fins, and therefore no additional end cap length is required to account for mask misalignment. In addition, the methods described herein do not necessarily require lithographic patterning at a previously required stage, as the gate and TCN end cap / overlap dimensions remain fixed, resulting in an improvement (i.e., reduction) in the variability in electrical parameters from device to device.

[0039] According to one or more embodiments of the present disclosure, scaling is achieved by constructing the SAGE wall by reducing the overlap of the gate end cap to the diffusion. As an example, Figure 3 Illustrated are cross-sectional views taken through nanowires and fins of a conventional architecture (left) versus a self-aligned gate end cap (SAGE) architecture (right) in accordance with an embodiment of the present disclosure.

[0040] refer to Figure 3 , an integrated circuit structure 300 includes a substrate 302 having a fin 304 protruding a certain amount 306 from the substrate 302 above an isolation structure 308, and the isolation structure 308 laterally surrounds the lower portion of the fin 304. A corresponding nanowire 305 is located on the fin 304. A gate structure can be formed on the integrated circuit structure 300 to manufacture a device. However, the break in such a gate structure is accommodated by increasing the spacing between the fin 304 / nanowire 305 pairs.

[0041] In contrast, reference Figure 3 , the integrated circuit structure 350 includes a substrate 352 having a fin 354 protruding a certain amount 356 from the substrate 352 above an isolation structure 358, and the isolation structure 358 laterally surrounds the lower portion of the fin 304. The corresponding nanowire 305 is located above the fin 304. An isolation SAGE wall 360 (which may include a hard mask as depicted) is included within the isolation structure 352 and between adjacent fins 354 / nanowires 355 pairs. The distance between the isolation SAGE wall 360 and the nearest fin 354 / nanowire 355 pair defines a gate end cap spacing 362. A gate structure can be formed between the isolation SAGE walls above the integrated circuit structure 300 to manufacture a device. The break in such a gate structure is imposed by the isolation SAGE wall. Because the isolation SAGE wall 360 is self-aligned, the restrictions from conventional methods can be minimized to enable more aggressive diffusion to the diffusion spacing. Furthermore, because the gate structure includes breaks at all locations, the various gate structure portions can be connected by local interconnect layers formed on the isolated SAGE walls 360. In an embodiment, as depicted, the SAGE walls 360 each include a lower dielectric portion and a dielectric cap on the lower dielectric portion.

[0042] According to one or more embodiments of the present disclosure, a self-aligned gate end cap (SAGE) processing scheme involves forming a gate / trench contact end cap that is self-aligned with the fin without requiring additional length to account for mask misalignment. Thus, embodiments may be implemented to enable a reduction in transistor layout area. Embodiments described herein may relate to the manufacture of a gate end cap isolation structure, which may also be referred to as a gate wall, an isolation gate wall, or a self-aligned gate end cap (SAGE) wall.

[0043] In an embodiment, the SAGE architecture is implemented by fabricating the SAGE isolation structure after a process of cutting the fins to remove the fin portions in selected locations. In another embodiment, the SAGE wall formation is performed before finalization of the fin geometry. For comparison purposes, Figure 4 The diagram illustrates a cross-sectional view and a corresponding plan view of an integrated circuit structure manufactured according to an embodiment of the present disclosure, the integrated circuit structure (a) having no SAGE isolation structure, (b) having a SAGE isolation structure manufactured after a fin cutting process, and (c) having a SAGE isolation structure manufactured before a fin cutting process.

[0044] refer to Figure 4 4. In portion (a), an integrated circuit structure 400 manufactured without a SAGE isolation structure includes a substrate having a plurality of fin / nanowire pairs 404 protruding therefrom. An isolation structure 406 laterally surrounds a lower portion of the fins of the fin / nanowire pairs 404. Position 408 indicates an area where a fin or portion of a fin has been removed, for example, by a mask and etching process. A process sequence for manufacturing the integrated circuit structure 400 may include (i) providing a silicon substrate, (ii) forming and patterning a hard mask on the silicon substrate, (iii) patterning silicon fins by etching the silicon substrate in the presence of the hard mask, (iv) performing fin cutting by further mask and etching processing, and (v) shallow trench isolation (STI) filling, polishing, and recessing to form the isolation structure 406.

[0045] refer to Figure 4 , an integrated circuit structure 420 (referred to herein as a bidirectional SAGE architecture) fabricated by forming a SAGE isolation structure after a fin cutting process includes a substrate having a plurality of fin / nanowire pairs 424 protruding therefrom. An isolation structure 426 laterally surrounds the lower portions of the fins of the fin / nanowire pairs 424. Position 428 indicates an area where a fin / nanowire pair or a portion of a fin / nanowire pair is removed, for example, by a mask and etching process. A SAGE wall 430 (which may include a hard mask as indicated by a horizontal line) is formed in position 428 and has an extension portion 432 extending from the SAGE wall 430. The process sequence for manufacturing the integrated circuit structure 420 may include (i) providing a silicon substrate, (ii) SAGE stack formation, (iii) fin / nanowire precursor patterning, (iv) cutting the fin / nanowire precursor by further masking and etching processing, (v) SAGE end cap / wall fabrication, (vi) shallow trench isolation (STI) filling, polishing and recessing to form isolation structure 426, and (vii) releasing (one or more) nanowires.

[0046] refer to Figure 4In part (c), an integrated circuit structure 440 (referred to herein as a unidirectional SAGE architecture) fabricated by forming a SAGE isolation structure prior to a fin cutting process includes a substrate having a plurality of fin / nanowire pairs 444 protruding therefrom. An isolation structure 446 laterally surrounds the lower portions of the fins of the fin / nanowire pairs 444. Position 448 indicates an area where a fin / nanowire pair or a portion of a fin / nanowire pair is removed or not formed. A SAGE wall 450 (which may include a hard mask as indicated by a horizontal line) is formed in a narrow area of ​​position 428. With Figure 4 In contrast to the SAGE wall 430 of portion (b), the SAGE wall 450 has a width of an adjacent uncut fin / nanowire pair portion that is the same as a width of an adjacent fin / nanowire pair cut portion. A process sequence for fabricating the integrated circuit structure 420 may include (i) providing a silicon substrate, (ii) SAGE stack formation, (iii) fin / nanowire precursor patterning, (iv) SAGE end cap / wall fabrication, (v) cutting the fin / nanowire precursor by further masking and etching processing, (vi) shallow trench isolation (STI) filling, polishing and recessing to form isolation structure 446, and (vii) releasing the nanowire(s).

[0047] Referring to integrated structure 440, when compared to integrated circuit structure 420, by repositioning the wall formation prior to fin / nanowire precursor dicing, the SAGE walls can be constrained to extend only along the fin direction. Figure 4 450 , the integrated circuit structure includes a first semiconductor fin / nanowire pair (the fin / nanowire pair 444 immediately to the left of 450) having a cutout along the length of the first semiconductor fin / nanowire pair. The second semiconductor fin / nanowire pair (the fin / nanowire pair 444 immediately to the right of 450) has a cutout along the length of the second semiconductor fin / nanowire pair. The gate end cap isolation structure 450 is located between the first semiconductor fin / nanowire pair and the second semiconductor fin / nanowire pair. The gate end cap isolation structure 450 has a substantially uniform width along the length of the first and second semiconductor fin / nanowire pairs.

[0048] In an exemplary processing scheme, Figure 5 Illustrated are cross-sectional views representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure having a gate-all-around device in accordance with an embodiment of the present disclosure.

[0049] refer to Figure 5, a starting structure includes a nanowire patterned stack 504 above a substrate 502. A photolithographic patterned stack 506 is formed above the nanowire patterned stack 504. The nanowire patterned stack 504 includes alternating silicon germanium layers 510 and silicon layers 512. A protective mask 514 is located between the nanowire patterned stack 504 and the photolithographic patterned stack 506. In one embodiment, the photolithographic patterned stack 506 is a three-layer mask consisting of a topography masking portion 520, an anti-reflective coating (ARC) layer 522, and a photoresist layer 524. In a particular such embodiment, the topography masking portion 520 is a carbon hard mask (CHM) layer, and the anti-reflective coating 522 is a silicon ARC layer.

[0050] refer to Figure 5 The stack of portion (b), portion (a) is photolithographically patterned and then etched to provide an etched structure including a patterned substrate 502 and a trench 530.

[0051] refer to Figure 5 5. In part (c), the structure of part (b) has an isolation layer 540 and a SAGE material 542 formed in the trench 530. The structure is then planarized to leave the patterned topographic mask layer 520' as an exposed upper layer.

[0052] refer to Figure 5 In portion (d), the isolation layer 540 is recessed below the upper surface of the patterned substrate 502 , for example, to define a protruding fin portion and provide a trench isolation structure 541 below the SAGE wall 542 .

[0053] refer to Figure 5 In the portion (e), the silicon germanium layer 510 is removed at least in the channel region to release the silicon nanowires 512A and 512B. Figure 5 After forming the structure of portion (e) of FIG. 5 , a gate stack can be formed around nanowire 512B or 512A, over the protruding fins of substrate 502, and between SAGE walls 542. In one embodiment, the remaining portion of protective mask 514 is removed before forming the gate stack. In another embodiment, the remaining portion of protective mask 514 is retained as an insulating fin cap as an artifact of the processing scheme.

[0054] Reference again Figure 5In part (e), it should be understood that a channel view is depicted in which the source or drain regions are located within the page and outside the page. In an embodiment, the channel region including nanowire 512B has a width that is less than the channel region including nanowire 512A. Therefore, in an embodiment, the integrated circuit structure includes multiple width (multiple Wsi) nanowires. Although the structures of 512B and 512A can be distinguished as nanowires and nanoribbons, respectively, these two structures are generally referred to as nanowires in this article. It should also be understood that references or depictions of fin / nanowire pairs throughout may refer to structures including fins and one or more overlying nanowires (e.g., Figure 5 two overlying nanowires as shown in FIG.

[0055] To highlight an exemplary nanowire portion where the nanowire portion includes a fin / nanowire pair of three nanowires, Fig. 6A A three-dimensional cross-sectional view of a nanowire-based semiconductor structure according to an embodiment of the present disclosure is illustrated. Figure 6B The diagram shows a cross section along the a-a' axis. Fig. 6A A cross-sectional source or drain view of a nanowire-based semiconductor structure. Figure 6C The diagram shows the image taken along the b-b' axis. Fig. 6A Cross-sectional channel view of a nanowire-based semiconductor structure.

[0056] refer to Fig. 6A , semiconductor device 600 includes one or more vertically stacked nanowires (604 groups) above substrate 602. For the purpose of illustration, in order to emphasize the nanowire portion, the fins between the bottommost nanowire and substrate 602 are not depicted. The embodiments herein are directed to both single-wire devices and multi-wire devices. As an example, for illustrative purposes, a three-nanowire-based device with nanowires 604A, 604B, and 604C is shown. For ease of description, nanowire 604A is used as an example in which the description focuses on one of the nanowires. It should be understood that in the case of describing the properties of one nanowire, embodiments based on multiple nanowires can have the same properties for each of the nanowires.

[0057] Each of the nanowires 604 includes a channel region 606 in the nanowire. The channel region 606 has a length (L). Figure 6C , the channel region also has a perimeter (Pc) perpendicular to the length (L). Fig. 6A and 6CIn both, the gate electrode stack 608 surrounds the entire perimeter (Pc) of each of the channel regions 606. The gate electrode stack 608 includes a gate electrode and a gate dielectric layer between the channel region 606 and the gate electrode (not shown). The channel region is discrete because it is completely surrounded by the gate electrode stack 608 without any intervening materials, such as underlying substrate materials or overlying channel fabrication materials. Therefore, in embodiments having multiple nanowires 604, the channel regions 606 of the nanowires are also discrete relative to each other.

[0058] Each of the nanowires 604 also includes source and drain regions 610 and 612 in the nanowire on either side of the channel region 606. Figure 6B , the source or drain region 610 / 612 has a perimeter (Psd) perpendicular to the length (L) of the channel region 606. Fig. 6A and 6B Both, a pair of contacts 614 surround the entire perimeter (Psd) of each of the source or drain regions 610 / 612. The source or drain regions 610 / 612 are discrete because they are completely surrounded by the contacts 614 without any intervening material, such as underlying substrate material or overlying channel fabrication material. Thus, in embodiments having multiple nanowires 604, the source or drain regions 610 / 612 of the nanowires are also discrete relative to each other. In another embodiment, the source or drain regions are replaced with a single epitaxial source or drain structure.

[0059] Reference again Fig. 6A , in an embodiment, the semiconductor device 600 further includes a pair of spacers 616. The spacer 616 is located between the gate electrode stack 608 and the pair of contacts 614. In an embodiment, although not depicted, the source or drain region 610 / 612 of the nanowire 604 is uniformly doped around the perimeter (Psd) of each of the regions. In one such embodiment (also not shown), the doped layer is on the perimeter of each of the source or drain regions 610 / 612 between the source or drain region 610 / 612 and the contact region 614 and completely surrounds the perimeter. In a specific such embodiment, the doped layer is a boron-doped silicon germanium layer, for example, for a PMOS device. In another specific such embodiment, the doped layer is a phosphorus-doped silicon layer, for example, for an NMOS device.

[0060] Substrate 602 may be composed of a material suitable for semiconductor device fabrication. In one embodiment, substrate 602 includes a lower bulk substrate composed of a single crystal material, which may include but is not limited to silicon, germanium, silicon germanium, or a III-V compound semiconductor material. An upper insulating layer composed of a material that may include but is not limited to silicon dioxide, silicon nitride, or silicon oxynitride is located on the lower bulk substrate. Thus, structure 600 may be manufactured from a starting insulator-on-semiconductor substrate. Alternatively, structure 600 is formed directly from a bulk substrate, and local oxidation is used to form an electrically insulating portion to replace the upper insulating layer described above. In another alternative embodiment, structure 600 is formed directly from a bulk substrate, and doping is used to form an electrically isolated active region, such as a nanowire, thereon. In one such embodiment, the first nanowire (i.e., close to the substrate) is in the form of an ω-FET type structure.

[0061] In an embodiment, nanowire 604 may be sized as a wire or ribbon, as described below, and may have square or rounded corners. In an embodiment, nanowire 604 is composed of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowire is single crystalline. For example, for silicon nanowire 604, the single crystalline nanowire may be based on a (100) global orientation, for example, having a z-direction of <100> Plane. Other orientations are also contemplated as described below. In an embodiment, the dimensions of nanowire 604 are nanometers in cross-sectional view. For example, in a specific embodiment, the smallest dimension of nanowire 604 is less than about 20 nanometers. In an embodiment, nanowire 604 is composed of strained material, particularly in channel region 606.

[0062] refer to Figure 6B and 6C In an embodiment, each of the channel regions 606 has a width (Wc) and a height (Hc), the width (Wc) being approximately the same as the height (Hc), and each of the source or drain regions 610 / 612 has a width (Wsd) and a height (Hsd), the width (Wsd) being approximately the same as the height (Hsd). That is, in both cases, the channel regions 606 and the source or drain regions 610 / 612 are square in cross-sectional profile, or, if rounded, circular in cross-sectional profile. In one such embodiment, Wc and Wsd are approximately the same, and Hc and Hsd are approximately the same, as Figure 6B and 6C as shown in .

[0063] However, in another aspect, the perimeter of the channel region (Pc) may be smaller than the perimeter of the source or drain region 610 / 612 (Psd). For example, according to another embodiment of the present disclosure, Fig. 7A A cross-sectional source or drain view of another nanowire-based semiconductor structure is illustrated. Figure 7B Pictured Fig. 7A Cross-sectional channel view of a nanowire-based semiconductor structure.

[0064] refer to Fig. 7A and 7B , in an embodiment, each of the channel regions 606 has a width (Wc) and a height (Hc), the width (Wc) being approximately the same as the height (Hc). Each of the source or drain regions 610 / 612 has a width (WsD) and a height (HsD), the width (WsD) being approximately the same as the height (HsD). That is, in both cases, the channel regions 606 and the source or drain regions 610 / 612 are square in cross-sectional profile, or, if rounded, circular in cross-sectional profile. However, in one such embodiment, Wc is less than Wsd, and Hc is less than Hsd, such as Fig. 7A and 7B In certain such embodiments, the perimeters of the source region 610 and the drain region 612 are substantially the same. In another embodiment, the source or drain region is replaced with a single epitaxial source or drain structure. Thus, the perimeter of each of the source or drain regions 610 / 612 is greater than the perimeter of the channel region 606. Figures 9A-9E Methods for making such arrangements are described in detail.

[0065] In another aspect, the width and height of the channel region need not be the same, and similarly, the width and height of the source or drain region need not be the same. For example, according to another embodiment of the present disclosure, Fig. 8A A cross-sectional source or drain view of another nanowire-based semiconductor structure is illustrated. Figure 8B Pictured Fig. 8A Cross-sectional channel view of a nanowire-based semiconductor structure.

[0066] refer to Fig. 8A and 8B , in an embodiment, each of the channel regions 606 has a width (Wc) and a height (Hc). The width (Wc) is significantly greater than the height (Hc). For example, in a specific embodiment, the width Wc is approximately 2-10 times the height Hc. In addition, each of the source or drain regions 610 / 612 has a width (Wsd) and a height (Hsd), and the width (Wsd) is significantly greater than the height (Hsd). That is, in both cases, the channel region 606 and the source or drain region 610 / 612 are rectangular in cross-sectional profile, or if rounded, elliptical in cross-sectional profile. Nanowires having such a geometry may be referred to as nanoribbons. In one such embodiment, Wc and Wsd are approximately the same, and Hc and Hsd are approximately the same, such as Fig. 8A and 8BHowever, in another embodiment, the perimeter of the source or drain region 610 / 612 is larger than the perimeter of the channel region 606. In another embodiment, the source or drain region is replaced with a single epitaxial source or drain structure.

[0067] The contact resistance may depend on the interface area and the barrier between the metal and the semiconductor. In an embodiment, a method is provided for increasing the contact resistance by reducing the barrier between the metal and the semiconductor by selecting the most favorable semiconductor orientation for the metal contact. For example, in one embodiment, the starting silicon (Si) wafer orientation is suitable for forming contacts around the structure, where more metal / silicon contacts will be with <110> As an exemplary embodiment for illustrating this concept, again refer to Fig. 8A .

[0068] refer to Fig. 8A , the surface of the source or drain region 610 / 612 oriented with Hsd has <q>Crystal orientation. The surface of the source or drain region 610 / 612 oriented with Wsd has <r>In an embodiment, each of the nanowires is composed of silicon, <q>yes <110> orientation, and <r>yes <100> That is, the perimeter along the width of each of the source and drain regions is formed by the exposed <110> The silicon surface is composed of exposed <100> Therefore, a larger portion of the interface between the source or drain region 610 / 612 and the contact 614 is based on the <110> The interaction of the silicon surface rather than <100> Interactions of Silicon Surfaces. In an embodiment, such an orientation is achieved by starting with a base silicon substrate or layer having a global (110) orientation instead of the conventional (100) global orientation.

[0069] In an alternative embodiment (not shown), the nanoribbons are oriented vertically. That is, each of the channel regions has a width and a height, the width being substantially less than the height, and each of the source and drain regions has a width and a height, the width being substantially less than the height. In one such embodiment, each of the nanowires is composed of silicon, with the perimeter of the width of each of the source and drain regions being formed by exposed <100> The silicon surface is composed of exposed <110> Silicon surface composition.

[0070] As described above, in at least some embodiments, the channel region and the source or drain region are made discrete. However, not all regions of a nanowire need or even can be made discrete. For example, a cross-sectional spacer view of a nanowire-based semiconductor structure includes nanowires 604A-604C that are not discrete at a location below spacer 616. In one embodiment, a stack of nanowires 604A-604C has intervening semiconductor material therebetween, such as silicon germanium intervening between silicon nanowires, or vice versa, as described below in conjunction with Fig. 9B described.

[0071] In another aspect, a method of manufacturing a nanowire portion of a fin / nanowire semiconductor device is provided. For example, Figures 9A-9E 3D cross-sectional views showing various operations in a method of fabricating a nanowire portion of a fin / nanowire structure in accordance with an embodiment of the present disclosure are illustrated. Figures 9A-9E Depicting SAGE wall processing.

[0072] A method of manufacturing a nanowire semiconductor device may include forming nanowires over a substrate. In a specific example showing the formation of two silicon nanowires, Fig.9A A substrate 902 is illustrated having a silicon layer 904 / silicon germanium layer 906 / silicon layer 908 stack thereon (e.g., consisting of a bulk silicon substrate 902A with an insulating silicon dioxide layer 902B thereon). It should be understood that in another embodiment, the silicon germanium layer / silicon layer / silicon germanium layer stack can be used to ultimately form two silicon germanium nanowires.

[0073] refer to Fig. 9B , for example, a portion of the silicon layer 904 / silicon germanium layer 906 / silicon layer 908 stack and a top portion of the silicon dioxide layer 902B are patterned into a fin structure 910 using a mask and plasma etching process. It should be understood that for illustrative purposes, Fig. 9B The etching is shown to form two silicon nanowire precursor portions. Although for ease of illustration, the etching is shown to end within the bottom isolation layer, more complex stacks are considered in the context of the embodiments of the present disclosure. For example, the process can be applied to combine Figure 5 Nanowire / fin stack depicted.

[0074] The method may also include forming a channel region in the nanowire, the channel region having a length and a perimeter perpendicular to the length. In a specific example showing the formation of three gate structures over two silicon nanowires, Fig. 9C A fin structure 910 is illustrated having three sacrificial gates 912A, 912B, and 912C thereon. In one such embodiment, the three sacrificial gates 912A, 912B, and 912C are comprised of a sacrificial gate oxide layer 914 and a sacrificial polysilicon gate layer 916 that are blanket deposited and patterned using a plasma etch process.

[0075] After patterning to form the three sacrificial gates 912A, 912B, and 912C, spacers may be formed on the sidewalls of the three sacrificial gates 912A, 912B, and 912C, doping (e.g., tip and / or source and drain type doping) may be performed, and an interlayer dielectric layer may be formed to cover the three sacrificial gates 912A, 912B, and 912C. The interlayer dielectric layer may be polished to expose the three sacrificial gates 912A, 912B, and 912C for a replacement gate or gate-last process. Fig.9D , the three sacrificial gates 912A, 912B, and 912C have been removed, leaving spacers 918 and a portion of the remaining interlayer dielectric layer 920.

[0076] Also, see again Fig.9D , portions of the silicon germanium layer 906 and portions of the insulating silicon dioxide layer 902B of the fin structure 910 are removed in the areas originally covered by the three sacrificial gates 912A, 912B, and 912C. Thus, discrete portions of the silicon layers 904 and 908 remain, such as Fig.9D as shown in .

[0077] In one embodiment, Fig.9D The discrete portions of silicon layers 904 and 908 shown in FIG. 1 will eventually become the channel regions in the nanowire-based device. Fig.9D At the process stage depicted in FIG. 1 , channel engineering or adjustments may be performed. For example, in one embodiment, oxidation and etching processes are used to Fig.9D 906. Such an etching process can be performed at the same time as the wires are separated by etching the silicon germanium layer 906. Thus, the initial wire formed by the silicon layers 904 and 908 starts thick and thins to a size suitable for the channel region in the nanowire device, regardless of the size of the source and drain regions of the device. Thus, in an embodiment, forming the channel region includes removing a portion of the nanowire, and the perimeters of the resulting source and drain regions (described below) are larger than the perimeters of the resulting channel region.

[0078] The method may also include forming a gate electrode stack around the entire perimeter of the channel region. In a specific example showing the formation of three gate structures over two silicon nanowires, Fig.9E The structure is shown after a gate dielectric layer 922 (such as a high-k gate dielectric layer) and a gate electrode layer 924 (such as a metal gate electrode layer) are deposited between the spacers 918 and then polished. That is, the gate structure is formed at Fig.9D In the groove 921. In addition, Fig.9E The result of subsequently removing the interlayer dielectric layer 920 after forming the permanent gate stack is depicted. Portions of the silicon germanium layer 906 and portions of the insulating silicon dioxide layer 902B of the fin structure 910 are also initially formed by Fig.9D The interlayer dielectric layer 920 is removed in the region partially covered by the depicted interlayer dielectric layer 920. Thus, discrete portions of silicon layers 904 and 908 remain, such as Fig.9E As described in .

[0079] The method may also include forming a pair of source and drain regions in the nanowire on either side of the channel region, each of the source and drain regions having a perimeter perpendicular to the length of the channel region. Specifically, in one embodiment, Fig.9E The discrete portions of silicon layers 904 and 908 shown in FIG. 1 will eventually become at least a portion, if not all, of the source and drain regions in a nanowire-based device. Fig.9E At the process stage depicted in , source and drain region engineering or adjustments may be performed, examples of which are as follows. It should be understood that similar engineering or adjustments may instead be performed earlier in the process flow, for example, before depositing an interlayer dielectric layer and forming a permanent gate electrode.

[0080] In an embodiment, forming the pair of source and drain regions includes growing (e.g., by epitaxial growth) to extend a portion of the nanowire. In this manner, the perimeter of the source and drain regions can be made larger than the perimeter of the channel region. In one such embodiment, the nanowire is composed of silicon, and growing the portion of the nanowire includes forming an exposed ?? electrode along the entire perimeter of each of the source and drain regions. <111> In certain such embodiments, the exposed <111> The silicon surface includes the use of deposition and subsequent selective facet etching processes. <111> The oriented surface can be provided directly by depositing epitaxial silicon <111> The nanowires are fabricated by faceting or by depositing silicon and using orientation-dependent silicon etching. In yet another embodiment, the process starts with a thicker nanowire and then uses orientation-dependent silicon etching for subsequent etching. In an embodiment, forming the pair of source and drain regions includes forming a doped layer, such as a boron-doped silicon germanium layer, on and completely around the perimeter of each of the source and drain regions. The layer can facilitate the formation of nanowires with uniformly doped perimeters.

[0081] The method may also include forming a pair of contacts, a first one of the pair of contacts completely surrounding a perimeter of the source region, and a second one of the pair of contacts completely surrounding a perimeter of the drain region. Fig.9E The resulting structure can be Fig. 6A The structure 600 is similar to or Fig. 6A The structure 600 is the same as that of FIG. 601. In an embodiment, the contacts are formed of a metal substance. In one such embodiment, the metal substance is formed by conformally depositing the contact metal and then filling any remaining trench volume. The conformal aspect of the deposition can be performed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or metal reflow.

[0082] In another aspect, system-on-chip (SoC) process technologies typically require support for standard logic (e.g., low voltage thin oxide) and I / O (e.g., high voltage thick oxide) transistors. The distinction between standard logic and high voltage (HVI / O) devices can be achieved through a multi-oxide process sequence, where logic transistors receive a thin, high-performance oxide, and I / O devices receive a thick oxide capable of sustaining higher voltages. As process technology scales, logic devices are aggressively scaled in size, creating manufacturing challenges for dual oxide formation. According to one or more embodiments of the present disclosure, a high voltage / dual end cap process is used to manufacture a super-scaled finfet (fin field effect transistor) transistor architecture.

[0083] To provide context, as technology node scaling shrinks, there is an increasing lack of geometric space in narrow endcap logic devices to accommodate defect-free dual oxide processes that may be required for high voltage transistor manufacturing. Current approaches rely on a single unscaled endcap space to accommodate a single logic oxide process. However, such a process may not be compatible with the highly scaled geometries that support dual oxide high voltage SoC technology because the endcap space may not be sufficient to accommodate both oxides (gate dielectrics).

[0084] According to an embodiment of the present disclosure, the scaling limitations imposed by the requirement to fill the high voltage gate with both high voltage oxide and logic oxide are solved. In particular, as the logic size decreases, the end cap space in the high voltage (HV) device becomes not narrow enough to fill both oxides. In an embodiment, before the fin cutting process, the different end cap spaces between the logic transistor and the high voltage transistor are manufactured separately with the SAGE architecture. By using a self-aligned end cap structure, the logic transistor end caps are over-scaled, and the high voltage transistor has a wider end cap to accommodate a thicker gate dielectric. Both end caps are unidirectional end caps because they are formed by fin cutting processing.

[0085] One or more embodiments described herein relate to or may be referred to as a dual unidirectional end cap process flow for super-scaled logic end caps. To provide context, in a typical SAGE flow, a single end cap spacer is deposited to form a self-aligned end cap that separates the fin from the SAGE wall. The embodiments described herein may involve forming a differentiated sacrificial spacer thickness between the logic and HV gates. Subsequently, a self-aligned end cap wall is formed. The differentiated spacer width is selected to be thicker in the high voltage region, and a standard thickness is used in the logic region. The differentiated spacer width can enable the high voltage oxide to be successfully deposited without sacrificing the density in the logic region. In an embodiment, the thickness of the differentiated spacer depends on the expected HV oxide thickness.

[0086] As an example of a completed device, Fig. 10A Illustrated is a cross-sectional view of a nanowire-based integrated circuit structure with self-aligned gate end cap isolation according to an embodiment of the present disclosure.

[0087] Fig. 10B The diagram shows an embodiment according to the present disclosure. Fig. 10A A plan view of a semiconductor device taken along the a-a' axis.

[0088] refer to Fig. 10A , the semiconductor structure 1000 includes a non-planar active area, for example, a protruding fin portion 1004 and one or more vertically overlying nanowires 1007. The protruding fin portion 1004 may be included in a fin structure, which further includes a sub-fin region 1005 formed by the substrate 1002 and located within the trench isolation layer 1006. In an embodiment, the fin structure is a plurality of fin lines that form a gate structure, such as a close-pitch gate structure. In one such embodiment, the close pitch cannot be directly achieved by conventional lithography. For example, a pattern based on conventional lithography may be first formed, but the pitch may be halved by patterning using a spacer mask, as is known in the art. Further, the original pitch may be quartered by a second round of spacer mask patterning. Thus, the grid-like fin pattern may have lines spaced apart at a constant pitch and having a constant width. The pattern may be manufactured by halving the pitch or quartering the pitch or other pitch segmentation methods. Each of the depicted individual fins 1004 may represent a corresponding individual fin, or may represent multiple fins at a given position.

[0089] The gate structure 1008 is located over the protruding portion 1004 of the non-planar active region and surrounds one or more corresponding vertically overlying nanowires 1007, and also over a portion of the trench isolation layer 1006. As shown, the gate structure 1008 includes a gate electrode 1050 and a gate dielectric layer 1052. In one embodiment, although not shown, the gate structure 1008 may also include a dielectric cap layer.

[0090] The gate structures 1008 are separated by narrow self-aligned gate end cap (SAGE) isolation structures or walls 1020, 1021A, or 1021B. The SAGE walls 1020 each have a certain width. In an embodiment, SAGE wall 1021A has a width that is greater than the width of each of the SAGE walls 1020, and SAGE wall 1021B has a width that is less than the width of each of the SAGE walls 1020. SAGE walls of different widths may be associated with different device types, as described in the exemplary embodiments below. Each SAGE wall 1020, 1021A, or 1021B may include one or more of a local interconnect 1054 or a dielectric plug 1099 formed thereon. In an embodiment, each of the SAGE walls 1020, 1021A, or 1021B is recessed below the uppermost surface 1097 of the trench isolation layer 1006, as shown in FIG. Fig. 10A As depicted in .

[0091] In an exemplary embodiment, the semiconductor structure 1000 includes a first plurality of semiconductor fin / nanowire pairs (one or more fin / nanowire pairs 1004 / 1007 of region 1070A) above the substrate 1002 and protruding through the uppermost surface 1097 of the trench isolation layer 1006, and a first gate structure (gate structure 1008 of region 1070A) above the first plurality of semiconductor fin / nanowire pairs. A second plurality of semiconductor fin / nanowire pairs (one or more fin / nanowire pairs 1004 / 1007 of region 1070B) are above the substrate 1002 and protruding through the uppermost surface 1097 of the trench isolation layer 1006, and a second gate structure (gate structure 1008 of region 1070B) is above the second plurality of semiconductor fin / nanowire pairs. A gate end cap isolation structure (left SAGE wall 1020) is located between the first gate structure and the second gate structure and contacts the first gate structure and the second gate structure. Semiconductor fin / nanowire pairs of the first plurality of semiconductor fins closest to the gate endcap isolation structure (from region 1070A) are spaced farther from the gate endcap isolation structure than semiconductor fin / nanowire pairs of the second plurality of semiconductor fins closest to the gate endcap isolation structure (from region 1070B).

[0092] In an embodiment, region 1070A is an I / O region, and region 1070B is a logic region. As depicted, in one such embodiment, a second logic region 1070C is adjacent to logic region 1070B and is electrically connected to logic region 1070B via local interconnect 1054. Another region 1070D may be a location where additional logic or I / O regions may be placed. The embodiments described herein may involve a differential spacing with SAGE walls (e.g., a wider spacing with SAGE walls 1021B and left 1020 in region 1070A), or may involve SAGE walls of different widths (e.g., narrower 1021B vs. 1020 vs. wider 1021A), or both a differential spacing with SAGE walls and SAGE walls of different widths. In an embodiment, the I / O region has a larger spacing between SAGE walls than the logic region. In an embodiment, the SAGE walls between adjacent logic regions are wider than the SAGE walls between adjacent I / O regions.

[0093] Also visible from this angle are gate contact 1014 and overlying gate contact via 1016, along with overlying metal interconnect 1060, all of which are within an interlayer dielectric stack or layer 1070. Fig. 10A It can also be seen from the perspective that, in one embodiment, the gate contact 1014 is located above the non-planar active region. Fig. 10A As depicted in , an interface 1080 exists between the doping profiles of the protruding fin portion 1004 and the sub-fin region 1005 , although other embodiments do not include such an interface in the doping profiles between these regions.

[0094] refer to Fig. 10A and 10B , a gate structure 1008 is shown above the protruding fin portion 1004 and the corresponding nanowire 1007, as isolated by a self-aligned gate end cap isolation structure 1020. In an embodiment, the gate structure 1008 forms one of a plurality of parallel gate lines that form a gate structure, such as a tightly spaced gate structure. In one such embodiment, the tight spacing cannot be directly achieved by conventional photolithography. For example, a pattern based on conventional photolithography can be first formed, but the spacing can be halved by patterning using a spacer mask, as is known in the art. Further, the original spacing can be quartered by a second round of spacer mask patterning. Thus, a gate-like gate pattern can have lines spaced at a constant spacing and having a constant width. The pattern can be manufactured by halving the spacing or quartering the spacing or other spacing segmentation methods.

[0095] Reference again Fig. 10B , the source and drain regions 1004A and 1004B of the protruding fin portion 1004 and the corresponding (one or more) nanowires 1007 are shown at this angle, but it should be understood that these regions will overlap with the trench contact structure. In one embodiment, the source and drain regions 1004A and 1004B are doped portions of the original material of the protruding fin / nanowire portion 1004 / 1007. In another embodiment, the material of the protruding fin / nanowire portion 1004 / 1007 is removed and replaced with another semiconductor material, for example by epitaxial deposition. In either case, the source and drain regions 1004A and 1004B can extend below the height of the trench isolation layer 1006, that is, into the sub-fin area 1005.

[0096] In an embodiment, semiconductor structure 1000 includes a non-planar device such as, but not limited to, a finFET or a tri-gate device having corresponding one or more overlying nanowire structures. In such an embodiment, the corresponding semiconductor channel region is composed of or formed in a three-dimensional body, wherein one or more discrete nanowire channel portions overly the three-dimensional body. In one such embodiment, gate structure 1008 surrounds at least a top surface and a pair of sidewalls of the three-dimensional body, and further surrounds each of the one or more discrete nanowire channel portions.

[0097] The substrate 1002 may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, the substrate 1002 is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers, such as but not limited to phosphorus, arsenic, boron, or a combination thereof, to form an active region 1004. In one embodiment, the concentration of silicon atoms in the bulk substrate 1002 is greater than 97%. In another embodiment, the bulk substrate 1002 is composed of an epitaxial layer grown on top of a different crystalline substrate, for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate. The bulk substrate 1002 may alternatively be composed of a III-V material. In an embodiment, the bulk substrate 1002 is made of a III-V material, such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, gallium indium arsenide, gallium aluminum arsenide, gallium indium phosphide, or a combination thereof. In one embodiment, the bulk substrate 1002 is composed of a III-V material and the charge carrier dopant impurity atoms are atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0098] The trench isolation layer 1006 may be composed of a material suitable for ultimately electrically isolating or facilitating isolation of a portion of the permanent gate structure from the underlying bulk substrate or isolating an active region (such as an isolation fin active region) formed within the underlying bulk substrate. For example, in one embodiment, the trench isolation layer 1006 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0099] The self-aligned gate end cap isolation structures 1020, 1021A, and 1021B may be composed of one or more materials suitable for ultimately electrically isolating portions of the permanent gate structure from one another or facilitating isolation of portions of the permanent gate structure from one another. Exemplary materials or material combinations include single material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include multi-layer stacks of upper higher dielectric constant materials (such as hafnium oxide) with lower silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0100] The gate structure 1008 may be composed of a gate electrode stack including a gate dielectric layer 1052 and a gate electrode layer 1050. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer includes a high-K material.

[0101] In an exemplary embodiment, the gate structure 1008 of region 1070A includes a first gate dielectric 1052 that conforms to the first plurality of semiconductor fin / nanowire pairs and is laterally adjacent to and in contact with a first side (left side 1020) of the gate end cap isolation structure. The second gate stack of region 1070B includes a second gate dielectric 1052 that conforms to the second plurality of semiconductor fin / nanowire pairs and is laterally adjacent to and in contact with a second side of the gate end cap isolation structure opposite to the first side of the gate end cap isolation structure. In one embodiment, the first gate dielectric is thicker than the second gate dielectric, such as Fig. 10A . In one embodiment, the first gate dielectric has more dielectric layers (e.g., layers 1052A and 1052B) than the second gate dielectric (e.g., only layer 1052). In an embodiment, the gate dielectric of region 1070A is an I / O gate dielectric, and the gate dielectric of region 1070B is a logic gate dielectric.

[0102] In an embodiment, the gate dielectric of region 1070B is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer may include a layer of native oxide formed by the top layers of substrate 1002. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In an embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In an embodiment, the top high-k portion is composed of a "U" shaped structure, which includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In an embodiment, in addition to the layer of high-k material, the gate dielectric of region 1070A also includes a layer of non-native silicon oxide. The layer of non-native silicon oxide can be formed using a CVD process and can be formed below or above a layer of high-k material. In an exemplary embodiment, a layer of non-native silicon oxide (e.g., layer 1052A) is formed below a layer of high-k material (e.g., layer 1052B).

[0103] In one embodiment, the gate electrode is composed of a metal layer, such as but not limited to a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or a conductive metal oxide. In a specific embodiment, the gate electrode is composed of a non-work function setting filling material formed above a metal work function setting layer. In some implementations, the gate electrode may be composed of a "U" shaped structure, the "U" shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In a further implementation of the present disclosure, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0104] The spacers associated with the gate electrode stack may be composed of a material suitable for ultimately electrically isolating or facilitating isolation of the permanent gate structure from adjacent conductive contacts (such as self-aligned contacts). For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0105] The local interconnect 1054, the gate contact 1014, the overlying gate contact via 1016, and the overlying metal interconnect 1060 may be composed of a conductive material. In an embodiment, one or more of the contacts or vias are composed of a metal substance. The metal substance may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material). A common example is the use of a copper structure, which may or may not include a barrier layer (such as a Ta or TaN layer) between copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer, a stack of different metals or alloys, and the like.

[0106] In an embodiment (although not shown), providing structure 1000 involves forming a contact pattern that is substantially perfectly aligned with an existing gate pattern while eliminating the use of a lithography step with an extremely tight registration budget. In one such embodiment, the method enables the use of an essentially highly selective wet etch (e.g., relative to a conventionally implemented dry etch or plasma etch) to produce contact openings. In an embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the method enables the elimination of the need for additional critical lithography operations as used in conventional methods to produce the contact pattern. In an embodiment, the trench contact grid is not patterned separately, but rather is formed between the polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0107] In addition, the gate structure 1008 can be manufactured by a replacement gate process. In such a scheme, a dummy gate material such as a polysilicon or silicon nitride pillar material can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, rather than from an earlier process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process including the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etching process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etching process including aqueous phosphoric acid.

[0108] In an embodiment, one or more methods described herein substantially contemplate dummy and replacement gate processes in combination with dummy and replacement contact processes to implement structure 1000. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, an anneal is performed on at least a portion of the permanent gate structure at a temperature greater than about 600 degrees Celsius, such as after forming the gate dielectric layer. The anneal is performed prior to the formation of the permanent contact.

[0109] Reference again Fig. 10A In an embodiment, as depicted, a semiconductor device has a contact structure that contacts a portion of a gate electrode formed above an active area. Typically, before (e.g., in addition to) forming a gate contact structure (such as a via) above the active portion of the gate and in the same layer as the trench contact via, one or more embodiments of the present disclosure include first using a gate alignment trench contact process. Such a process can be implemented to form a trench contact structure for semiconductor structure fabrication (e.g., for integrated circuit fabrication). In an embodiment, a trench contact pattern is formed to align with an existing gate pattern. In contrast, conventional methods typically involve additional lithography processes in which a lithographic contact pattern is closely aligned with an existing gate pattern in conjunction with selective contact etching. For example, a conventional process may include patterning a polysilicon (gate) grid with separate patterning of contact features.

[0110] It should be understood that Fig. 10A and 10B As shown in , SAGE walls of different widths can be manufactured. It should also be understood that the manufacture of the gate end cap isolation structure can result in the formation of vertical seams within the gate end cap isolation structure. It should also be understood that a stack of dielectric layers can be used to form the SAGE wall. It should also be understood that the gate end cap isolation structure can be different in composition depending on the spacing of adjacent fins.

[0111] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, fluorinated silicon oxides, carbon-doped silicon oxides, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0112] In an embodiment, as also used throughout this specification, the metal line or interconnect material (and via material) is composed of one or more metals or other conductive structures. Common examples are the use of copper wires and structures, which may include a barrier layer or may not include a barrier layer between copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Therefore, the interconnect may be a single material layer, or may be formed by several layers, including a conductive liner layer and a filling layer. Any suitable deposition process may be used to form the interconnect, such as electroplating, chemical vapor deposition, or physical vapor deposition. In an embodiment, the interconnect is composed of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or its alloy. Interconnects are sometimes also referred to as traces, wires, lines, metals, or simply interconnects in the art.

[0113] In an embodiment, as also used throughout this specification, the hard mask material, cap layer or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, cap or plug materials can be used in different regions to provide different growth or etching selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, cap layer or plug layer includes a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide or both or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask, cap or plug layers known in the art may be used. The hard mask, cap or plug layer may be formed by CVD, PVD or by other deposition methods.

[0114] In an embodiment, as also used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), EUV and / or EBDW lithography, or the like. Positive or negative resists may be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific such embodiment, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating is a silicon ARC layer.

[0115] The embodiments disclosed herein can be used to manufacture a variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a variety of electronic devices known in the art. For example, in computer systems (e.g., desktop computers, laptop computers, servers), cellular phones, personal electronic devices, etc. The integrated circuit can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. via one or more buses. Each of the processor, memory, and chipset can be manufactured using the methods disclosed herein.

[0116] Fig.11 A computing device 1100 is illustrated according to one implementation of an embodiment of the present disclosure. The computing device 1100 houses a board 1102. The board 1102 may include multiple components, including, but not limited to, a processor 1104 and at least one communication chip 1106. The processor 1104 is physically and electrically coupled to the board 1102. In some implementations, the at least one communication chip 1106 is also physically and electrically coupled to the board 1102. In other implementations, the communication chip 1106 is part of the processor 1104.

[0117] Depending on its application, the computing device 1100 may include other components that may or may not be physically and electrically coupled to the board 1102. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard drives, compact disks (CDs), digital versatile disks (DVDs), and the like).

[0118] The communication chip 1106 enables wireless communication for the transfer of data to and from the computing device 1100. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., which can transmit data by the use of modulated electromagnetic radiation through a non-physical medium. The term does not imply that the associated device does not contain any wires, although in some embodiments they may not include wires. The communication chip 1106 can implement any standard or protocol in a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and later. The computing device 1100 may include a plurality of communication chips 1106. For example, the first communication chip 1106 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and the second communication chip 1106 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0119] The processor 1104 of the computing device 1100 includes an integrated circuit die packaged within the processor 1104. The integrated circuit die of the processor 1104 may include one or more structures, such as a self-aligned gate end cap (SAGE) structure constructed according to implementations of embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0120] The communication chip 1106 also includes an integrated circuit die packaged within the communication chip 1106. The integrated circuit die of the communication chip 1106 may include one or more structures, such as a self-aligned gate end cap (SAGE) structure constructed according to implementations of embodiments of the present disclosure.

[0121] In further implementations, another component housed within computing device 1100 may include an integrated circuit die that includes one or more structures, such as a self-aligned gate end cap (SAGE) structure constructed in accordance with implementations of embodiments of the present disclosure.

[0122] In various implementations, computing device 1100 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In other implementations, computing device 1100 may be any other electronic device that processes data.

[0123] Fig.12 An interposer 1200 including one or more embodiments of the present disclosure is illustrated. Interposer 1200 is an intervening substrate for bridging a first substrate 1202 to a second substrate 1204. The first substrate 1202 may be, for example, an integrated circuit die. The second substrate 1204 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of interposer 1200 is to extend the connection to a wider spacing or to reroute the connection to a different connection. For example, interposer 1200 may couple an integrated circuit die to a ball grid array (BGA) 1206, which may then be coupled to a second substrate 1204. In some embodiments, first and second substrates 1202 / 1204 are attached to opposite sides of interposer 1200. In other embodiments, first and second substrates 1202 / 1204 are attached to the same side of interposer 1200. And in further embodiments, three or more substrates are interconnected by interposer 1200.

[0124] The interposer 1200 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In other implementations, the interposer may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V or IV materials.

[0125] The interposer may include metal interconnects 1208 and through-holes 1210, including but not limited to through silicon vias (TSVs) 1212. The interposer 1200 may further include embedded devices 1214, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1200. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used in the manufacture of the interposer 1200 or in the manufacture of components included in the interposer 1200.

[0126] Thus, embodiments of the present disclosure include a self-aligned gate endcap (SAGE) architecture having a gate-all-around device, and a method of fabricating a self-aligned gate endcap (SAGE) architecture having a gate-all-around device.

[0127] This application provides the following technical solutions:

[0128] 1. An integrated circuit structure, comprising:

[0129] a semiconductor fin over the substrate and having a length in a first direction;

[0130] nanowires on top of semiconductor fins;

[0131] a gate structure over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, the second direction being perpendicular to the first direction; and

[0132] A pair of gate end cap isolation structures, wherein a first one of the pair of gate end cap isolation structures is equidistantly spaced from a first side of the semiconductor fin and a second one of the pair of gate end cap isolation structures is spaced from a second side of the semiconductor fin, wherein the first one of the pair of gate end cap isolation structures is directly adjacent to a first end of the gate structure and the second one of the pair of gate end cap isolation structures is directly adjacent to a second end of the gate structure.

[0133] 2. The integrated circuit structure according to technical solution 1 further comprises:

[0134] On either side of the gate structure, source and drain regions adjacent to the nanowires and semiconductor fins; and

[0135] A first trench contact is over the source region and a second trench contact is over the drain region.

[0136] 3. The integrated circuit structure according to technical solution 1 further comprises:

[0137] a second semiconductor fin over the substrate and having a length in the first direction, the second semiconductor fin being spaced apart from the first semiconductor fin;

[0138] a second nanowire over the second semiconductor fin;

[0139] a second gate structure over the second nanowire and the second semiconductor fin, the second gate structure having a first end opposite the second end in the second direction, wherein a second one of the pair of gate end cap isolation structures is directly adjacent to the first end of the second gate structure; and

[0140] A third gate end cap isolation structure is directly adjacent to the second end of the second gate structure, wherein the third gate end cap isolation structure and the second one of the pair of gate end cap isolation structures are centered about the second semiconductor fin.

[0141] 4. The integrated circuit structure according to technical solution 3 further comprises:

[0142] A local interconnect is over the first and second gate structures and electrically couples the first and second gate structures.

[0143] 5. An integrated circuit structure according to Technical Solution 3, wherein the second nanowire is wider than the nanowire.

[0144] 6. An integrated circuit structure according to technical solution 1, wherein the gate structure includes a high-k gate dielectric layer and a metal gate electrode.

[0145] 7. The integrated circuit structure according to technical solution 1, wherein the pair of gate end cap isolation structures include a material selected from the group consisting of: silicon oxide, silicon nitride, silicon carbide and a combination thereof.

[0146] 8. The integrated circuit structure according to technical solution 1, wherein the pair of gate end cap isolation structures includes a lower dielectric portion and a dielectric cap on the lower dielectric portion.

[0147] 9. The integrated circuit structure according to technical solution 1, wherein at least one of the pair of gate end cap isolation structures includes a vertical seam located at the center thereof.

[0148] 10. An integrated circuit structure comprising:

[0149] a first fin having a longest dimension along a first direction;

[0150] a first nanowire over the first fin;

[0151] a second fin having a longest dimension along the first direction;

[0152] a second nanowire over the second fin;

[0153] a first gate structure over the first nanowire and the first fin, the first gate structure having a longest dimension along a second direction, the second direction being perpendicular to the first direction;

[0154] a second gate structure over the second nanowire and over the second fin, the second gate structure having a longest dimension along the second direction, the second gate structure being discontinuous with the first gate structure along the second direction, and the second gate structure having an edge along the second direction facing an edge of the first gate structure; and

[0155] A gate end cap isolation structure is between and in contact with an edge of the first gate structure and an edge of the second gate structure along the second direction, the gate end cap isolation structure having a length along the first direction that is greater than a length of the first gate structure and the second gate structure along the first direction.

[0156] 11. An integrated circuit structure according to technical solution 10, wherein the second nanowire is wider than the nanowire.

[0157] 12. An integrated circuit structure according to technical solution 10, wherein the gate end cap isolation structure includes a lower dielectric portion and a dielectric cap on the lower dielectric portion.

[0158] 13. An integrated circuit structure according to technical solution 10, wherein the gate end cap isolation structure includes a vertical seam located at the center thereof.

[0159] 14. The integrated circuit structure according to technical solution 10 further comprises:

[0160] A dielectric material is laterally adjacent to and in contact with the gate end cap isolation structure, and the dielectric material has a composition different from a composition of the gate end cap isolation structure.

[0161] 15. An integrated circuit structure according to technical solution 10, wherein the first gate structure includes a first gate dielectric layer and a first gate electrode, and wherein the second gate structure includes a second gate dielectric layer and a second gate electrode.

[0162] 16. An integrated circuit structure according to technical solution 15, wherein the gate end cap isolation structure contacts the gate dielectric layer of the first gate structure and contacts the gate dielectric layer of the second gate structure.

[0163] 17. An integrated circuit structure according to technical solution 10, wherein the gate end cap isolation structure has a height greater than the height of the first gate structure and greater than the height of the second gate structure.

[0164] 18. The integrated circuit structure according to technical solution 17 further comprises:

[0165] A local interconnect is over a portion of the first gate structure, over a portion of the gate end cap isolation structure, and over a portion of the second gate structure.

[0166] 19. The integrated circuit structure according to technical solution 18, wherein the local interconnection electrically couples the first gate structure to the second gate structure.

[0167] 20. The integrated circuit structure according to technical solution 19 further comprises:

[0168] A gate contact is on a portion of the local interconnect over the first gate structure but not on a portion of the local interconnect over the second gate structure.

[0169] 21. An integrated circuit structure comprising:

[0170] a first semiconductor fin and nanowire pair having a cutout along a length of the first semiconductor fin and nanowire pair;

[0171] a second semiconductor fin and nanowire pair having a cutout along a length of the second semiconductor fin and nanowire pair; and

[0172] A gate end cap isolation structure is provided between the first semiconductor fin and nanowire pair and the second semiconductor fin and nanowire pair, the gate end cap isolation structure having a substantially uniform width along the length of the first and second semiconductor fin and nanowire pairs.

[0173] 22. An integrated circuit structure according to technical solution 21, wherein the gate end cap isolation structure includes a lower dielectric portion and a dielectric cap on the lower dielectric portion.

[0174] 23. An integrated circuit structure according to technical solution 21, wherein the gate end cap isolation structure includes a vertical seam located in the center of the gate end cap isolation structure.

[0175] The above description of the illustrated implementations of the embodiments of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the present disclosure to the exact form disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as will be recognized by those skilled in the relevant art.

[0176] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the following claims should not be interpreted to limit the present disclosure to the specific implementations disclosed in the specification and claims. Instead, the scope of the present disclosure is to be determined entirely by the following claims, which are to be interpreted in accordance with established principles of claim interpretation.

[0177] Example embodiment 1: An integrated circuit structure, comprising: a semiconductor fin, which is above a substrate and has a length in a first direction. A nanowire is above the semiconductor fin. A gate structure is above the nanowire and the semiconductor fin, the gate structure having a first end opposite to a second end in a second direction, the second direction being perpendicular to the first direction. A pair of gate end cap isolation structures are included, wherein the first of the pair of gate end cap isolation structures is equidistantly spaced from a first side of the semiconductor fin, and the second of the pair of gate end cap isolation structures is spaced from a second side of the semiconductor fin. The first of the pair of gate end cap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate end cap isolation structures is directly adjacent to the second end of the gate structure.

[0178] Example embodiment 2: The integrated circuit structure of example embodiment 1 further includes: on either side of the gate structure, source and drain regions adjacent to the nanowires and semiconductor fins, and further includes a first trench contact above the source region and a second trench contact above the drain region.

[0179] Example embodiment 3: The integrated circuit structure of example embodiment 1 or 2, further comprising: a second semiconductor fin, which is above the substrate and has a length in the first direction, the second semiconductor fin is spaced apart from the first semiconductor fin; a second nanowire above the second semiconductor fin; a second gate structure above the second nanowire and the second semiconductor fin, the second gate structure having a first end opposite to the second end in the second direction, wherein the second of the pair of gate end cap isolation structures is directly adjacent to the first end of the second gate structure. The integrated circuit structure further comprises a third gate end cap isolation structure, which is directly adjacent to the second end of the second gate structure, wherein the third gate end cap isolation structure and the second of the pair of gate end cap isolation structures are centered on the second semiconductor fin.

[0180] Example Embodiment 4: The integrated circuit structure of Example Embodiment 3, further comprising a local interconnect over the first and second gate structures and electrically coupling the first and second gate structures.

[0181] Example Embodiment 5: The integrated circuit structure of Example Embodiment 3 or 4, wherein the second nanowire is wider than the nanowire.

[0182] Example Embodiment 6: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, or 5, wherein the gate structure includes a high-k gate dielectric layer and a metal gate electrode.

[0183] Example Embodiment 7: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, 5, or 6, wherein the pair of gate end cap isolation structures comprises a material selected from the group consisting of: silicon oxide, silicon nitride, silicon carbide, and combinations thereof.

[0184] Example Embodiment 8: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, 5, 6 or 7, wherein the pair of gate end cap isolation structures includes a lower dielectric portion and a dielectric cap on the lower dielectric portion.

[0185] Example Embodiment 9: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, 5, 6, 7, or 8, wherein at least one of the pair of gate end cap isolation structures includes a vertical seam centrally located therein.

[0186] Example embodiment 10: An integrated circuit structure comprising: a first fin having a longest dimension along a first direction. A first nanowire is above the first fin. A second fin having a longest dimension is along the first direction. A second nanowire is above the second fin. A first gate structure is above the first nanowire and the first fin, the first gate structure having a longest dimension along a second direction, the second direction being perpendicular to the first direction. A second gate structure is above the second nanowire and above the second fin, the second gate structure having a longest dimension along the second direction, the second gate structure being discontinuous with the first gate structure along the second direction, and the second gate structure having an edge facing an edge of the first gate structure along the second direction. A gate end cap isolation structure is between and in contact with an edge of the first gate structure and an edge of the second gate structure along the second direction, the gate end cap isolation structure having a length along the first direction that is greater than the length of the first gate structure and the second gate structure along the first direction.

[0187] Example Embodiment 11: The integrated circuit structure of Example Embodiment 10, wherein the second nanowire is wider than the nanowire.

[0188] Example Embodiment 12: The integrated circuit structure of Example Embodiment 10 or 11, wherein the gate end cap isolation structure includes a lower dielectric portion and a dielectric cap on the lower dielectric portion.

[0189] Example Embodiment 13: The integrated circuit structure of Example Embodiment 10, 11, or 12, wherein the gate end cap isolation structure includes a vertical seam located at the center thereof.

[0190] Example Embodiment 14: The integrated circuit structure of Example Embodiment 10, 11, 12 or 13, further comprising: a dielectric material laterally adjacent to and in contact with the gate end cap isolation structure, and the dielectric material has a composition different from a composition of the gate end cap isolation structure.

[0191] Example Embodiment 15: The integrated circuit structure of Example Embodiment 10, 11, 12, 13 or 14, wherein the first gate structure comprises a first gate dielectric layer and a first gate electrode, and wherein the second gate structure comprises a second gate dielectric layer and a second gate electrode.

[0192] Example Embodiment 16: The integrated circuit structure of Example Embodiment 15, wherein the gate end cap isolation structure contacts the gate dielectric layer of the first gate structure and contacts the gate dielectric layer of the second gate structure.

[0193] Example Embodiment 17: The integrated circuit structure of Example Embodiment 10, 11, 12, 13, 14, 15 or 16, wherein the gate end cap isolation structure has a height greater than a height of the first gate structure and greater than a height of the second gate structure.

[0194] Example Embodiment 18: The integrated circuit structure of Example Embodiment 17, further comprising: a local interconnect over a portion of the first gate structure, over a portion of the gate end cap isolation structure, and over a portion of the second gate structure.

[0195] Example Embodiment 19: The integrated circuit structure of Example Embodiment 18, wherein the local interconnect electrically couples the first gate structure to the second gate structure.

[0196] Example Embodiment 20: The integrated circuit structure of Example Embodiment 19, further comprising: a gate contact on a portion of the local interconnect over the first gate structure but not on a portion of the local interconnect over the second gate structure.

[0197] Example embodiment 21: An integrated circuit structure comprising: a first semiconductor fin and nanowire pair having a cutout along the length of the first semiconductor fin and nanowire pair; a second semiconductor fin and nanowire pair having a cutout along the length of the second semiconductor fin and nanowire pair; and a gate end cap isolation structure between the first semiconductor fin and nanowire pair and the second semiconductor fin and nanowire pair. The gate end cap isolation structure has a substantially uniform width along the length of the first and second semiconductor fin and nanowire pairs.

[0198] Example Embodiment 22: The integrated circuit structure of Example Embodiment 21, wherein the gate end cap isolation structure includes a lower dielectric portion and a dielectric cap on the lower dielectric portion.

[0199] Example Embodiment 23: The integrated circuit structure of Example Embodiment 21 or 22, wherein the gate end cap isolation structure includes a vertical seam located in the center of the gate end cap isolation structure.< / r> < / q> < / r> < / q>

Claims

1. An integrated circuit structure, comprising: a first isolation structure having an upper surface and a lower surface; a first fin having a bottom portion located below an upper surface of the first isolation structure, and the first fin having a top portion located above an upper surface of the first isolation structure; a second fin having a bottom portion located below an upper surface of the first isolation structure, the second fin having a top portion located above an upper surface of the first isolation structure, and the second fin being laterally spaced apart from the first fin; as well as A second isolation structure is located between the first fin and the second fin and is laterally spaced apart from the first fin and the second fin, the second isolation structure is vertically located above the first isolation structure, the second isolation structure has a top located above the top of the first fin and the top of the second fin, and the second isolation structure has a bottom located below the upper surface of the first isolation structure, and the bottom of the second isolation structure is located above the lower surface of the first isolation structure.

2. The integrated circuit structure according to claim 1, further comprising: a first nanowire vertically disposed above the first fin; as well as A second nanowire is vertically disposed above the second fin.

3. The integrated circuit structure according to claim 1, further comprising: a first gate stack located above the first fin; as well as A second gate stack is located above the second fin. 4 . The integrated circuit structure of claim 3 , wherein the second isolation structure laterally separates the first gate stack from the second gate stack, and wherein the second isolation structure contacts the first gate stack and the second gate stack. 5 . The integrated circuit structure of claim 3 , wherein each of the first gate stack and the second gate stack comprises a gate dielectric and a gate electrode.

6. The integrated circuit structure according to claim 3, further comprising: a first pair of source or drain structures on either side of the first gate stack; as well as A second pair of source or drain structures is located on either side of the second gate stack.

7. The integrated circuit structure of claim 1, wherein the second isolation structure comprises a lower dielectric portion and a dielectric cap on the lower dielectric portion.

8. An integrated circuit structure comprising: a trench isolation structure having an upper surface and a lower surface; a first semiconductor body having a bottom portion located below an upper surface of the trench isolation structure, and the first semiconductor body having a top portion located above the upper surface of the trench isolation structure; a second semiconductor body having a bottom portion below an upper surface of the trench isolation structure, the second semiconductor body having a top portion above an upper surface of the trench isolation structure, and the second semiconductor body being laterally spaced apart from the first semiconductor body; as well as A gate end cap isolation structure is located between the first semiconductor body and the second semiconductor body and is laterally spaced apart from the first semiconductor body and the second semiconductor body, the gate end cap isolation structure is vertically located above the trench isolation structure, the gate end cap isolation structure has a top located above the top of the first semiconductor body and the top of the second semiconductor body, and the gate end cap isolation structure has a bottom located below the upper surface of the trench isolation structure, and the bottom of the gate end cap isolation structure is located above the lower surface of the trench isolation structure.

9. The integrated circuit structure of claim 8, further comprising: a first nanowire vertically disposed above the first semiconductor body; as well as A second nanowire is vertically disposed above the second semiconductor body.

10. The integrated circuit structure of claim 8, further comprising: a first gate stack over the first semiconductor body; as well as A second gate stack is located over the second semiconductor body.

11. The integrated circuit structure of claim 10, wherein the gate end cap isolation structure laterally separates the first gate stack from the second gate stack, and wherein the gate end cap isolation structure contacts the first gate stack and the second gate stack. 12 . The integrated circuit structure of claim 10 , wherein each of the first gate stack and the second gate stack comprises a gate dielectric and a gate electrode.

13. The integrated circuit structure of claim 10, further comprising: a first pair of source or drain structures on either side of the first gate stack; as well as A second pair of source or drain structures is located on either side of the second gate stack.

14. The integrated circuit structure of claim 8, wherein the gate end cap isolation structure comprises a lower dielectric portion and a dielectric cap on the lower dielectric portion.

15. An integrated circuit structure comprising: a first isolation structure having an upper surface and a lower surface; a first fin protruding through the first isolation structure; a second fin protruding through the first isolation structure, the second fin being laterally spaced apart from the first fin; as well as A second isolation structure is located between the first fin and the second fin and is laterally spaced apart from the first fin and the second fin, the second isolation structure is vertically located above the first isolation structure, and the second isolation structure extends from a position located above the top of the first fin and the top of the second fin to a position located below the upper surface of the first isolation structure and above the lower surface of the first isolation structure.

16. The integrated circuit structure of claim 15, further comprising: a first nanowire vertically disposed above the first fin; as well as A second nanowire is vertically disposed above the second fin.

17. The integrated circuit structure of claim 15, further comprising: a first gate stack located above the first fin; as well as A second gate stack is located above the second fin. 18 . The integrated circuit structure of claim 17 , wherein a second isolation structure laterally separates the first gate stack from the second gate stack, and wherein the second isolation structure contacts the first gate stack and the second gate stack.

19. The integrated circuit structure of claim 17, wherein each of the first gate stack and the second gate stack comprises a gate dielectric and a gate electrode.

20. The integrated circuit structure of claim 17, further comprising: a first pair of source or drain structures on either side of the first gate stack; as well as A second pair of source or drain structures is located on either side of the second gate stack.

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