Image sensor and method for manufacturing the same

Abstract

The present invention provides an image sensor and a manufacturing method thereof. The isolation ring metal layer of the present invention is arranged around the pixel array; the isolation ring metal layer is used for physical isolation instead of NPN ion implantation isolation to achieve the purpose of isolating the pixel array more effectively; the physical isolation is more stable and reliable, and leakage and signal crosstalk caused by various PN junctions and microscopic MOS transistor secondary effects are avoided. Compared with PN junction isolation, the physical isolation of the isolation ring metal layer saves chip area. The isolation ring opening is combined with the silicon through hole etching process of the image sensor, and the isolation ring opening and the silicon through hole share the same mask and are formed simultaneously in the same silicon substrate etching process; in the same metal forming process, an interconnected metal layer filling the silicon through hole and an isolation ring metal layer filling the isolation ring opening are formed; the mask is saved and the process integration difficulty is low. For products such as infrared cameras that have high requirements for silicon substrate thickness, the physical isolation of the isolation ring metal layer is more reliable.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to an image sensor and a manufacturing method thereof. Background Art

[0002] As people continue to pursue high-quality images, stacked CMOS image sensors have been developed. Stacked CMOS image sensors usually include a logic wafer and a pixel wafer bonded to the logic wafer. Compared with traditional CMOS image sensors (including front-illuminated CMOS image sensors or back-illuminated CMOS image sensors), stacked CMOS image sensors have a smaller chip structure and faster processing speed.

[0003] During the manufacturing process of stacked CMOS image sensor chips, various PN junctions and microscopic MOS transistor secondary effects (including band lattices) will cause leakage and signal crosstalk, so an isolation structure is required. In CMOS transistors, the periphery of NMOS tubes requires P-type ion implantation isolation, and the periphery of PMOS tubes requires N-type ion implantation isolation. Different types of ions implanted in isolation structures in different regions also lead to process complexity. Figure 1 As shown, a PNP isolation structure is usually used around the pixel array 01 of the image sensor. The design rules have requirements for the size of the PNP isolation structure, for example, it must be at least 45μm, and the PNP isolation structure occupies a larger chip size. The PNP isolation structure is formed by PNP ion implantation. The ion implantation of pixels with small pitches requires deeper depth, and the ion implantation of the PNP isolation structure in a small-sized chip is more difficult. Summary of the invention

[0004] The purpose of the present invention is to provide an image sensor and a manufacturing method thereof, wherein an isolation ring metal layer is arranged around a pixel array; physical isolation of the isolation ring metal layer is used instead of NPN ion implantation isolation to achieve a more effective purpose of isolating the pixel array; physical isolation is more stable and reliable, avoiding leakage and signal crosstalk caused by various PN junctions and microscopic MOS transistor secondary effects; saving chip area; saving photomasks, and low process integration difficulty. For products such as infrared cameras that require a high thickness of the silicon substrate, physical isolation of the isolation ring metal layer is more reliable.

[0005] The present invention provides a method for manufacturing an image sensor, comprising:

[0006] Providing a bonded logic wafer and a pixel wafer, wherein a first line metal layer is formed in the logic wafer; the pixel wafer comprises a second substrate, a second dielectric layer located on the second substrate, and a second line metal layer embedded in the second dielectric layer, wherein a pixel array is formed in the second substrate;

[0007] Using the same photomask, through exposure and etching processes, a through silicon via and an isolation ring opening are formed, both of which penetrate the second substrate; the isolation ring opening is arranged around the pixel array;

[0008] Etching to form a dielectric layer opening, wherein the dielectric layer opening penetrates the second dielectric layer and exposes the second wire metal layer;

[0009] In the same metal forming process, an interconnect metal layer filling the through silicon via and the dielectric layer opening, and an isolation ring metal layer filling the isolation ring opening are formed; the interconnect metal layer is electrically connected to the second line metal layer and the first line metal layer respectively.

[0010] Furthermore, in a top view, the opening of the isolation ring is in the form of a rectangular ring or a square ring.

[0011] Furthermore, the through silicon via is arranged in the second substrate outside the annular shape of the isolation ring opening.

[0012] Further, the isolation ring opening includes an annular opening portion and an epitaxial opening portion extending from the annular opening portion, and the epitaxial opening portion is connected to the through silicon via;

[0013] The interconnect metal layer filling the through silicon via is electrically connected to the isolation ring metal layer filling the isolation ring opening.

[0014] Furthermore, the metal forming process adopts a deposition process or an electroplating process.

[0015] The present invention also provides an image sensor, comprising:

[0016] A bonded logic wafer and a pixel wafer, wherein a first line metal layer is formed in the logic wafer; the pixel wafer comprises a second substrate, a second dielectric layer located on the second substrate, and a second line metal layer embedded in the second dielectric layer, wherein a pixel array is formed in the second substrate;

[0017] Through silicon vias and isolation ring openings both penetrate the second substrate; the isolation ring openings are arranged around the pixel array;

[0018] A dielectric layer opening, wherein the dielectric layer opening penetrates the second dielectric layer and exposes the second wire metal layer;

[0019] An interconnect metal layer filling the through silicon via and the dielectric layer opening, and an isolation ring metal layer filling the isolation ring opening; the interconnect metal layer is electrically connected to the second line metal layer and the first line metal layer respectively.

[0020] Further, the isolation ring opening includes an annular opening portion and an epitaxial opening portion extending from the annular opening portion, and the epitaxial opening portion is connected to the through silicon via;

[0021] The interconnect metal layer filling the through silicon via is electrically connected to the isolation ring metal layer filling the isolation ring opening.

[0022] Furthermore, a pad or a connection line connected to the interconnect metal layer is connected to a negative potential, so that the isolation ring metal layer is connected to a negative potential, thereby forming a hole gathering area in the second substrate near the periphery of the isolation ring metal layer.

[0023] Furthermore, the interconnection metal layer and the isolation ring metal layer are made of the same material, which includes at least one of copper, aluminum, gold, silver, titanium, tin and nickel.

[0024] Furthermore, a first plug is formed in the first dielectric layer, and the first plug is electrically connected to the first line metal layer; the interconnection metal layer is electrically connected to the first line metal layer through the first plug.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The present invention provides an image sensor and a manufacturing method thereof, comprising: providing a bonded logic wafer and a pixel wafer, wherein a first line metal layer is formed in the logic wafer; the pixel wafer comprises a second substrate, a second dielectric layer located on the second substrate and a second line metal layer embedded in the second dielectric layer, wherein a pixel array is formed in the second substrate; using the same photomask, through-silicon vias and isolation ring openings that both penetrate the second substrate are formed through exposure and etching processes; the isolation ring openings are arranged around the pixel array; etching forms dielectric layer openings, wherein the dielectric layer openings penetrate the second dielectric layer and expose the second line metal layer; in the same metal forming process, forming an interconnection metal layer that fills the through-silicon vias and the dielectric layer openings, and an isolation ring metal layer that fills the isolation ring openings; the interconnection metal layer is electrically connected to the second line metal layer and the first line metal layer, respectively.

[0027] The metal layer of the isolation ring of the present invention is arranged around the pixel array; the present invention eliminates the traditional PNP isolation isolation ring, and the isolation ring adopts physical isolation of the isolation ring metal layer instead of NPN ion implantation isolation, so as to achieve the purpose of more effective isolation of the pixel array. Physical isolation is more stable and reliable, and avoids leakage and signal crosstalk caused by various PN junctions and microscopic MOS transistor secondary effects (such as energy band lattices) in the chip manufacturing process. Compared with PN junction isolation, physical isolation of the isolation ring metal layer is more friendly to design rules, does not need to occupy too much area, and saves chip area.

[0028] The isolation ring opening is combined with the through silicon via etching process of the image sensor. The isolation ring opening and the through silicon via share the same photomask and are formed simultaneously in the same silicon substrate etching process without adding additional photomasks and etching processes; it saves photomasks and has low process integration difficulty. The metal process is very mature in the field of chip manufacturing and is relatively simple to implement.

[0029] The current fine-pitch pixel ion implantation requires deeper depth, and the physical isolation of the isolation ring metal layer can avoid leakage and signal crosstalk in the deeper areas of the silicon substrate. For products such as infrared cameras that require a higher silicon substrate thickness, the physical isolation of the isolation ring metal layer is more reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of an image sensor using a PNP isolation structure.

[0031] Figure 2 FIG. 4 is a flow chart of a method for manufacturing an image sensor according to an embodiment of the present invention.

[0032] Figure 3 FIG. 4 is a top view of an image sensor according to an embodiment of the present invention.

[0033] Figure 4 The image sensor of one embodiment of the present invention focuses on Figure 3 Schematic diagram of the cross section of the Aa region.

[0034] Figure 5 FIG. 4 is a top view of an image sensor according to another embodiment of the present invention.

[0035] Figure 6 The image sensor of another embodiment of the present invention focuses on Figure 5 Schematic cross-section of the middle ellipse region.

[0036] The reference numerals are as follows:

[0037] 01-pixel array; 12-first dielectric layer; 13-first line metal layer; 14-first plug; 21-second substrate; 22-second dielectric layer; 23-second line metal layer; 24-pixel array; 31, 34-interconnection metal layer; 32, 35-isolation ring metal layer; V1, V5-through silicon via; V2, V6-isolation ring opening; 33-soldering pad. DETAILED DESCRIPTION

[0038] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0039] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0040] The embodiment of the present invention provides a method for manufacturing an image sensor, such as Figure 2 As shown, including:

[0041] Step S1, providing a bonded logic wafer and a pixel wafer, wherein a first line metal layer is formed in the logic wafer; the pixel wafer comprises a second substrate, a second dielectric layer located on the second substrate, and a second line metal layer embedded in the second dielectric layer, wherein a pixel array is formed in the second substrate;

[0042] Step S2, using the same photomask, through exposure and etching processes, forming through silicon vias and isolation ring openings that penetrate the second substrate; the isolation ring openings are arranged around the pixel array;

[0043] Step S3, etching to form a dielectric layer opening, wherein the dielectric layer opening penetrates the second dielectric layer and exposes the second wire metal layer;

[0044] Step S4, in the same metal forming process, forming an interconnect metal layer filling the through silicon vias and the dielectric layer openings, and an isolation ring metal layer filling the isolation ring openings; the interconnect metal layer is electrically connected to the second line metal layer and the first line metal layer respectively.

[0045] The steps of the method for manufacturing an image sensor according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings.

[0046] Figure 3 FIG. 4 is a top view of an image sensor according to an embodiment of the present invention. Figure 4 The image sensor of one embodiment of the present invention focuses on Figure 3 Schematic diagram of the cross section of the Aa region. Figure 3 and Figure 4As shown, step S1, providing a bonded logic wafer and pixel wafer, the logic wafer includes a first substrate (not shown), a first dielectric layer 12 located on the first substrate, and a first line metal layer 13 embedded in the first dielectric layer 12, the pixel wafer includes a second substrate 21, a second dielectric layer 22 located on the second substrate 21, and a second line metal layer 23 embedded in the second dielectric layer 22, the first dielectric layer 12 is bonded facing the second dielectric layer 22; a pixel array 24 is formed in the second substrate 21, and a photodiode is formed in the pixel array 24. A first plug 14 is also formed in the first dielectric layer 12, and the first plug 14 is electrically connected to the first line metal layer 13.

[0047] Step S2, using the same photomask, through exposure and etching processes, forming a silicon through via V1 and an isolation ring opening V2 that both penetrate the second substrate 21; from a top view, the isolation ring opening V2 is arranged around the pixel array 24. From a top view, the isolation ring opening V2 is a rectangular ring or a square ring. The silicon through via V1 is arranged in the second substrate 21 outside the ring of the isolation ring opening V2. The isolation ring opening V2 is combined with the silicon through via V1 etching process of the image sensor, and the isolation ring opening V2 and the silicon through via V1 share the same photomask and are formed simultaneously in the same silicon substrate etching process, without adding additional photomasks and etching processes; saving photomasks, and low difficulty in process integration.

[0048] Step S3, etching to form dielectric layer openings, the dielectric layer openings penetrate the second dielectric layer 22 and expose the second wire metal layer 23. Specifically, a first opening V3 with a smaller opening size may be formed first, the first opening V3 penetrates the second dielectric layer 22 and exposes the first plug 14; then, a second opening V4 with a larger opening size is formed, the second opening V4 has a larger lateral size based on the first opening V3, and the second opening V4 exposes the second wire metal layer 23. The first opening V3 and the second opening V4 constitute dielectric layer openings.

[0049] Step S4, in the same metal forming process, an interconnect metal layer 31 filling the through silicon via V1 and the dielectric layer opening, and an isolation ring metal layer 32 filling the isolation ring opening V2 are formed; the interconnect metal layer 31 is electrically connected to the second line metal layer 23 and the first line metal layer 13 respectively. The interconnect metal layer 31 is electrically connected to the first line metal layer 13 through the first plug 14. The metal forming process adopts a deposition process or an electroplating process. The interconnect metal layer 31 and the isolation ring metal layer 32 are made of the same material, which may include but is not limited to at least one of copper, aluminum, gold, silver, titanium, tin and nickel, as well as other suitable conductive materials. The metal process is very mature in the field of chip manufacturing and is relatively simple to implement.

[0050] Next, a passivation layer may be formed, the passivation layer covers the interconnection metal layer 31, the isolation ring metal layer 32, and the second substrate 21; the passivation layer may be a stacked structure of an oxide layer and a nitride layer (such as ONO), the passivation layer and the second substrate 21 are etched to form an opening, and a pad 33 is formed in the opening, and the pad 33 leads out the electrical signal in the pixel wafer. The pad may also be led out directly above the interconnection metal layer 31.

[0051] Figure 5 FIG. 4 is a top view of an image sensor according to another embodiment of the present invention. Figure 6 The image sensor of another embodiment of the present invention focuses on Figure 5 Schematic diagram of the cross section of the elliptical area. Figure 5 and Figure 6 As shown, the same photomask is used to form a through silicon via V5 and an isolation ring opening V6 that penetrate the second substrate 21 through exposure and etching processes; in a top view, the isolation ring opening V6 is arranged around the pixel array 24. In a top view, the isolation ring opening V6 includes an annular opening portion and an epitaxial opening portion ( Figure 5 ellipse), and the epitaxial opening portion is connected to the silicon through via V5. The annular opening portion is a rectangular ring or a square ring. The silicon through via V5 is arranged in the second substrate 21 on the annular outer side of the isolation ring opening V6. Exemplarily, silicon through vias V5 are arranged on all sides of the annular outer side of the isolation ring opening V6. A metal layer lead-out pad can be filled in the silicon through via V5. The interconnection metal layer 34 filling the silicon through via V5 is directly electrically connected to the isolation ring metal layer 35 filling the isolation ring opening V6. A negative potential can be connected to the pad or wire connecting the interconnection metal layer 34, so that the isolation ring metal layer 35 is connected to a negative potential, thereby forming a hole gathering area in the second substrate 21 near the periphery of the isolation ring metal layer 35; on the one hand, leakage is reduced, and on the other hand, non-photoelectrons generated by the interface state or the defective area nearby during the process manufacturing process can be forcibly pulled away, thereby reducing white pixels.

[0052] The metal layer of the isolation ring of the present invention is arranged around the pixel array; the traditional PNP isolation isolation ring is eliminated, and the isolation ring adopts physical isolation of the isolation ring metal layer instead of NPN ion implantation isolation, so as to achieve the purpose of isolating the pixel array more effectively. Physical isolation is more stable and reliable, and avoids leakage and signal crosstalk caused by various PN junctions and microscopic MOS transistor secondary effects (such as band lattices) in the chip manufacturing process. Compared with PN junction isolation, physical isolation of the isolation ring metal layer is more friendly to design rules, does not need to occupy too much area, and saves chip area. The current small-pitch pixel ion implantation requires deeper depth, and physical isolation of the isolation ring metal layer can avoid leakage and signal crosstalk in deeper areas of the silicon substrate. For products such as infrared cameras that have high requirements for silicon substrate thickness, physical isolation of the isolation ring metal layer is more reliable.

[0053] The present invention also provides an image sensor, comprising:

[0054] The logic wafer and the pixel wafer are bonded, wherein the first line metal layer 13 is formed in the logic wafer; the pixel wafer includes a second substrate 21, a second dielectric layer 22 located on the second substrate 21, and a second line metal layer 23 embedded in the second dielectric layer 22, and a pixel array 24 is formed in the second substrate 21;

[0055] The through silicon vias and the isolation ring openings all penetrate the second substrate 21; the isolation ring openings are arranged around the pixel array 24;

[0056] The dielectric layer has a hole, and the dielectric layer has a hole that penetrates the second dielectric layer 22 and exposes the second wire metal layer 23;

[0057] The interconnection metal layer fills the through silicon vias and the dielectric layer openings, and the isolation ring metal layer fills the isolation ring openings; the interconnection metal layer is electrically connected to the second line metal layer 23 and the first line metal layer 13 respectively.

[0058] In one embodiment, if Figure 3 and Figure 4 As shown, the image sensor includes: a silicon through via V1 and an isolation ring opening V2 both penetrating the second substrate 21; in a top view, the isolation ring opening V2 is arranged around the pixel array 24. In a top view, the isolation ring opening V2 is a rectangular ring or a square ring. The silicon through via V1 is arranged in the second substrate 21 outside the ring of the isolation ring opening V2. The image sensor includes: an interconnection metal layer 31 filling the silicon through via V1 and the dielectric layer opening, and an isolation ring metal layer 32 filling the isolation ring opening V2; the interconnection metal layer 31 is electrically connected to the second line metal layer 23 and the first line metal layer 13 respectively. The interconnection metal layer 31 is electrically connected to the first line metal layer 13 through the first plug 14.

[0059] In another embodiment, if Figure 5 and Figure 6 As shown, the image sensor includes: a through silicon via V5 and an isolation ring opening V6 both penetrating the second substrate 21; in a top view, the isolation ring opening V6 is arranged around the pixel array 24. In a top view, the isolation ring opening V6 includes an annular opening portion and an epitaxial opening portion ( Figure 5The through-silicon via V5 is arranged in the second substrate 21 outside the annular ring of the isolation ring opening V6. Exemplarily, through-silicon vias V5 are arranged around the annular outer side of the isolation ring opening V6. A metal layer lead-out pad can be filled in the through-silicon via V5. The interconnection metal layer 34 filling the through-silicon via V5 is directly electrically connected to the isolation ring metal layer 35 filling the isolation ring opening V6. A negative potential can be connected to the pad or wire connecting the interconnection metal layer 34, so that the isolation ring metal layer 35 is connected to a negative potential, thereby forming a hole gathering area in the second substrate 21 near the periphery of the isolation ring metal layer 35; on the one hand, leakage is reduced, and on the other hand, non-photoelectrons generated by the interface state or the defective area nearby during the process manufacturing process can be forcibly pulled away, thereby reducing white pixels. The physical isolation of the isolation ring metal layer is similar to deep trench isolation.

[0060] In summary, the present invention provides an image sensor and a method for manufacturing the same. The isolation ring metal layer of the present invention is arranged around the pixel array; the isolation ring metal layer is used for physical isolation instead of NPN ion implantation isolation to achieve the purpose of isolating the pixel array more effectively; the physical isolation is more stable and reliable, avoiding leakage and signal crosstalk caused by various PN junctions and microscopic MOS transistor secondary effects. Compared with PN junction isolation, the physical isolation of the isolation ring metal layer saves chip area. The isolation ring opening is combined with the silicon through hole etching process of the image sensor, and the isolation ring opening and the silicon through hole share the same mask and are formed simultaneously in the same silicon substrate etching process; in the same metal forming process, an interconnected metal layer filling the silicon through hole and an isolation ring metal layer filling the isolation ring opening are formed; the mask is saved and the process integration difficulty is low. For products such as infrared cameras that have high requirements for silicon substrate thickness, the physical isolation of the isolation ring metal layer is more reliable.

[0061] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0062] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the isolation scope of the technical solution of the present invention.

Claims

1. A method for manufacturing an image sensor, characterized in that: include: Providing a bonded logic wafer and a pixel wafer, wherein a first line metal layer is formed in the logic wafer; the pixel wafer comprises a second substrate, a second dielectric layer located on the second substrate, and a second line metal layer embedded in the second dielectric layer, wherein a pixel array is formed in the second substrate; Using the same photomask, through exposure and etching processes, a through silicon via and an isolation ring opening are formed, both of which penetrate the second substrate; the isolation ring opening is arranged around the pixel array; Etching to form a dielectric layer opening, wherein the dielectric layer opening penetrates the second dielectric layer and exposes the second wire metal layer; In the same metal forming process, an interconnect metal layer filling the through silicon via and the dielectric layer opening, and an isolation ring metal layer filling the isolation ring opening are formed; the interconnect metal layer is electrically connected to the second line metal layer and the first line metal layer respectively.

2. The method for manufacturing an image sensor according to claim 1, wherein: In a top view, the opening of the isolation ring is a rectangular ring or a square ring.

3. The method for manufacturing an image sensor according to claim 1, wherein: The through silicon via is disposed in the second substrate outside the annular shape of the isolation ring opening.

4. The method for manufacturing an image sensor according to claim 1, wherein: The isolation ring opening includes an annular opening portion and an epitaxial opening portion extending from the annular opening portion, and the epitaxial opening portion is connected to the through silicon via; The interconnect metal layer filling the through silicon via is electrically connected to the isolation ring metal layer filling the isolation ring opening.

5. The method for manufacturing an image sensor according to claim 1, wherein: The metal forming process adopts a deposition process or an electroplating process.

6. An image sensor, characterized in that: include: A bonded logic wafer and a pixel wafer, wherein a first line metal layer is formed in the logic wafer; the pixel wafer comprises a second substrate, a second dielectric layer located on the second substrate, and a second line metal layer embedded in the second dielectric layer, wherein a pixel array is formed in the second substrate; Through silicon vias and isolation ring openings both penetrate the second substrate; the isolation ring openings are arranged around the pixel array; A dielectric layer opening, wherein the dielectric layer opening penetrates the second dielectric layer and exposes the second wire metal layer; An interconnect metal layer filling the through silicon via and the dielectric layer opening, and an isolation ring metal layer filling the isolation ring opening; the interconnect metal layer is electrically connected to the second line metal layer and the first line metal layer respectively.

7. The image sensor according to claim 6, wherein: The isolation ring opening includes an annular opening portion and an epitaxial opening portion extending from the annular opening portion, and the epitaxial opening portion is connected to the through silicon via; The interconnect metal layer filling the through silicon via is electrically connected to the isolation ring metal layer filling the isolation ring opening.

8. The image sensor according to claim 7, wherein: The pad or the connection line connected to the interconnection metal layer is connected to a negative potential, so that the isolation ring metal layer is connected to a negative potential, thereby forming a hole gathering area in the second substrate near the periphery of the isolation ring metal layer.

9. The image sensor according to claim 6, wherein: The interconnection metal layer and the isolation ring metal layer are made of the same material, which includes at least one of copper, aluminum, gold, silver, titanium, tin and nickel.

10. The image sensor according to claim 6, wherein: A first plug is also formed in the first dielectric layer, and the first plug is electrically connected to the first line metal layer; the interconnection metal layer is electrically connected to the first line metal layer through the first plug.

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