Light-emitting diode with improved reliability and method for preparing the same

Abstract

The present disclosure provides a light-emitting diode with improved reliability and a method for manufacturing the same, which belongs to the field of optoelectronic manufacturing technology. The light-emitting diode includes an epitaxial layer, a first surface of the epitaxial layer has an annular groove, the annular groove surrounds the epitaxial layer along the peripheral edge of the first surface, and the annular groove is located on the side wall of the epitaxial layer. The embodiments of the present disclosure can reduce the stress inside the light-emitting diode and prevent the light-emitting diode from cracking.

Description

Technical Field

[0001] The present disclosure relates to the technical field of optoelectronic manufacturing, and in particular to a light emitting diode with improved reliability and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) is a common product. LED is usually manufactured by manufacturing various film layers on a substrate, performing graphic processing, and then cutting to form individual LED core particles.

[0003] In the related art, during the preparation process of light-emitting diodes, a laser lift-off process is usually used to separate the epitaxial layer and the sapphire substrate, and the epitaxial layer is bonded to another silicon substrate with better thermal conductivity, thereby solving the heat dissipation problem of high-power LEDs.

[0004] However, during the laser lift-off process, compressive stress is generated due to the lattice mismatch between the sapphire substrate and the epitaxial layer; and during the bonding process, compressive stress is also generated due to the material difference between the silicon substrate and the sapphire substrate. Under the action of these stresses, the light-emitting diode will cause warping and the internal stress will increase, which can easily cause the light-emitting diode to crack and cause the epitaxial layer to fall off. Summary of the invention

[0005] The embodiment of the present disclosure provides a light emitting diode with improved reliability and a method for manufacturing the same, which can reduce the stress inside the light emitting diode and prevent the light emitting diode from cracking. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode, which includes an epitaxial layer, a first surface of the epitaxial layer having an annular groove, the annular groove surrounding the epitaxial layer along the peripheral edge of the first surface, and the annular groove is located on the side wall of the epitaxial layer.

[0007] Optionally, the width of the annular groove is 3 μm to 10 μm.

[0008] Optionally, the depth of the annular groove is greater than or equal to 2000 angstroms.

[0009] Optionally, the light-emitting diode also includes a passivation layer, which is located on the first surface and in the annular groove; the second surface of the epitaxial layer has a first groove, and the annular groove surrounds the first groove, and at most a part of the orthographic projection of the first groove on the second surface intersects with the orthographic projection of the annular groove on the second surface, and the first surface and the second surface are two opposite surfaces on the epitaxial layer.

[0010] Optionally, from the first surface to the second surface, the epitaxial layer includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence; the annular groove is located on the surface of the first semiconductor layer away from the second semiconductor layer, and the annular groove exposes at most the second semiconductor layer; the first groove is located on the surface of the second semiconductor layer away from the first semiconductor layer, and at least exposes the first semiconductor layer.

[0011] Optionally, the light-emitting diode further includes: a transparent conductive layer, a metal reflective layer and a metal protective layer; the transparent conductive layer is located on the first surface, the passivation layer also covers the transparent conductive layer, the passivation layer has a through hole exposing the transparent conductive layer, the metal reflective layer is located on the surface of the passivation layer away from the second surface, and is connected to the transparent conductive layer through the through hole, and the metal protective layer is located on the surface of the passivation layer away from the second surface, and covers the metal reflective layer.

[0012] Optionally, the light-emitting diode also includes: an insulating layer, a bonding metal layer and a conductive substrate; the first surface also has a second groove, the first groove and the second groove are arranged at intervals, the annular groove surrounds the second groove, and the passivation layer is also located in the second groove; the insulating layer is located on the surface of the passivation layer away from the second surface and in the second groove, and the insulating layer covers the metal protective layer, the surface of the insulating layer away from the second surface has a via hole exposing the bottom of the second groove, the bonding metal layer is located on the surface of the insulating layer away from the second surface, and is connected to the bottom of the second groove through the via hole, and the conductive substrate is located on the surface of the bonding metal layer away from the second surface.

[0013] Optionally, the light emitting diode further includes a connecting electrode, and the connecting electrode is located in the first groove.

[0014] An embodiment of the present disclosure provides a method for preparing a light emitting diode, the method comprising: preparing an epitaxial layer on a substrate; forming an annular groove on a first surface of the epitaxial layer, the annular groove surrounding the epitaxial layer along a peripheral edge of the first surface, and the annular groove being located on a side wall of the epitaxial layer.

[0015] Optionally, after the annular groove is formed on the first surface of the epitaxial layer, the method further includes: forming a passivation layer on the first surface so that the passivation layer extends into the annular groove; bonding the side of the light-emitting diode having the passivation layer to a conductive substrate, and removing the substrate to expose the second surface of the epitaxial layer; forming a first groove on the second surface of the epitaxial layer, the annular groove surrounds the first groove, at most a portion of the orthographic projection of the first groove on the second surface intersects with the orthographic projection of the annular groove on the second surface, and the first surface and the second surface are two opposite surfaces on the epitaxial layer.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] The light-emitting diode provided in the embodiment of the present disclosure has an annular groove arranged on the first surface of the epitaxial layer. The annular groove surrounds the epitaxial layer along the peripheral edge of the first surface, and the annular groove is located on the side wall of the epitaxial layer. The distribution area of ​​the annular groove arranged in this way can avoid the removal of more epitaxial layers in the central area when preparing the annular groove to ensure the light-emitting effect of the epitaxial layer; at the same time, by setting the annular groove, when the stress inside the epitaxial layer is transmitted to the annular groove, the stress can be released, the stress generated inside the epitaxial layer can be reduced, the warping of the light-emitting diode can be avoided, the light-emitting diode can be prevented from being broken, and the problem of epitaxial layer falling off can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0020] Figure 2 It is a stress comparison diagram of an epitaxial layer provided with an annular groove according to an embodiment of the present disclosure;

[0021] Figure 3 is a flow chart of manufacturing a light emitting diode provided by an embodiment of the present disclosure;

[0022] Figure 4 It is a preparation state diagram of a light emitting diode provided by the present disclosure;

[0023] Figure 5 It is a preparation state diagram of a light emitting diode provided by the present disclosure;

[0024] Figure 6It is a preparation state diagram of a light emitting diode provided by the present disclosure;

[0025] Figure 7 It is a preparation state diagram of a light emitting diode provided by the implementation of the present disclosure.

[0026] The descriptions of the marks in the figure are as follows:

[0027] 10. Substrate;

[0028] 20, epitaxial layer; 21, first semiconductor layer; 210, annular groove; 211, second groove; 22, multi-quantum well layer; 23, second semiconductor layer; 231, first groove;

[0029] 30. Passivation layer;

[0030] 41. Transparent conductive layer; 42. Metal reflective layer; 43. Metal protective layer;

[0031] 51. Insulating layer; 52. Bonding metal layer; 53. Conductive substrate;

[0032] 60. Connect the electrodes. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0034] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0035] Figure 1 Schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 1As shown, the light emitting diode includes an epitaxial layer 20 , a first surface of the epitaxial layer 20 has an annular groove 210 , the annular groove 210 surrounds the epitaxial layer 20 along the peripheral edge of the first surface, and the annular groove 210 is located on the sidewall of the epitaxial layer 20 .

[0036] The light emitting diode provided in the embodiment of the present disclosure is provided with an annular groove 210 on the first surface of the epitaxial layer 20. The annular groove 210 surrounds the epitaxial layer 20 along the peripheral edge of the first surface, and the annular groove 210 is located on the side wall of the epitaxial layer 20. The distribution area of ​​the annular groove 210 is set in this way to avoid removing more central areas of the epitaxial layer 20 when preparing the annular groove 210, so as to ensure the light emitting effect of the epitaxial layer 20.

[0037] Figure 2 2 is a stress comparison diagram of an epitaxial layer 20 provided with an annular groove 210 according to an embodiment of the present disclosure. Figure 2 As shown, the light emitting diode on the left side of the vertical line in the figure is a light emitting diode without an annular groove 210 on the epitaxial layer 20, and the light emitting diode on the right side of the vertical line in the figure is a light emitting diode with an annular groove 210 on the epitaxial layer 20. According to the accompanying drawings, the stress of the epitaxial layer 20 without the annular groove 210 is higher than 0.39, while the stress of the epitaxial layer 20 with the annular groove 210 is lower than 0.4. Therefore, by providing the annular groove 210, the stress generated in the epitaxial layer 20 can be effectively reduced. This is because when the stress inside the epitaxial layer 20 is transmitted to the annular groove 210, the epitaxial layer 20 in the area where the annular groove 210 is located is not continuous, and the stress cannot continue to be transmitted when it is transmitted to the annular groove 210, so it is released at the annular groove 210, thereby reducing the stress generated inside the epitaxial layer 20, avoiding the warping of the light emitting diode, preventing the light emitting diode from breaking, and improving the problem of the epitaxial layer 20 falling off.

[0038] Optionally, the width of the annular groove 210 is 3 μm to 10 μm.

[0039] The embodiment of the present disclosure sets the width of the annular groove 210 within the above range to avoid the annular groove 210 being too wide and removing more epitaxial layer 20, thereby affecting the light-emitting effect of the epitaxial layer 20; it can also avoid the annular groove 210 being too small and failing to interrupt stress transmission.

[0040] As an example, in the embodiment of the present disclosure, the width of the annular groove 210 may be 5 μm.

[0041] Optionally, the depth of the annular groove 210 is greater than or equal to 2000 angstroms.

[0042] In the above implementation, by controlling the depth of the annular groove 210 to be no less than 2000 angstroms, it can be ensured that the annular groove 210 releases at least part of the stress in the epitaxial layer 20, thereby preventing the annular groove 210 from being unable to effectively release stress and causing cracks during the laser stripping process.

[0043] As an example, in the embodiment of the present disclosure, the depth of the annular groove 210 is 2500 angstroms.

[0044] Alternatively, if Figure 1 As shown, the light emitting diode further includes a passivation layer 30 , and the passivation layer 30 is located on the first surface and in the annular groove 210 .

[0045] Optionally, the passivation layer 30 may be at least one of a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0046] Exemplarily, the passivation layer 30 may be a silicon oxide layer.

[0047] By forming a passivation layer 30 on the surface of the epitaxial layer 20 to wrap the epitaxial layer 20 , it is possible to prevent the epitaxial layer 20 from contacting other film layers and causing a short circuit, thereby effectively protecting the epitaxial layer 20 .

[0048] like Figure 1 As shown, the second surface of the epitaxial layer 20 has a first groove 231 , and the annular groove 210 surrounds the first groove 231 .

[0049] Among them, at most a portion of the orthographic projection of the first groove 231 on the second surface intersects with the orthographic projection of the annular groove 210 on the second surface, and the first surface and the second surface are two opposite surfaces on the epitaxial layer 20 .

[0050] In the embodiment of the present disclosure, the first groove 231 exposes the semiconductor layer in the epitaxial layer 20 , and the first groove 231 is used to form an electrode so that electricity can be supplied to the semiconductor layer exposed by the first groove 231 through the electrode.

[0051] For example, Figure 1 As shown, the orthographic projection of the first groove 231 on the second surface does not overlap with the orthographic projection of the annular groove 210 on the second surface.

[0052] Since the epitaxial layer 20 in the region where the annular groove 210 is located is relatively thin, and when etching the epitaxial layer 20, over-etching is often performed to ensure that the required depth is etched, the epitaxial layer 20 in the region where the annular groove 210 is located is easily completely etched away during the etching process. This exposes the passivation layer 30 in the region where the annular groove 210 is located to the etching gas environment, and the etching gas easily invades the passivation layer 30 under the continuous bombardment of the etching gas, which may cause leakage problems in the light-emitting diode, thereby affecting the reliability of the light-emitting diode.

[0053] In the embodiment of the present disclosure, when etching the first groove 231, the orthographic projection of the first groove 231 on the second surface is controlled to overlap with the orthographic projection of the annular groove 210 on the second surface, so as to avoid etching the area where the annular groove 210 is located as much as possible. This prevents the passivation layer 30 from being invaded by etching gas, and improves the reliability of the light-emitting diode.

[0054] Alternatively, if Figure 1 As shown, from the first surface to the second surface, the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 stacked in sequence.

[0055] Optionally, one of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer.

[0056] Exemplarily, the first semiconductor layer 21 is a p-type layer, and the second semiconductor layer 23 is an n-type layer.

[0057] Optionally, the n-type layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0058] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0059] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0060] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0061] Optionally, the p-type layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0062] Alternatively, if Figure 1 As shown, the annular groove 210 is located on the surface of the first semiconductor layer 21 away from the second semiconductor layer 23 , and the annular groove 210 at most exposes the second semiconductor layer 23 .

[0063] like Figure 1 As shown, the first groove 231 is located on the surface of the second semiconductor layer 23 away from the first semiconductor layer 21 , and at least exposes the first semiconductor layer 21 .

[0064] Alternatively, if Figure 1 As shown, the light emitting diode further includes a connecting electrode 60 , and the connecting electrode 60 is located in the first groove 231 .

[0065] The connection electrode 60 has the same conductivity type as the first semiconductor layer 21. For example, when the first semiconductor layer 21 is a p-type layer, the connection electrode 60 is a p-electrode. The first groove 231 is used to form a p-electrode, which is connected to an external power source, so that the first semiconductor layer 21 exposed by the first groove 231 is energized.

[0066] Exemplarily, the connection electrode 60 includes a Cr layer, an Al layer, a Ti layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer, and a Ti layer stacked in sequence, and the thickness of each metal layer is 30 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 500 angstroms, 2000 angstroms, and 500 angstroms, respectively.

[0067] Alternatively, if Figure 1 As shown, the light emitting diode further includes: a transparent conductive layer 41 , a metal reflective layer 42 and a metal protective layer 43 .

[0068] like Figure 1 As shown, the transparent conductive layer 41 is located on the first surface, the passivation layer 30 also covers the transparent conductive layer 41, the passivation layer 30 has a through hole exposing the transparent conductive layer 41, the metal reflective layer 42 is located on the surface of the passivation layer 30 away from the second surface, and is connected to the transparent conductive layer 41 through the through hole, and the metal protective layer 43 is located on the surface of the passivation layer 30 away from the second surface, and the metal protective layer 43 covers the metal reflective layer 42.

[0069] For example, the transparent conductive layer 41 may be an indium tin oxide (ITO) layer, which has good transmittance and low resistivity.

[0070] For example, the transparent conductive layer 41 may be an indium zinc oxide (IZO) layer, which has good transmittance and low resistivity.

[0071] Among them, using an ITO layer or an IZO layer as the transparent conductive layer 41 can allow more light to be transmitted from the transparent conductive layer 41, thereby ensuring the light output effect; at the same time, due to the low resistivity, the metal reflective layer 42 is stacked on the transparent conductive layer 41, so that the carriers can be more efficiently conducted from the metal reflective layer 42 to the epitaxial layer 20, thereby improving the injection efficiency.

[0072] Exemplarily, the thickness of the transparent conductive layer 41 may be 600 angstroms to 2000 angstroms. For example, the thickness of the transparent conductive layer 41 is 1500 angstroms.

[0073] In the embodiment of the present disclosure, the metal reflective layer 42 is provided to reflect the light emitted from the epitaxial layer 20 , so that more light is emitted from the light emitting surface of the epitaxial layer 20 , thereby improving the light emitting intensity of the light emitting diode.

[0074] At the same time, a metal protection layer 43 is also covered on the reflective layer to prevent the metal in the metal reflective layer 42 from migrating upwards.

[0075] Optionally, the metal reflective layer 42 includes Ag layers stacked sequentially.

[0076] Since Ag has a good reflective effect, providing an Ag layer in the metal reflective layer 42 can enhance the reflection of light by the metal reflective layer 42 and improve the light emitting brightness of the light emitting surface of the light emitting diode.

[0077] Optionally, the metal protection layer 43 includes a Ni layer or a TiW layer.

[0078] The Ni layer has good corrosion resistance and wear resistance, and the TiW layer can be successfully deposited on other films as an adhesion layer without peeling or cracking. The alternating stacked Ni and TiW layers can act as a barrier layer to protect the silver mirror.

[0079] Exemplarily, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0080] Exemplarily, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0081] Exemplarily, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0082] Alternatively, if Figure 1 As shown, the light emitting diode further includes: an insulating layer 51 , a bonding metal layer 52 and a conductive substrate 53 .

[0083] like Figure 1 As shown, the first surface further has a second groove 211 , the first groove 231 and the second groove 211 are arranged at intervals, the annular groove 210 surrounds the second groove 211 , and the passivation layer 30 is also located in the second groove 211 .

[0084] The second groove 211 is on the surface of the first semiconductor layer 21 and exposes the surface of the second semiconductor layer 23 .

[0085] like Figure 1 As shown, the insulating layer 51 is located on the surface of the passivation layer 30 away from the second surface and in the second groove 211 , and the insulating layer 51 covers the metal protection layer 43 .

[0086] Exemplarily, the insulating layer 51 may be at least one of a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0087] Exemplarily, the insulating layer 51 may be a silicon oxide layer.

[0088] By providing the insulating layer 51 to wrap the metal protection layer 43 , the problem of short circuit caused by connection between other film layers and the metal protection layer 43 can be avoided, thereby improving reliability.

[0089] like Figure 1 As shown, the surface of the insulating layer 51 away from the second surface has a via hole exposing the bottom of the second groove 211, the bonding metal layer 52 is located on the surface of the insulating layer 51 away from the second surface, and is connected to the bottom of the second groove 211 through the via hole, and the conductive substrate 53 is located on the surface of the bonding metal layer 52 away from the second surface.

[0090] By opening the second groove 211 to expose the second semiconductor layer 23, the conductive substrate 53 can be electrically connected to the second semiconductor layer 23 through the bonding metal layer 52. When the light-emitting diode needs to be controlled to emit light, power is supplied to the conductive substrate 53 and the connecting electrode 60 respectively, so that current can be injected into the first semiconductor layer 21 and the second semiconductor layer 23 respectively, so as to achieve the purpose of controlling the light-emitting diode to emit light.

[0091] Illustratively, the bonding metal layer 52 may be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0092] The thickness of the first Al layer is 8000 angstroms to 12000 angstroms, the thickness of the first Ti layer is 100 angstroms to 500 angstroms, the thickness of the second Al layer is 8000 angstroms to 12000 angstroms, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms, and the thickness of the Au layer is 2000 angstroms to 5000 angstroms.

[0093] For example, the thickness of the first Al layer is 10000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10000 angstroms, the thickness of the second Ti layer is 1000 angstroms, and the thickness of the Au layer is 3000 angstroms.

[0094] Exemplarily, the conductive substrate 53 may be a silicon substrate.

[0095] Figure 3 FIG. 1 is a flow chart of manufacturing a light emitting diode according to an embodiment of the present disclosure. Figure 3 As shown, the preparation method comprises:

[0096] Step S11 : preparing an epitaxial layer 20 on the substrate 10 .

[0097] For example, the substrate may be a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the LED has good luminous effect and stability.

[0098] The process of preparing the epitaxial layer 20 may include the following steps:

[0099] First, if Figure 4 As shown, the epitaxial layer 20 grown on the sapphire substrate 10 includes a second semiconductor layer 23, a multi-quantum well layer 22 and a first semiconductor layer 21 which are stacked in sequence.

[0100] The sapphire substrate may be pre-treated, placed in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and baked for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0101] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0102] For example, the first semiconductor layer 21 may be a p-type layer, and the second semiconductor layer 23 may be an n-type layer.

[0103] Optionally, the n-type layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0104] The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 torr to 300 torr.

[0105] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0106] When growing the multi-quantum well layer 22, the pressure of the MOCVD reaction chamber is controlled at 200 torr. When growing the InGaN quantum well layer, the temperature of the reaction chamber is 760° C. to 780° C. When growing the GaN quantum barrier layer, the temperature of the reaction chamber is 860° C. to 890° C.

[0107] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0108] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0109] Optionally, the p-type layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0110] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0111] Then, the epitaxial layer 20 is etched to form a second groove 211 on the surface of the first semiconductor layer 21 to expose the second semiconductor layer 23 .

[0112] Step S12 : forming an annular groove 210 on the first surface of the epitaxial layer 20 .

[0113] The annular groove 210 is located on the surface of the first semiconductor layer 21 , the annular groove 210 surrounds the epitaxial layer 20 along the peripheral edge of the first surface, and the annular groove 210 is located on the sidewall of the epitaxial layer 20 .

[0114] Optionally, the width of the annular groove 210 is 3 μm to 10 μm.

[0115] As an example, in the embodiment of the present disclosure, the width of the annular groove 210 may be 5 μm.

[0116] Optionally, the depth of the annular groove 210 is greater than or equal to 2000 angstroms.

[0117] As an example, in the embodiment of the present disclosure, the depth of the annular groove 210 is 2500 angstroms.

[0118] After step S12, the following steps may also be included:

[0119] The first step, such as Figure 5 As shown, a transparent conductive layer 41 is formed on the surface of the first semiconductor layer 21 .

[0120] The transparent conductive layer 41 is located outside the second groove 211 .

[0121] Exemplarily, the transparent conductive layer 41 is an indium tin oxide layer or an indium zinc oxide layer.

[0122] Exemplarily, the thickness of the transparent conductive layer 41 is 100 angstroms to 300 angstroms. For example, the thickness of the transparent conductive layer 41 is 200 angstroms.

[0123] In the second step, a passivation layer 30 is formed on the first surface, so that the passivation layer 30 extends into the annular groove 210 and covers the transparent conductive layer 41 .

[0124] The passivation layer 30 has a through hole exposing the transparent conductive layer 41 .

[0125] Optionally, the passivation layer 30 may be at least one of a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0126] Exemplarily, the passivation layer 30 may be a silicon oxide layer.

[0127] The third step is Figure 5 As shown, a metal reflective layer 42 is formed on the surface of the passivation layer 30 , and the metal reflective layer 42 is connected to the transparent conductive layer 41 through a through hole.

[0128] The fourth step is Figure 5 As shown, a metal protection layer 43 is formed on the surface of the passivation layer 30 , so that the metal protection layer 43 covers the metal reflective layer 42 .

[0129] Step 5: Figure 5 As shown, an insulating layer 51 is formed on the surface of the passivation layer 30 away from the second surface and in the second groove 211 , so that the insulating layer 51 covers the metal protection layer 43 .

[0130] Step 6: Figure 6 As shown, the side of the light emitting diode having the passivation layer 30 is bonded to the conductive substrate 53 , and the substrate 10 is removed to expose the second surface of the epitaxial layer 20 .

[0131] Specifically, it may include: first, Figure 6 As shown, a bonding metal layer 52 is formed on the surface of the insulating layer 51 and in the second groove 211 , so that the bonding metal layer 52 is electrically connected to the second semiconductor layer 23 through the second groove 211 .

[0132] Then, if Figure 6 As shown, a bonding metal layer 52 is formed on a conductive substrate 53 , and the bonding metal layer 52 of the conductive substrate 53 is bonded to the bonding metal layer 52 on the epitaxial layer 20 .

[0133] Exemplarily, the conductive substrate 53 may be a silicon substrate.

[0134] Next, the sapphire substrate is removed by laser lift-off to expose the second semiconductor layer 23 .

[0135] Step 7: Figure 7 As shown, a first groove 231 is formed on the second surface of the epitaxial layer 20 .

[0136] like Figure 7 As shown, the annular groove 210 surrounds the first groove 231 , and at most a portion of the orthographic projection of the first groove 231 on the second surface intersects with the orthographic projection of the annular groove 210 on the second surface. The first surface and the second surface are two opposite surfaces on the epitaxial layer 20 .

[0137] For example, Figure 7 As shown, the orthographic projection of the first groove 231 on the second surface does not overlap with the orthographic projection of the annular groove 210 on the second surface.

[0138] Since the epitaxial layer 20 in the region where the annular groove 210 is located is relatively thin, and when etching the epitaxial layer 20, over-etching is often performed to ensure that the required depth is etched, the epitaxial layer 20 in the region where the annular groove 210 is located is easily completely etched away during the etching process. This exposes the passivation layer 30 in the region where the annular groove 210 is located to the etching gas environment, and the etching gas easily invades the passivation layer 30 under the continuous bombardment of the etching gas, which may cause leakage problems in the light-emitting diode, thereby affecting the reliability of the light-emitting diode.

[0139] In the embodiment of the present disclosure, when etching the first groove 231, the orthographic projection of the first groove 231 on the second surface is controlled to overlap with the orthographic projection of the annular groove 210 on the second surface, so as to avoid etching the area where the annular groove 210 is located as much as possible. This prevents the passivation layer 30 from being invaded by etching gas, and improves the reliability of the light-emitting diode.

[0140] Step 8: Figure 1 As shown, a connection electrode 60 is formed in the first groove 231 .

[0141] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises an epitaxial layer (20), wherein a first surface of the epitaxial layer (20) has an annular groove (210), the annular groove (210) surrounds the epitaxial layer (20) along a peripheral edge of the first surface, and the annular groove (210) is located on a side wall of the epitaxial layer (20).

2. The light emitting diode according to claim 1, characterized in that: The width of the annular groove (210) is 3 μm to 10 μm.

3. The light emitting diode according to claim 1, characterized in that: The depth of the annular groove (210) is greater than or equal to 2000 angstroms.

4. The light emitting diode according to any one of claims 1 to 3, characterized in that: The light emitting diode further comprises a passivation layer (30), wherein the passivation layer (30) is located on the first surface and in the annular groove (210); The second surface of the epitaxial layer (20) has a first groove (231), the annular groove (210) surrounds the first groove (231), at most a portion of the orthographic projection of the first groove (231) on the second surface intersects with the orthographic projection of the annular groove (210) on the second surface, and the first surface and the second surface are two opposite surfaces on the epitaxial layer (20).

5. The light emitting diode according to claim 4, characterized in that: From the first surface to the second surface, the epitaxial layer (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22) and a second semiconductor layer (23) stacked in sequence; The annular groove (210) is located on a surface of the first semiconductor layer (21) away from the second semiconductor layer (23), and the annular groove (210) at most exposes the second semiconductor layer (23); The first groove (231) is located on a surface of the second semiconductor layer (23) away from the first semiconductor layer (21), and at least exposes the first semiconductor layer (21).

6. The light emitting diode according to claim 4, characterized in that: The light emitting diode further comprises: a transparent conductive layer (41), a metal reflective layer (42) and a metal protective layer (43); The transparent conductive layer (41) is located on the first surface, the passivation layer (30) also covers the transparent conductive layer (41), the passivation layer (30) has a through hole exposing the transparent conductive layer (41), the metal reflective layer (42) is located on a surface of the passivation layer (30) away from the second surface, and is connected to the transparent conductive layer (41) through the through hole, and the metal protective layer (43) is located on a surface of the passivation layer (30) away from the second surface, and covers the metal reflective layer (42).

7. The light emitting diode according to claim 6, characterized in that: The light emitting diode further comprises: an insulating layer (51), a bonding metal layer (52) and a conductive substrate (53); The first surface also has a second groove (211), the first groove (231) and the second groove (211) are arranged at intervals, the annular groove (210) surrounds the second groove (211), and the passivation layer (30) is also located in the second groove (211); The insulating layer (51) is located on a surface of the passivation layer (30) away from the second surface and in the second groove (211), and the insulating layer (51) covers the metal protection layer (43); the surface of the insulating layer (51) away from the second surface has a via hole exposing the bottom of the second groove (211); the bonding metal layer (52) is located on a surface of the insulating layer (51) away from the second surface and is connected to the bottom of the second groove (211) through the via hole; and the conductive substrate (53) is located on a surface of the bonding metal layer (52) away from the second surface.

8. The light emitting diode according to claim 4, characterized in that: The light emitting diode further comprises a connecting electrode (60), wherein the connecting electrode (60) is located in the first groove (231).

9. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: preparing an epitaxial layer on a substrate; An annular groove is formed on the first surface of the epitaxial layer. The annular groove surrounds the epitaxial layer along the peripheral edge of the first surface and is located on the side wall of the epitaxial layer.

10. The preparation method according to claim 9, characterized in that: After forming the annular groove on the first surface of the epitaxial layer, the method further comprises: forming a passivation layer on the first surface, so that the passivation layer extends into the annular groove; Bonding the side of the light emitting diode having the passivation layer to a conductive substrate, and removing the substrate to expose the second surface of the epitaxial layer; A first groove is formed on the second surface of the epitaxial layer, the annular groove surrounds the first groove, at most a portion of the orthographic projection of the first groove on the second surface intersects with the orthographic projection of the annular groove on the second surface, and the first surface and the second surface are two opposite surfaces on the epitaxial layer.

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