Flip light-emitting diode chip and preparation method thereof

Abstract

The invention belongs to the technical field of photoelectron manufacturing, and particularly relates to a flip light-emitting diode chip and a preparation method thereof, and the diode chip comprises a first contact electrode layer which is disposed in a first contact region on the surface of a first semiconductor layer; the first reflection electrode layer covers the second contact region, the top surface of the first contact electrode layer and the inner side part of the third contact region; the first contact area and the second contact area are at least partially crossed, and the third contact area is an area except the first contact area and the second contact area; the second semiconductor contact layer is arranged on the second semiconductor layer and covers a fourth contact region of the second semiconductor layer; the second contact electrode layer is arranged on the second semiconductor contact layer and covers the area where the second contact electrode layer is located; the second reflection electrode layer is arranged on the second semiconductor layer and covers the top surface of the second contact electrode layer and the inner side parts of the fifth contact region and the sixth contact region; the fourth contact area and the fifth contact area are at least partially arranged in a crossed mode, and the sixth contact area is an area except the fourth contact area and the fifth contact area. Through the arrangement, the light emitting efficiency is improved.

Description

Technical Field

[0001] The present application belongs to the field of optoelectronic manufacturing technology, and specifically relates to a flip-chip light emitting diode chip and a preparation method thereof. Background Art

[0002] Due to the excellent disinfection effect of the light-emitting band on surface viruses and the fact that it is a non-polluting clean energy source, deep ultraviolet light-emitting diodes have become one of the hot spots for research and development in recent years. Since the p-type AlGaN layer of deep ultraviolet light-emitting diodes has a high work function, it is difficult to find a suitable metal electrode when preparing light-emitting diode chips, which makes it impossible to form a good ohmic contact between metal and semiconductor. Relevant researchers have added a thin p-type GaN layer on the p-type AlGaN layer to form an ohmic contact with the metal. However, the p-type GaN layer absorbs light in the deep ultraviolet band, resulting in poor light output efficiency.

[0003] On the other hand, the n-type electrode layer also needs to be adapted to the semiconductor layer for ohmic contact, so some metals with good adaptability but absorbing deep ultraviolet light have to be selected, which will lead to poor light output efficiency of the deep ultraviolet LED chip. Summary of the invention

[0004] The present application is proposed based on the above-mentioned requirements of the prior art. The technical problem to be solved by the present application is to provide a flip-chip light-emitting diode chip and a preparation method to improve the performance of the light-emitting diode chip.

[0005] In order to solve the above problems, the technical solutions provided by this application include:

[0006] Provided is a flip-chip light-emitting diode chip, comprising: an epitaxial structure located at the bottom of the diode chip, the epitaxial structure comprising a first semiconductor layer; a first contact electrode layer arranged on a first portion of the surface of the first semiconductor layer, covering a first contact region on the first portion; a first reflective electrode layer arranged on a first portion of the surface of the first semiconductor layer, covering a second contact region on the first portion, a top surface of the first contact electrode layer, and an inner portion of a third contact region; the first contact region and the second contact region are at least partially arranged to cross each other, the third contact region comprising a region on the first portion except the first contact region and the second contact region; a second semiconductor layer arranged on a second portion of the first semiconductor layer The second part is connected to the first part; a second semiconductor contact layer is arranged on the second semiconductor layer, covering the fourth contact area of ​​the second semiconductor layer; a second contact electrode layer is arranged on the second semiconductor contact layer and covers the area where the second contact electrode layer is located; a second reflective electrode layer is arranged on the second semiconductor layer, covering the top surface of the second contact electrode layer, the fifth contact area and the inner part of the sixth contact area; the fourth contact area and the fifth contact area are at least partially cross-arranged, and the sixth contact area includes the area on the second part except the fourth contact area and the fifth contact area; a current spreading layer, a passivation layer and a pad electrode are arranged in sequence on the first semiconductor layer and the second semiconductor layer.

[0007] The above arrangement can reduce the space occupied by the first contact electrode layer and the second contact electrode layer, thereby reducing the absorption of light, so that more light is emitted to the outside of the chip, and the light extraction rate is improved; in addition, the first contact electrode layer and the first reflective electrode layer are at least partially cross-arranged, and the second contact electrode layer and the second reflective electrode layer are at least partially cross-arranged, which has higher reliability than the contact electrode layer being arranged as a whole in the prior art. When the contact electrode layers are arranged in blocks with intervals, if part of the contact electrode layers is abnormal, the semiconductor chip will not fail immediately, but gradually lose its effectiveness; when the contact electrode layers are arranged as a whole, when part of the contact electrode layers is abnormal, the semiconductor chip will easily fail as a whole.

[0008] Preferably, the first contact area and the second contact area are connected, and the first contact area is evenly arranged in the left-right direction and the front-back direction; the second contact area is evenly arranged in the extension direction.

[0009] The above arrangement enables the semiconductor chip to emit light uniformly.

[0010] Preferably, a surface of the first reflective electrode layer and a surface of the second reflective electrode layer are on the same horizontal plane.

[0011] Preferably, the epitaxial structure is arranged on a sapphire substrate, and an AlN buffer layer and an AlN / AlGaN superlattice stress buffer layer are arranged in sequence from bottom to top.

[0012] Preferably, a multi-quantum well structure layer and an electron blocking layer are further provided on the other side of the first semiconductor layer, and are located below the second semiconductor layer.

[0013] A method for preparing a flip-chip light-emitting diode is also provided, comprising: preparing an epitaxial structure on a substrate, the epitaxial structure comprising a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being above the first semiconductor layer, the first semiconductor layer comprising a first contact region, a second contact region and a third contact region, the first contact region and the second contact region being at least partially cross-arranged, and the third contact region being arranged outside the first contact region and the second contact region; the second semiconductor contact layer comprising a fourth contact region, a fifth contact region and a sixth contact region, the fourth contact region and the fifth contact region being at least partially cross-arranged, and the sixth contact region being arranged outside the fourth contact region and the fifth contact region; preparing a second semiconductor contact layer on the second semiconductor layer; etching a portion of the epitaxial structure until a first portion of the first semiconductor layer is exposed, and etching the second semiconductor contact layer so that it only covers the fourth contact region; preparing a first contact electrode layer on the first portion, and preparing a second contact electrode layer on the second semiconductor contact layer; the first contact electrode The first reflective electrode layer covers the first contact area, and the second contact electrode layer covers the second contact electrode layer; a first reflective electrode layer is prepared on the first part, and a second reflective electrode layer is prepared on the second part; the first reflective electrode layer covers the first contact electrode layer, the second contact area and the part of the third contact area close to the first contact area; the second reflective electrode layer covers the second contact electrode layer, the fifth contact area and the part of the sixth contact area close to the first contact area; the surfaces of the first reflective electrode layer and the second reflective electrode layer are located on the same horizontal plane; a current spreading layer is prepared, and a corresponding current spreading layer is prepared on the first reflective electrode layer and the second reflective electrode layer; a passivation layer is prepared, and the area covered by the passivation layer includes the exposed part of the third contact area, the exposed part of the sixth contact area and the partial area close to the edge of the current spreading layer; a first pad electrode and a second pad electrode are prepared, the first pad electrode covers the exposed area corresponding to the first reflective electrode layer, and the second pad electrode covers the exposed area corresponding to the second reflective electrode layer.

[0014] The above arrangement can reduce the space occupied by the first contact electrode layer and the second contact electrode layer, thereby reducing the absorption of light, allowing more light to be emitted outside the chip, and improving the light extraction rate; in addition, the first contact electrode layer and the first reflective electrode layer are at least partially cross-arranged, and the second contact electrode layer and the second reflective electrode layer are at least partially cross-arranged, which has higher reliability than the block arrangement of the contact electrode layer in the prior art. When the contact electrode layer is arranged in blocks at intervals, if part of the contact electrode layer is abnormal, the semiconductor chip will not fail immediately, but gradually lose its effectiveness; when the contact electrode layer is arranged in a block, when part of the contact electrode layer is abnormal, the semiconductor chip will easily fail as a whole. In addition, the structural layers on the first semiconductor layer and the second semiconductor layer are prepared at the same time to simplify the process.

[0015] A method for preparing a flip-chip light-emitting diode is also provided, comprising: preparing an epitaxial structure on a substrate, the epitaxial structure comprising a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being on the first semiconductor layer, the first semiconductor layer comprising a first contact region, a second contact region and a third contact region, the first contact region and the second contact region being at least partially cross-arranged, and the third contact region being arranged outside the first contact region and the second contact region; the second semiconductor layer comprising a fourth contact region, a fifth contact region and a sixth contact region, the fourth contact region and the fifth contact region being at least partially cross-arranged, and the sixth contact region being arranged outside the fourth contact region and the fifth contact region; etching one side of the epitaxial structure to expose a first portion of the first semiconductor layer, and preparing a first contact electrode layer on the first portion, the first contact electrode layer covering the first contact region of the first portion; preparing a first reflective electrode layer on the first portion, the first reflective electrode layer covering the first contact region of the first portion A layer covers the first contact electrode layer, the second contact area and the portion of the third contact area close to the first contact area; a second semiconductor contact layer is prepared on the second semiconductor layer, and the second semiconductor contact layer is etched to cover only the fourth contact area; a second contact electrode layer is prepared, and the second contact electrode layer covers the second semiconductor contact layer; a second reflective electrode layer is prepared, and covers the second contact electrode layer, the fifth contact area and the portion of the sixth contact area close to the fourth contact area; a current spreading layer is prepared, and a corresponding current spreading layer is prepared on the first reflective electrode layer and the second reflective electrode layer; a passivation layer is prepared, and the area covered by the passivation layer includes the exposed portion of the third contact area, the exposed portion of the sixth contact area and the partial area close to the edge of the current spreading layer; a first pad electrode and a second pad electrode are prepared, and the first pad electrode covers the exposed area corresponding to the first reflective electrode layer, and the second pad electrode covers the exposed area corresponding to the second reflective electrode layer.

[0016] The above arrangement reduces the space occupied by the first contact electrode layer and the second contact electrode layer, thereby reducing the absorption of light, allowing more light to be emitted outside the chip, and improving the light extraction rate; in addition, the first contact electrode layer and the first reflective electrode layer are at least partially cross-arranged, and the second contact electrode layer and the second reflective electrode layer are at least partially cross-arranged, which has higher reliability than the block arrangement of the contact electrode layer in the prior art. When the contact electrode layer is arranged in blocks at intervals, if part of the contact electrode layer is abnormal, the semiconductor chip will not fail immediately, but gradually lose its effectiveness; when the contact electrode layer is arranged in a block, when part of the contact electrode layer is abnormal, the semiconductor chip will easily fail as a whole. In addition, the structural layers on the first semiconductor layer and the second semiconductor layer are prepared separately to ensure good chip quality.

[0017] Preferably, the first contact area and the second contact area are connected, and the first contact area is evenly arranged in the left-right direction and the front-back direction; the second contact area is evenly arranged in the extension direction.

[0018] Preferably, the first reflective electrode layer is formed by metal evaporation, and the evaporated metal is one or a composite form of several metals selected from the group consisting of Al, Rh, Zn, Ni and Au.

[0019] Preferably, the second reflective electrode layer is formed by metal evaporation, and the evaporated metal is one or a composite metal of several metals selected from the group consisting of Al, Rh, Ni and Au.

[0020] Compared with the prior art, the present application reduces the absorption of light inside the semiconductor chip by reducing the space occupied by the first contact electrode layer and the second contact electrode layer, so that more light can be emitted to the outside of the chip, thereby improving the light extraction rate; in addition, the first contact electrode layer and the first reflective electrode layer are at least partially cross-arranged, and the second contact electrode layer and the second reflective electrode layer are at least partially cross-arranged, which has higher reliability than the prior art in which the contact electrode layers are arranged in blocks. When the contact electrode layers are arranged in blocks with intervals, if part of the contact electrode layers is abnormal, the semiconductor chip will not fail immediately, but will gradually lose its effectiveness; when the contact electrode layers are arranged in blocks, when part of the contact electrode layers is abnormal, the semiconductor chip will easily fail as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this specification. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0022] Figure 1 A cross-sectional structure diagram of a flip-chip light-emitting diode chip in an embodiment of the present application is disclosed;

[0023] Figure 2 A cross-sectional view of the epitaxial structure of a flip-chip light-emitting diode chip in an embodiment of the present application is disclosed;

[0024] Figure 3 Disclosed is another angle schematic diagram of the flip-chip light emitting diode chip in the embodiment of the present application;

[0025] Figure 4 A flow chart of the steps of the method for preparing a flip-chip light-emitting diode chip in an embodiment of the present application is disclosed;

[0026] Figure 5 A flow chart of the steps of another method for preparing a flip-chip light-emitting diode chip in an embodiment of the present application is disclosed.

[0027] Reference numerals:

[0028] 1. substrate; 2. AlN buffer layer; 3. AlN / AlGaN superlattice stress buffer layer; 4. first semiconductor layer; 5. multi-quantum well structure layer; 6. electron blocking layer; 7. second semiconductor layer; 8. second semiconductor contact layer; 9. first contact electrode layer; 10. first reflective electrode layer; 11. second contact electrode layer; 12. second reflective electrode layer; 13. current spreading layer; 14. passivation layer; 15. first pad electrode; 16. second pad electrode. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the term "connected" should be understood in a broad sense, for example, it can be a fixed connection, or a detachable connection, or an integral connection can be a mechanical connection, or an electrical connection can be a direct connection, or it can be indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0031] The terms "top", "bottom", "above", "lower", and "on" used throughout the description are relative to the relative positions of components of a device, such as the relative positions of the top and bottom substrates within a device. It is understood that devices are multifunctional regardless of their orientation in space.

[0032] To facilitate understanding of the embodiments of the present application, further explanation will be given below with reference to specific embodiments in conjunction with the accompanying drawings. The embodiments do not constitute a limitation on the embodiments of the present application.

[0033] Example 1

[0034] This embodiment provides a method for preparing a flip-chip light emitting diode chip, such as Figure 4 shown.

[0035] The preparation method comprises:

[0036] An epitaxial structure is prepared on a substrate 1 .

[0037] The epitaxial structure includes a sapphire substrate 1 arranged in sequence from bottom to top, and an AlN buffer layer 2, an AlN / AlGaN superlattice stress buffer layer 3, a first semiconductor layer 4, a multi-quantum well structure layer 5, an electron blocking layer 6, a second semiconductor layer 7 and a second semiconductor contact layer 8 grown in sequence on the sapphire substrate 1.

[0038] A first contact electrode layer 9 is formed on the first semiconductor layer 4 .

[0039] Determine the platform where the first semiconductor layer 4 is located, and perform etching by ICP dry method. The first semiconductor includes a first part and a second part, and the first part is exposed by etching to facilitate the growth of other layers thereon. The first part includes a first contact area, a second contact area and a third contact area, and the first contact area and the second contact area are at least partially cross-arranged, and the third part is arranged around the first part and the second part. Furthermore, the first contact area includes a part extending in the left-right direction and a part extending in the up-down direction, which are uniformly distributed along the extension direction; similarly, although the second contact area only extends in the left-right direction, it is also uniformly distributed along the extension direction.

[0040] Determine the area covered by the first contact electrode layer 9 on the surface of the first semiconductor layer 4, the covered area is less than half of the surface area of ​​the first semiconductor, and the area is circled by photoresist. Evaporate a contact metal in the circled area, and the contact metal can be a composite of one or more metals of Ti and Cr. Preferably, the contact metal is Ti. The circled area corresponds to the first contact area.

[0041] The formed contact metal is subjected to high temperature rapid annealing to form a first contact electrode layer 9, thereby forming an ohmic contact between the metal and the semiconductor. The annealing temperature is between 600-1000°C. Preferably, the annealing temperature is 850°C. The annealing time is between 30-600 seconds. Preferably, the annealing time is 90 seconds. The air atmosphere during annealing is a protective gas. Preferably, the air atmosphere during annealing is nitrogen.

[0042] Through the above arrangement, the first contact electrode layer 9 only occupies a part of the first semiconductor layer 4, thereby reducing the absorption of the light source inside the flip-chip light-emitting diode by the first contact electrode layer 9. When the reflective electrode layer is prepared thereon, the reflective electrode layer occupies a larger space, which is convenient for effectively reflecting the light source from the flip-chip diode, so as to improve the light extraction efficiency of the flip-chip light-emitting diode. In addition, since the first contact area and the second contact area are arranged at intervals, when an abnormality occurs in one part, the entire chip will not fail immediately. Its reliability is significantly improved compared to the arrangement of the first contact electrode layer 9 as a whole block. The reason is that when the first contact electrode layer 9 forms a whole that is fully connected to each other, if an abnormality occurs in one part, the entire chip will fail.

[0043] A first reflective electrode layer 10 is formed on the first semiconductor layer 4 and the first contact electrode layer 9 .

[0044] The first reflective electrode layer 10 covers an area on the surface of the first semiconductor layer 4 , and the covered area specifically includes the inner parts of the first contact area, the second contact area and the third contact area. When it covers the first contact area, it will cover the surface of the first contact electrode layer 9 .

[0045] A reflective metal is evaporated in the determined area of ​​the first reflective electrode layer 10 by a metal evaporation process. The reflective metal is a composite form of one or more metals selected from Al, Rh, Zn, Ni, and Au. Preferably, the reflective metal is a composite metal of Al and Ni.

[0046] The area where the second semiconductor contact layer 8 is located is adjusted.

[0047] The area on the original second semiconductor contact layer 8 except the second contact electrode layer 11 is determined by photoresist, and the area where the second contact electrode layer 11 is located is less than half of the area originally occupied by the second semiconductor contact layer 8. The surface of the second semiconductor layer 7 includes the second semiconductor layer 7 including a fourth contact area, a fifth contact area and a sixth contact area, the fourth contact area and the fifth contact area are at least partially cross-arranged, and the sixth contact area is arranged outside the fourth contact area and the fifth contact area. Specifically, all areas on the second semiconductor layer 7 except the fourth area are removed by the ICP dry etching method to obtain the adjusted second semiconductor contact layer 8 area.

[0048] Furthermore, the fourth contact area includes a portion extending in the left-right direction and a portion extending in the up-down direction, and is evenly distributed along the extending direction; similarly, although the fifth contact area only extends in the left-right direction, it is also evenly distributed along the extending direction.

[0049] A second contact electrode layer 11 is formed on the second semiconductor contact layer 8 .

[0050] A contact metal is evaporated on the second semiconductor contact layer 8 by a metal evaporation process. The contact metal is a metal selected from Ti, Cr, and Ni or a composite metal of concentrated metals. Preferably, the contact metal is Ni.

[0051] The second contact electrode layer 11 is annealed to form an ohmic contact between the metal and the semiconductor. The annealing temperature of the second contact electrode layer 11 is between 400 and 600 degrees Celsius, preferably, the annealing temperature is 500 degrees Celsius. The annealing time is between 300 and 2100 seconds, preferably, the annealing time is 1500 seconds. The air atmosphere during annealing is air.

[0052] Through the above arrangement, the second contact electrode layer 11 only occupies a part of the second semiconductor contact layer 8, thereby reducing the absorption of the light source inside the flip-chip light-emitting diode by the second contact electrode layer 11. When the reflective electrode layer is prepared thereon, the reflective electrode layer occupies a larger space, which is convenient for effectively reflecting the light source from the flip-chip diode, so as to improve the light extraction efficiency of the flip-chip light-emitting diode. In addition, since the fourth contact area and the fifth contact area are arranged at intervals, when an abnormality occurs in one of the parts, the entire chip will not fail immediately, and its reliability is significantly improved compared to the arrangement of the fourth contact electrode layer as a whole block, because when the fourth contact electrode layer forms a whole that is fully connected to each other, if an abnormality occurs in one part, the entire chip will fail.

[0053] The second reflective electrode layer 12 is formed on the second semiconductor layer 7 and the second contact electrode layer 11 .

[0054] The second reflective electrode layer 12 covers an area on the surface of the second semiconductor layer 7 , which specifically includes the inner parts of the fourth contact area, the fifth contact area and the sixth contact area. When it covers the fifth contact area, it covers the surface of the second contact electrode layer 11 .

[0055] A reflective metal is evaporated on the second reflective electrode layer 12 region by a metal evaporation process. The reflective metal is one or a composite metal of several metals selected from Al, Rh, Ni, and Au. Preferably, the reflective metal is a composite metal of Rh and Ni.

[0056] The current spreading layer 13 is formed on the first reflective electrode layer 10 and the second reflective electrode layer 12 , respectively.

[0057] The area where the current spreading layer 13 is located on the first reflective electrode layer 10 overlaps with the area of ​​the first reflective electrode layer 10 , and the area where the current spreading layer 13 is located on the second reflective electrode layer 12 overlaps with the area of ​​the second reflective electrode layer 12 .

[0058] A passivation layer 14 is formed on the current spreading layer 13 , the first semiconductor layer 4 and the second semiconductor layer 7 .

[0059] The passivation layer 14 completely covers the first semiconductor layer 4 and the second semiconductor layer 7 that are still exposed, and covers part of the current spreading layer 13. Specifically, the passivation layer 14 covers the surrounding area of ​​the current spreading layer 13, and exposes the central area of ​​the current spreading layer 13.

[0060] A pad electrode is formed on the passivation layer 14 and the current spreading layer 13 .

[0061] The pad electrode includes a first pad electrode 15 and a second pad electrode 16, wherein the first pad electrode 15 is disposed above the first semiconductor layer 4, and the area occupied by the first pad electrode 15 includes a first area and a second area. The first area is the current spreading layer 13 exposed to the outside, that is, the central area of ​​the current spreading layer 13. The second area is the area where a portion of the passivation layer 14 is located, and the first area is connected to the second area. The second pad electrode 16 is disposed above the second semiconductor layer 7. The area occupied by the second pad electrode 16 is similar to the area occupied by the first pad electrode 15, including the central area of ​​the current spreading layer 13 corresponding to it and the area of ​​the portion of the passivation layer 14 connected thereto.

[0062] Example 2

[0063] This embodiment provides a method for preparing a flip-chip light emitting diode chip, such as Figure 5 shown.

[0064] The preparation method comprises:

[0065] Preparation of epitaxial structure.

[0066] The epitaxial structure includes a sapphire substrate 1 arranged in sequence from bottom to top, and an AlN buffer layer 2, an AlN / AlGaN superlattice stress buffer layer 3, a first semiconductor layer 4, a multi-quantum well structure layer 5, an electron blocking layer 6, a second semiconductor layer 7 and a second semiconductor contact layer 8 grown in sequence on the sapphire substrate 1.

[0067] A first contact electrode layer 9 is formed on the first semiconductor layer 4 , the region where the second semiconductor contact layer 8 is located is adjusted, and a second contact electrode layer 11 is formed on the second semiconductor contact layer 8 .

[0068] Determine the platform where the first semiconductor layer 4 is located, and perform etching by ICP dry method. The first semiconductor includes a first part and a second part, and the first part is exposed by etching to facilitate the growth of other layers thereon. The first part includes a first contact area, a second contact area and a third contact area, and the first contact area and the second contact area are at least partially cross-arranged, and the third part is arranged around the first part and the second part. Furthermore, the first contact area includes a part extending in the left-right direction and a part extending in the up-down direction, which are uniformly distributed along the extension direction; similarly, although the second contact area only extends in the left-right direction, it is also uniformly distributed along the extension direction.

[0069] The area on the original second semiconductor contact layer 8 except the second contact electrode layer 11 is determined by photoresist, and the area where the second contact electrode layer 11 is located is less than half of the area originally occupied by the second semiconductor contact layer 8. The surface of the second semiconductor layer 7 includes the second semiconductor layer 7 including a fourth contact area, a fifth contact area and a sixth contact area, the fourth contact area and the fifth contact area are at least partially cross-arranged, and the sixth contact area is arranged outside the fourth contact area and the fifth contact area. Specifically, all areas on the second semiconductor layer 7 except the fourth area are removed by the ICP dry etching method to obtain the adjusted second semiconductor contact layer 8 area.

[0070] Furthermore, the fourth contact area includes a portion extending in the left-right direction and a portion extending in the up-down direction, and is evenly distributed along the extending direction; similarly, although the fifth contact area only extends in the left-right direction, it is also evenly distributed along the extending direction.

[0071] By reducing the area of ​​the first semiconductor layer 4 occupied by the first semiconductor contact area and reducing the area of ​​the second semiconductor contact layer 8 occupied by the second semiconductor contact area, the absorption of the light source inside the flip-chip light-emitting diode by the first contact electrode layer 9 and the second contact electrode layer 11 is reduced. When the reflective electrode layer is prepared thereon, the reflective electrode layer occupies a larger space, which is convenient for effectively reflecting the light source from the flip-chip diode to improve the light extraction efficiency of the flip-chip light-emitting diode. In addition, since the first contact area and the second contact area are arranged at intervals, when an abnormality occurs in one part, the entire chip will not fail immediately. Its reliability is significantly improved compared to the arrangement of the first contact electrode layer 9 as a whole block. The reason is that when the first contact electrode layer 9 forms a whole that is fully connected to each other, if an abnormality occurs in one part, the entire chip will fail. The fourth contact area and the fifth contact area are similar.

[0072] Contact metals are evaporated in the first semiconductor contact layer region and the second semiconductor contact layer 8 region respectively, and the contact metals can be a composite of one or more metals selected from Ti and Cr. Preferably, the contact metal is Ti.

[0073] The contact metal formed above is subjected to high temperature rapid annealing treatment to form a first contact electrode layer 9 and a second contact electrode layer 11, thereby forming an ohmic contact between metal and semiconductor.

[0074] A first reflective electrode layer 10 is formed on the first semiconductor layer 4 and the first contact electrode layer 9 , and a first reflective electrode layer 10 is formed on the second semiconductor contact layer 8 and the second contact electrode layer 11 .

[0075] The first reflective electrode layer 10 covers an area on the surface of the first semiconductor layer 4 , and the covered area specifically includes the inner parts of the first contact area, the second contact area and the third contact area. When it covers the first contact area, it will cover the surface of the first contact electrode layer 9 .

[0076] The second reflective electrode layer 12 covers an area on the surface of the second semiconductor layer 7 , which specifically includes the inner parts of the fourth contact area, the fifth contact area and the sixth contact area. When it covers the fifth contact area, it covers the surface of the second contact electrode layer 11 .

[0077] Reflective metal is respectively deposited in the determined area of ​​the first reflective electrode layer 10 and the area of ​​the second reflective electrode layer 12 by a metal evaporation process. The reflective metal is a composite metal of one or more metals selected from Al, Rh, and Ni. Preferably, the reflective metal is a composite metal of Al and Ni.

[0078] The current spreading layer 13 is formed on the first reflective electrode layer 10 and the second reflective electrode layer 12 , respectively.

[0079] The area where the current spreading layer 13 is located on the first reflective electrode layer 10 overlaps with the area of ​​the first reflective electrode layer 10 , and the area where the current spreading layer 13 is located on the second reflective electrode layer 12 overlaps with the area of ​​the second reflective electrode layer 12 .

[0080] A passivation layer 14 is formed on the current spreading layer 13 , the first semiconductor layer 4 and the second semiconductor layer 7 .

[0081] The passivation layer 14 completely covers the first semiconductor layer 4 and the second semiconductor layer 7 that are still exposed, and covers part of the current spreading layer 13. Specifically, the passivation layer 14 covers the surrounding area of ​​the current spreading layer 13, and exposes the central area of ​​the current spreading layer 13.

[0082] A pad electrode is formed on the passivation layer 14 and the current spreading layer 13 .

[0083] The pad electrode includes a first pad electrode 15 and a second pad electrode 16, wherein the first pad electrode 15 is disposed above the first semiconductor layer 4, and the area occupied by the first pad electrode 15 includes a first area and a second area. The first area is the current spreading layer 13 exposed to the outside, that is, the central area of ​​the current spreading layer 13. The second area is the area where a portion of the passivation layer 14 is located, and the first area is connected to the second area. The second pad electrode 16 is disposed above the second semiconductor layer 7. The area occupied by the second pad electrode 16 is similar to the area occupied by the first pad electrode 15, including the central area of ​​the current spreading layer 13 corresponding to it and the area of ​​the portion of the passivation layer 14 connected thereto.

[0084] Example 3

[0085] This embodiment provides a flip-chip light emitting diode chip, such as Figure 1-Figure 3 shown.

[0086] The flip-chip light emitting diode chip comprises a sapphire substrate 1 arranged sequentially from bottom to top, and an AlN buffer layer 2, an AlN / AlGaN superlattice stress buffer layer 3 and a first semiconductor layer 4 grown sequentially on the sapphire substrate 1.

[0087] A first contact electrode layer 9 and a first reflective electrode layer 10 are disposed on the first portion of the first semiconductor layer 4 .

[0088] The first contact electrode layer 9 is arranged in a partial area of ​​the surface of the first semiconductor layer 4. Specifically, the area where the first contact electrode layer 9 is located is less than half of the area of ​​the first semiconductor layer 4. Further, the first semiconductor layer 4 includes a first contact area, a second contact area and a third contact area, the first contact area and the second contact area are at least partially cross-arranged, and the third part is arranged around the first part and the second part. The first contact area includes a part extending in the left-right direction and a part extending in the up-down direction, which are uniformly distributed along the extension direction. The first contact electrode layer 9 is arranged in the first contact area.

[0089] Through the above arrangement, the first contact electrode layer 9 only occupies a part of the first semiconductor layer 4, thereby reducing the absorption of the light source inside the flip-chip light-emitting diode by the first contact electrode layer 9. When the reflective electrode layer is prepared thereon, the reflective electrode layer occupies a larger space, which is convenient for effectively reflecting the light source from the flip-chip diode, so as to improve the light extraction efficiency of the flip-chip light-emitting diode. In addition, since the first contact area and the second contact area are arranged at intervals, when an abnormality occurs in one part, the entire chip will not fail immediately. Its reliability is significantly improved compared to the arrangement of the first contact electrode layer 9 as a whole block. The reason is that when the first contact electrode layer 9 forms a whole that is fully connected to each other, if an abnormality occurs in one part, the entire chip will fail.

[0090] The surface of the first reflective electrode layer 10 is a plane, and its coverage area specifically includes the first contact area, the second contact area and the inner part of the third contact area. When it covers the first contact area, it will cover the surface of the first contact electrode layer 9 .

[0091] A multi-quantum well structure layer 5, an electron blocking layer 6, a second semiconductor layer 7, a second semiconductor contact layer 8, a second contact electrode layer 11, and a second reflective electrode layer 12 are sequentially arranged upward on the second portion of the first semiconductor layer 4.

[0092] The multi-quantum well structure layer 5, the electron blocking layer 6 and the second semiconductor layer 7 are sequentially stacked and arranged, and their coverage areas overlap. The surface of the second semiconductor layer 7 includes the second semiconductor layer 7 including a fourth contact area, a fifth contact area and a sixth contact area, the fourth contact area and the fifth contact area are at least partially cross-arranged, and the sixth contact area is arranged outside the fourth contact area and the fifth contact area.

[0093] Furthermore, the fourth contact area includes a portion extending in the left-right direction and a portion extending in the up-down direction, and is evenly distributed along the extending direction; similarly, although the fifth contact area only extends in the left-right direction, it is also evenly distributed along the extending direction.

[0094] The second semiconductor contact layer 8 is disposed on the second semiconductor layer 7, and the area occupied by the second semiconductor contact layer 8 is less than half of the surface of the second semiconductor layer 7. Specifically, the second semiconductor contact layer 8 is disposed in the fourth contact region.

[0095] The second contact electrode layer 11 is arranged on the second semiconductor contact layer 8, and the coverage areas of the two overlap in the vertical direction. That is, the space occupied by the second contact electrode layer 11 only occupies part of the second semiconductor layer 7, thereby reducing the absorption of the light source inside the flip-chip light-emitting diode by the second contact electrode layer 11. When the reflective electrode layer is prepared thereon, the reflective electrode layer occupies a larger space, which is convenient for effectively reflecting the light source from the flip-chip diode to improve the light extraction efficiency of the flip-chip light-emitting diode. In addition, since the fourth contact area and the fifth contact area are arranged at intervals, when an abnormality occurs in one of the parts, the entire chip will not fail immediately. Its reliability is significantly improved compared to setting the fourth contact electrode layer as a whole block. The reason is that when the fourth contact electrode layer forms a whole that is fully connected to each other, if an abnormality occurs in one part, the entire chip will fail.

[0096] The surface of the second reflective electrode layer 12 is a plane, and its coverage area specifically includes the inner part of the fourth contact area, the fifth contact area, and the sixth contact area. When it covers the fifth contact area, it will cover the surface of the second contact electrode layer 11. In addition, the surfaces of the first reflective electrode layer 10 and the second reflective electrode layer 12 are located in the same horizontal plane.

[0097] A current spreading layer 13 and a passivation layer 14 as well as corresponding pad electrodes are also disposed on the first semiconductor layer 4 and the second semiconductor layer 7 .

[0098] The area where the current spreading layer 13 on the first semiconductor layer 4 is located overlaps with the area where the first reflective electrode layer 10 is located, and the corresponding current spreading layer 13 is in contact with the first reflective electrode layer 10. The area where the current spreading layer 13 on the second semiconductor layer 7 is located overlaps with the area where the second reflective electrode layer 12 is located, and the corresponding current spreading layer 13 is in contact with the second reflective electrode layer 12.

[0099] The passivation layer 14 is distributed on the first semiconductor layer 4, the second semiconductor layer 7 and the corresponding part of the current spreading layer 13. Specifically, the passivation layer 14 covers the first semiconductor layer 4 and the second semiconductor layer 7 on the exposed surface, and also covers the surrounding area of ​​the part of the current spreading layer 13, exposing the central area of ​​the current spreading layer 13.

[0100] The pad electrode includes a first pad electrode 15 and a second pad electrode 16, wherein the first pad electrode 15 is disposed above the first semiconductor layer 4, and the second pad electrode 16 is disposed above the second semiconductor layer 7, and the surfaces of the first pad electrode 15 and the second pad electrode 16 are in a horizontal plane. The first pad electrode 15 occupies the surface of the current spreading layer 13 exposed on the first semiconductor and the surface of the surrounding part of the passivation layer 14. Correspondingly, the second pad electrode 16 occupies the surface of the current spreading layer 13 exposed on the second semiconductor and the surface of the surrounding part of the passivation layer 14.

[0101] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only the specific implementation method of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A flip-chip light emitting diode chip, characterized in that: include: An epitaxial structure, located at the bottom of the diode chip, the epitaxial structure comprising a first semiconductor layer; A first contact electrode layer is disposed on a first portion of the surface of the first semiconductor layer and covers a first contact region on the first portion; A first reflective electrode layer is arranged on a first portion of the surface of the first semiconductor layer, covering a second contact region on the first portion, a top surface of the first contact electrode layer, and an inner portion of a third contact region; the first contact region and the second contact region are at least partially arranged to cross each other, and the third contact region includes a region on the first portion except the first contact region and the second contact region; A second semiconductor layer is disposed on a second portion of the first semiconductor layer, wherein the second portion is in contact with the first portion; a second semiconductor contact layer, disposed on the second semiconductor layer and covering a fourth contact region of the second semiconductor layer; A second contact electrode layer is disposed on the second semiconductor contact layer and covers the area where the second contact electrode layer is located; A second reflective electrode layer is disposed on the second semiconductor layer, covering the top surface of the second contact electrode layer, the fifth contact region, and the inner portion of the sixth contact region; the fourth contact region and the fifth contact region are at least partially intersected, and the sixth contact region includes an area on the second portion except the fourth contact region and the fifth contact region; A current spreading layer, a passivation layer and a pad electrode are sequentially arranged on the first semiconductor layer and the second semiconductor layer.

2. The flip-chip light emitting diode chip according to claim 1, characterized in that: The first contact area and the second contact area are connected, and the first contact area is evenly arranged in the left-right direction and the front-back direction; the second contact area is evenly arranged in the extending direction.

3. The flip-chip light emitting diode chip according to claim 1, characterized in that: The surface of the first reflective electrode layer and the surface of the second reflective electrode layer are on the same horizontal plane.

4. The flip-chip light emitting diode chip according to claim 1, characterized in that: The epitaxial structure is arranged on a sapphire substrate, and an AlN buffer layer and an AlN / AlGaN superlattice stress buffer layer are arranged in sequence from bottom to top.

5. The flip-chip light emitting diode chip according to claim 1, characterized in that: A multi-quantum well structure layer and an electron blocking layer are also disposed on the other side of the first semiconductor layer, and are located under the second semiconductor layer.

6. A method for preparing a flip-chip light-emitting diode, characterized in that: include: An epitaxial structure is prepared on a substrate, wherein the epitaxial structure comprises a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is above the first semiconductor layer, wherein the first semiconductor layer comprises a first contact region, a second contact region and a third contact region, wherein the first contact region and the second contact region are at least partially cross-arranged, and the third contact region is arranged outside the first contact region and the second contact region; and the second semiconductor contact layer comprises a fourth contact region, a fifth contact region and a sixth contact region, wherein the fourth contact region and the fifth contact region are at least partially cross-arranged, and the sixth contact region is arranged outside the fourth contact region and the fifth contact region; forming a second semiconductor contact layer on the second semiconductor layer; Etching a portion of the epitaxial structure until a first portion of the first semiconductor layer is exposed, and etching the second semiconductor contact layer so that it only covers the fourth contact region; Preparing a first contact electrode layer on the first portion, and preparing a second contact electrode layer on the second semiconductor contact layer; the first contact electrode layer covers the first contact area, and the second contact electrode layer covers the second contact electrode layer; A first reflective electrode layer is formed on the first part, and a second reflective electrode layer is formed on the second part; the first reflective electrode layer covers the first contact electrode layer, the second contact area, and a portion of the third contact area close to the first contact area; the second reflective electrode layer covers the second contact electrode layer, the fifth contact area, and a portion of the sixth contact area close to the first contact area; the surfaces of the first reflective electrode layer and the second reflective electrode layer are located on the same horizontal plane; preparing a current spreading layer, and preparing a corresponding current spreading layer on the first reflective electrode layer and the second reflective electrode layer; Prepare a passivation layer, wherein the area covered by the passivation layer includes the exposed portion of the third contact region, the exposed portion of the sixth contact region, and a partial area of ​​the current spreading layer close to the edge; A first pad electrode and a second pad electrode are prepared, wherein the first pad electrode covers an exposed area corresponding to the first reflective electrode layer, and the second pad electrode covers an exposed area corresponding to the second reflective electrode layer.

7. A method for preparing a flip-chip light-emitting diode, characterized in that: include: An epitaxial structure is prepared on a substrate, wherein the epitaxial structure comprises a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is above the first semiconductor layer, wherein the first semiconductor layer comprises a first contact region, a second contact region and a third contact region, wherein the first contact region and the second contact region are at least partially cross-arranged, and the third contact region is arranged outside the first contact region and the second contact region; and the second semiconductor layer comprises a fourth contact region, a fifth contact region and a sixth contact region, wherein the fourth contact region and the fifth contact region are at least partially cross-arranged, and the sixth contact region is arranged outside the fourth contact region and the fifth contact region; Etching the epitaxial structure on one side to expose a first portion of the first semiconductor layer, and preparing a first contact electrode layer on the first portion, wherein the first contact electrode layer covers a first contact region of the first portion; preparing a first reflective electrode layer on the first portion, wherein the first reflective electrode layer covers the first contact electrode layer, the second contact region, and a portion of the third contact region close to the first contact region; A second semiconductor contact layer is prepared on the second semiconductor layer, and the second semiconductor contact layer is etched to cover only the fourth contact area; a second contact electrode layer is prepared, and the second contact electrode layer covers the second semiconductor contact layer; a second reflective electrode layer is prepared, and covers the second contact electrode layer, the fifth contact area, and a portion of the sixth contact area close to the fourth contact area; preparing a current spreading layer, and preparing a corresponding current spreading layer on the first reflective electrode layer and the second reflective electrode layer; Prepare a passivation layer, wherein the area covered by the passivation layer includes the exposed portion of the third contact region, the exposed portion of the sixth contact region, and a partial area of ​​the current spreading layer close to the edge; A first pad electrode and a second pad electrode are prepared, wherein the first pad electrode covers an exposed area corresponding to the first reflective electrode layer, and the second pad electrode covers an exposed area corresponding to the second reflective electrode layer.

8. The method for preparing a flip-chip light-emitting diode according to claim 6 or 7, characterized in that: The first contact area and the second contact area are connected, and the first contact area is evenly arranged in the left-right direction and the front-back direction; the second contact area is evenly arranged in the extending direction.

9. The method for preparing a flip-chip light-emitting diode according to claim 7, characterized in that: The first reflective electrode layer is formed by metal evaporation, and the evaporated metal is one or a composite form of several metals selected from Al, Rh, Zn, Ni and Au.

10. The method for preparing a flip-chip light emitting diode according to claim 7, characterized in that: The second reflective electrode layer is formed by metal evaporation, and the evaporated metal is one or a composite metal of several metals selected from Al, Rh, Ni and Au.

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