Light-emitting device with improved electrode quality and preparation method thereof

Abstract

The present disclosure provides a light-emitting device with improved electrode quality and a method for preparing the same, which belongs to the field of optoelectronic manufacturing technology. The light-emitting device includes an epitaxial layer and an electrode, the electrode is located on the surface of the epitaxial layer, the electrode includes at least two first metal layers and at least two second metal layers alternately stacked, the first metal layer includes an Au layer, and the second metal layer includes an AuGe layer. The embodiments of the present disclosure can improve the problem that the morphology of the electrode is prone to change after annealing, and improve the preparation quality of the electrode.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting device with improved electrode quality and a preparation method thereof. Background Art

[0002] Micro Light Emitting Diode (Micro LED) refers to an ultra-small light-emitting diode with a side length of 10μm to 100μm. Micro LEDs are small in size and can be arranged more densely to greatly improve resolution. They also have self-luminous properties and have the characteristics of high brightness, high contrast, high responsiveness and power saving.

[0003] In the related art, a light emitting diode generally includes a substrate, an epitaxial layer and an electrode. The epitaxial layer is stacked on the substrate, and the electrode is arranged on the surface of the epitaxial layer away from the substrate. By supplying power to the electrode, the light emitting diode is controlled to emit light.

[0004] In order to obtain good ohmic contact characteristics, the electrode needs to be annealed when it is prepared. However, the electrode morphology after annealing is very easy to change. In addition, the random and irregular morphology change of the electrode after annealing will cause the subsequent insulating layer to have a leakage channel with needle-like holes, which will affect the reliability of the light-emitting diode. Summary of the invention

[0005] The embodiment of the present disclosure provides a light-emitting device with improved electrode quality and a method for preparing the same, which can improve the problem that the morphology of the electrode is easily changed after annealing and improve the preparation quality of the electrode. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting device, which includes an epitaxial layer and an electrode, wherein the electrode is located on the surface of the epitaxial layer, and the electrode includes at least two first metal layers and at least two second metal layers alternately stacked, wherein the first metal layer includes an Au layer, and the second metal layer includes an AuGe layer.

[0007] In an implementation of the present disclosure, the thickness of the first metal layer is 50 angstroms to 150 angstroms, and the thickness of the second metal layer is 250 angstroms to 350 angstroms.

[0008] In another implementation of the present disclosure, the electrode further includes a protective layer, and the protective layer is located on a surface of the second metal layer farthest from the epitaxial layer and away from the epitaxial layer.

[0009] In another implementation of the present disclosure, the thickness of the protective layer is 400 angstroms to 600 angstroms.

[0010] In another implementation of the present disclosure, the protective layer includes at least one of an Au layer, a Ni layer, and a Pt layer.

[0011] In a second aspect, an embodiment of the present disclosure provides a method for preparing a light-emitting device, the method comprising: forming an epitaxial layer; forming an electrode on the surface of the epitaxial layer, the electrode comprising at least two first metal layers and at least two second metal layers alternately stacked, the first metal layer comprising an Au layer, and the second metal layer comprising an AuGe layer.

[0012] In another implementation of the present disclosure, the preparation method further includes: when preparing the first metal layer, controlling the plating rate of the first metal layer to be less than or equal to 2 angstroms / second, and preparing the first metal layer with a thickness of 50 angstroms to 150 angstroms; when preparing the second metal layer, controlling the plating rate of the second metal layer to be less than or equal to 2 angstroms / second, and preparing the second metal layer with a thickness of 250 angstroms to 350 angstroms.

[0013] In another implementation of the present disclosure, forming an electrode on the surface of the epitaxial layer includes: forming at least two first metal layers and at least two second metal layers on the surface of the epitaxial layer; forming a protective layer on the surface of the second metal layer farthest from the epitaxial layer, the protective layer including at least one of an Au layer, a Ni layer and a Pt layer.

[0014] In another implementation of the present disclosure, the preparation method further includes: when preparing the protective layer, controlling the coating rate of the protective layer to be less than or equal to 4 angstroms / second, and preparing the protective layer with a thickness of 400 angstroms to 600 angstroms.

[0015] In another implementation of the present disclosure, after forming an electrode on the surface of the epitaxial layer, it also includes: controlling the annealing temperature to 380°C to 450°C for 5s to 150s, controlling the nitrogen introduction rate to 2L / min to 10L / min, and annealing the electrode.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] The electrode of the light-emitting device provided by the embodiment of the present disclosure includes a first metal layer and a second metal layer alternately stacked. Among them, the first metal layer includes an Au layer, and the second metal layer includes an AuGe layer. Since AuGe has a low melting point and the annealing temperature is high, the AuGe layer is prone to morphological changes. After introducing a stacked Au layer with better high temperature resistance on the AuGe layer, the stack formed by the first metal layer and AuGe can be more resistant to high temperatures. Therefore, at least two first metal layers and at least two second metal layers alternately stacked can form an electrode that is more resistant to high temperatures. In this way, when the electrode is annealed, the electrode is not prone to irregular morphological changes even at a higher ambient temperature, thereby preventing the subsequent insulating layer from having leakage channels with needle-like voids, thereby improving the reliability of the light-emitting device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a structural schematic diagram of a light-emitting device provided by an embodiment of the present disclosure;

[0020] Figure 2 is a schematic diagram of the structure of an electrode provided by an embodiment of the present disclosure;

[0021] Figure 3 is a flow chart of preparing a light-emitting device provided by an embodiment of the present disclosure;

[0022] Figure 4 is a diagram of a preparation state of a light-emitting device provided by an embodiment of the present disclosure;

[0023] Figure 5 is a diagram of a preparation state of a light-emitting device provided by an embodiment of the present disclosure;

[0024] Figure 6 is a diagram of a preparation state of a light-emitting device provided by an embodiment of the present disclosure;

[0025] Figure 7 is a diagram of a preparation state of a light-emitting device provided by an embodiment of the present disclosure;

[0026] Figure 8 is a diagram of a preparation state of a light-emitting device provided by an embodiment of the present disclosure;

[0027] Fig. 9 is a diagram of a preparation state of a light-emitting device provided by an embodiment of the present disclosure;

[0028] Fig.10 It is a test current and voltage characteristic curve diagram of a light emitting device provided in an embodiment of the present disclosure.

[0029] The descriptions of the marks in the figure are as follows:

[0030] 10. substrate; 11. GaAs wafer;

[0031] 20. epitaxial layer; 21. first semiconductor layer; 22. multi-quantum well layer; 23. second semiconductor layer; 24. groove; 25. isolation groove;

[0032] 30. electrode; 31. first metal layer; 32. second metal layer; 33. protective layer;

[0033] 50. Passivation layer;

[0034] 60. Solder pad;

[0035] 70. Bonding layer. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0037] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] Figure 1 Schematic diagram of a light emitting device provided by an embodiment of the present disclosure. Figure 1 As shown, the light emitting device includes an epitaxial layer 20 and an electrode 30 , wherein the electrode 30 is located on the surface of the epitaxial layer 20 .

[0039] Figure 2Schematic diagram of the structure of an electrode 30 provided in an embodiment of the present disclosure. Figure 2 As shown, the electrode 30 includes at least two first metal layers 31 and at least two second metal layers 32 which are alternately stacked.

[0040] The first metal layer 31 includes an Au layer, and the second metal layer 32 includes an AuGe layer.

[0041] The electrode 30 of the light-emitting device provided in the embodiment of the present disclosure includes a first metal layer 31 and a second metal layer 32 alternately stacked. Among them, the first metal layer 31 includes an Au layer, and the second metal layer 32 includes an AuGe layer. Since AuGe has a low melting point and the annealing temperature is high, the AuGe layer is prone to morphological changes. After introducing a stacked Au layer with better high temperature resistance on the AuGe layer, the stack formed by the first metal layer 31 and AuGe can be more resistant to high temperatures. Therefore, at least two first metal layers 31 and at least two second metal layers 32 alternately stacked can form an electrode 30 that is more resistant to high temperatures. In this way, when the electrode 30 is annealed, the electrode 30 is not prone to irregular morphological changes even at a higher ambient temperature, thereby preventing the subsequent insulating layer from having a leakage channel of needle-like voids, thereby improving the reliability of the light-emitting device.

[0042] In the first implementation of the present disclosure, the first metal layer 31 includes an Au layer. Au has good high temperature resistance, so the stacked layer formed by the Au layer and the AuGe layer is more resistant to high temperatures.

[0043] Furthermore, Au has good electrical conductivity, so the stack formed by the Au layer and the AuGe layer further reduces the resistance of the electrode 30, which is beneficial to current transmission.

[0044] In a second implementation of the present disclosure, the first metal layer 31 includes a Ni layer. Ni has good high temperature resistance, so that the stack formed by the Ni layer and the AuGe layer does not change in morphology at a temperature of 500° C., thereby improving the high temperature resistance of the electrode 30 .

[0045] Compared with the Au layer, the Ni layer has a larger resistance, and thus the resistance of the electrode 30 is larger. The current transmission efficiency of this electrode 30 is lower than that of the electrode 30 in the first implementation.

[0046] In the third implementation of the present disclosure, the first metal layer 31 includes a Pt layer. Pt has good high temperature resistance, so that the stack formed by the Pt layer and the AuGe layer does not change in morphology at a higher temperature, thereby improving the high temperature resistance of the electrode 30.

[0047] Compared with the Au layer, the Pt layer has a higher high temperature resistance than the electrode 30 in the first implementation. In addition, the Pt layer has a higher resistance, so the resistance of the electrode 30 is higher, and the current transmission efficiency of this electrode 30 is lower than that of the electrode 30 in the first implementation.

[0048] Exemplarily, the electrode 30 may include 3 to 5 first metal layers 31 and second metal layers 32 that are alternately stacked.

[0049] Optionally, the thickness of the first metal layer 31 is 50 angstroms to 150 angstroms.

[0050] By controlling the thickness of the first metal layer 31 to be within the above range, it is possible to avoid the first metal layer 31 being too thick, thereby preventing the manufacturing cost of the electrode 30 from increasing.

[0051] As an example, in the embodiment of the present disclosure, the thickness of the first metal layer 31 is 100 angstroms.

[0052] Optionally, the thickness of the second metal layer 32 is 250 angstroms to 350 angstroms.

[0053] Controlling the thickness of the second metal layer 32 within the above range can prevent the AuGe layer from being too thin, that is, allowing the AuGe layer to fully contact the epitaxial layer 20, so as to obtain more ideal ohmic contact characteristics, improve the current expansion efficiency of the electrode 30, and make it easier for the current to diffuse to various areas of the epitaxial layer 20, thereby reducing the local voltage on the epitaxial layer 20.

[0054] As an example, in the embodiment of the present disclosure, the thickness of the second metal layer 32 is 300 angstroms.

[0055] Alternatively, if Figure 2 As shown, the electrode 30 further includes a protection layer 33 , and the protection layer 33 is located on a surface of the second metal layer 32 farthest from the epitaxial layer 20 and away from the epitaxial layer 20 .

[0056] By covering a protective layer 33 on the alternately stacked first metal layer 31 and the second metal layer 32 , the stacked layers can be protected.

[0057] Optionally, the protection layer 33 includes at least one of an Au layer, a Ni layer, and a Pt layer.

[0058] Exemplarily, the protection layer 33 may be an Au layer, which has good electrical conductivity and can enable other conductive layers to form a better ohmic contact effect with the electrode 30 .

[0059] Optionally, the protective layer 33 has a thickness of 400 angstroms to 600 angstroms.

[0060] By setting the protective layer 33 within the above range, the thickness of the protective layer 33 is ensured to be large enough, so that the protective layer 33 can fully protect the stacked layer formed by the first metal layer 31 and the second metal layer 32 .

[0061] As an example, in the embodiment of the present disclosure, the thickness of the protection layer 33 is 500 angstroms.

[0062] Alternatively, if Figure 1 As shown, the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 which are stacked in sequence.

[0063] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0064] As an example, the first semiconductor layer 21 is a p-type layer, and the second semiconductor layer 23 is an n-type layer.

[0065] Optionally, the first semiconductor layer 21 includes an indium-doped p-type GaP layer. The p-type GaP layer may have a thickness of 0.5 μm to 3 μm.

[0066] Optionally, the multi-quantum well layer 22 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately, wherein the Al content in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer is different. The multi-quantum well layer 22 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers stacked alternately.

[0067] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0068] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0069] Optionally, the second semiconductor layer 23 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0070] Alternatively, if Figure 1 As shown, the surface of the second semiconductor layer 23 has a groove 24 exposing the first semiconductor layer 21 .

[0071] like Figure 1 As shown, the electrode 30 may include two parts, one part of the electrode 30 is located in the groove 24 and electrically connected to the first semiconductor layer 21 , and the other part of the electrode 30 is located on the surface of the second semiconductor layer 23 and electrically connected to the second semiconductor layer 23 .

[0072] Alternatively, if Figure 1 As shown, the light emitting device further includes a substrate 10 , an epitaxial layer 20 is stacked on the substrate 10 , and a bonding layer 70 is disposed between the substrate 10 and the epitaxial layer 20 .

[0073] Exemplarily, the bonding layer 70 includes a silicon oxide layer. Using silicon oxide as the bonding layer 70 can effectively adhere the substrate 10 and the epitaxial layer 20, and during the preparation process, the epitaxial layer 20 can be more reliably fixed on the substrate 10.

[0074] By way of example, the bonding layer 70 is benzocyclobutene glue, which can well bond the substrate 10 and the epitaxial layer 20 together.

[0075] Illustratively, the thickness of the bonding layer 70 is 3000 angstroms to 5000 angstroms. As an example, the thickness of the bonding layer 70 is 3500 angstroms.

[0076] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting device has good light-emitting effect and stability.

[0077] Alternatively, if Figure 1 As shown, the light emitting device further includes a passivation layer 50 . The passivation layer 50 is located in the groove 24 and on the surface of the second semiconductor layer 23 away from the substrate 10 , and the passivation layer 50 covers the electrode 30 .

[0078] For example, the passivation layer 50 may be a SiO2 layer, a SiN x At least one of a layer, an Al2O3 layer and a Ti3O5 layer.

[0079] For example, the passivation layer 50 may be a SiO 2 layer, and the passivation layer 50 may have a thickness of 3.5 μm to 4.5 μm.

[0080] Exemplarily, the passivation layer 50 may include a plurality of first material layers and a plurality of second material layers alternately stacked, wherein the first material layers and the second material layers have different refractive indices, so that a distributed Bragg reflector (DBR) layer can be formed by alternately stacking material layers with different refractive indices.

[0081] By providing the DBR layer, the light emitted from the epitaxial layer 20 can be reflected, so that more light can be emitted from the light emitting surface of the light emitting device, thereby improving the light emitting intensity of the light emitting device.

[0082] As an example, the passivation layer 50 may include a plurality of Ti3O5 layers and a plurality of SiO2 layers stacked alternately, wherein the thickness of the passivation layer 50 is 0.5 μm to 2 μm, and the effective reflection band of the passivation layer 50 is 500 nm to 700 nm.

[0083] Alternatively, if Figure 1 As shown, a through hole exposing the electrode 30 is also provided on the passivation layer 50. At least two pads 60 are provided on the surface of the passivation layer 50 away from the epitaxial layer 20, one portion of the pad 60 is connected to the electrode 30 on the second semiconductor layer 23 through the through hole, and the other portion of the pad 60 is connected to the electrode 30 located in the groove 24 through the through hole.

[0084] Optionally, the pad 60 is a rectangular block to increase the area and facilitate conduction. In addition, on the surface of the passivation layer 50, the two parts of the pads 60 are distributed at intervals.

[0085] Optionally, a protective layer 33 is further provided on the surface of the passivation layer 50 , and the protective layer 33 extends from the surface of the passivation layer 50 to the substrate 10 , and the protective layer 33 has a through hole exposing the pad 60 for electrical connection.

[0086] For example, in the embodiment of the present disclosure, the protective layer 33 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0087] Optionally, the light emitting device may further include a transparent conductive layer, which is located on the surface of the second semiconductor layer 23 and between the second semiconductor layer 23 and the electrode 30 .

[0088] For example, the transparent conductive layer may be an indium tin oxide (ITO) layer, which has good transmittance and low resistivity.

[0089] For example, the transparent conductive layer may be an indium zinc oxide (IZO) layer, which has good transmittance and low resistivity.

[0090] Among them, using an ITO layer or an IZO layer as a transparent conductive layer can allow more light to be transmitted from the transparent conductive layer, thereby ensuring the light output effect; at the same time, due to the low resistivity, it is easier for carriers to be conducted to the alloy layer more efficiently, thereby improving the injection efficiency.

[0091] Figure 3 is a flow chart of manufacturing a light emitting device provided by an embodiment of the present disclosure. Figure 3 As shown, the preparation method comprises:

[0092] Step S11: forming an epitaxial layer.

[0093] The epitaxial layer 20 includes a first semiconductor layer 21 , a multi-quantum well layer 22 and a second semiconductor layer 23 which are stacked in sequence.

[0094] Step S12 : forming an electrode 30 on the surface of the epitaxial layer 20 .

[0095] The electrode 30 includes at least two first metal layers 31 and at least two second metal layers 32 which are alternately stacked. The first metal layer 31 includes an Au layer, and the second metal layer 32 includes an AuGe layer.

[0096] The electrode 30 of the light-emitting device prepared in the embodiment of the present disclosure includes a first metal layer 31 and a second metal layer 32 that are alternately stacked. Among them, the first metal layer 31 includes an Au layer, and the second metal layer 32 includes an AuGe layer. Since AuGe has a low melting point and the annealing temperature is high, the AuGe layer is prone to morphological changes. After introducing a stacked Au layer with better high temperature resistance on the AuGe layer, the stack formed by the first metal layer 31 and AuGe can be more resistant to high temperatures. Therefore, at least two first metal layers 31 and at least two second metal layers 32 that are alternately stacked can form an electrode 30 that is more resistant to high temperatures. In this way, when the electrode 30 is annealed, the electrode 30 is not prone to irregular morphological changes even at a higher ambient temperature, thereby preventing the subsequent insulating layer from having leakage channels of needle-like voids, thereby improving the reliability of the light-emitting device.

[0097] Step S11 of preparing the epitaxial layer 20 may include the following steps:

[0098] First, a GaAs wafer 11 is provided.

[0099] Then, if Figure 4 As shown, an epitaxial layer 20 is grown on a GaAs wafer 11 , and the epitaxial layer 20 includes a second semiconductor layer 23 , a multi-quantum well layer 22 , and a first semiconductor layer 21 which are stacked in sequence.

[0100] Exemplarily, the first semiconductor layer 21 is an indium-doped p-type GaP layer, and the thickness of the p-type GaP layer may be 0.5 μm to 3 μm.

[0101] For example, the second semiconductor layer 23 may be an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0102] Optionally, the multi-quantum well layer 22 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately, wherein the Al content in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer is different. The multi-quantum well layer 22 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers stacked alternately.

[0103] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0104] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0105] Here, an etching stop layer may be grown before growing the second semiconductor layer 23 , and an AlInP carrier confinement layer may be grown before growing the multi-quantum well layer 22 .

[0106] A GaP window layer may be further grown after the first semiconductor layer 21 is grown, wherein the thickness of the GaP window layer is 10000 angstroms to 20000 angstroms.

[0107] Exemplarily, the GaP window layer has a thickness of 11,000 angstroms.

[0108] Next, the substrate 10 is bonded to the surface of the first semiconductor layer 21 and the GaAs wafer 11 is removed.

[0109] The substrate 10 may be a sapphire substrate 10 .

[0110] Specifically, the method may include: first, treating the surface of the p-type GaP layer with an iodic acid roughening solution.

[0111] The roughening process is as follows: the flat edge of the epitaxial film is immersed in the iodic acid roughening solution for 40 seconds, and then shaken and rinsed in a water tank for at least 6 minutes, and then dried. This is repeated three times and the flat edge needs to be rotated 90° before each roughening.

[0112] Then, if Figure 5 As shown, benzocyclobutene glue is coated on the roughened surface of the p-type GaP layer. The benzocyclobutene glue can well bond the substrate 10 and the epitaxial layer 20 together to form a bonding layer 70, and remove the GaAs sheet 11.

[0113] Illustratively, the bonding layer 70 has a thickness of 3000 angstroms to 5000 angstroms.

[0114] Then, a transparent conductive layer is formed on the surface of the second semiconductor layer 23 .

[0115] Exemplarily, the thickness of the transparent conductive layer is also 100 angstroms.

[0116] Then, if Figure 6 As shown, photolithography and development are performed on the second semiconductor layer 23 , and a groove 24 exposing the first semiconductor layer 21 is opened on the second semiconductor layer 23 using a dry etching technique.

[0117] Exemplarily, the slope angle of the groove 24 is 70° to 85°. For example, the slope angle of the groove 24 is 75°.

[0118] By setting the slope angle of the groove 24 within the above angle range, the side wall of the groove 24 can be ensured to be smoother, making it less likely for cracks to appear in the film layer formed subsequently.

[0119] Then, if Figure 7 As shown, after photolithography and development are performed on the surface of the first semiconductor layer 21, the isolation groove 25 is prepared by using dry etching technology.

[0120] like Figure 7 As shown, the isolation trench 25 surrounds the epitaxial layer 20 to physically isolate different light-emitting devices on the sapphire.

[0121] For example, the slope angle of the isolation groove 25 is 85° to 90°. The isolation groove 25 is provided so that each light emitting device can be selectively transferred independently during subsequent laser lift-off.

[0122] The electrodes prepared in step S12 include a p-type electrode and an n-type electrode. The p-type electrode is located in the groove 24 and electrically connected to the first semiconductor layer 21 , and the n-type electrode is located on the second semiconductor layer 23 and electrically connected to the second semiconductor layer 23 .

[0123] Optionally, preparing the p-type layer may include: preparing a p-type ohmic contact electrode on the surface of the groove 24 .

[0124] After photolithography and development are performed on the p-type layer, the p-type ohmic contact electrode is prepared by using electron beam metal vacuum coating technology.

[0125] Exemplarily, the preparation materials of the p-type ohmic contact electrode include Au, AuBe, Ti, Pt and Ni.

[0126] In the embodiment of the present disclosure, after the p-type ohmic contact electrode is stripped and debonded, an alloy annealing treatment is required to obtain ideal ohmic contact characteristics.

[0127] Exemplarily, the annealing conditions of the rapid alloying furnace are: temperature of 350° C. to 450° C., holding temperature for 100 s to 300 s, and nitrogen introduction rate of 10 L / min to 15 L / min.

[0128] Optionally, preparing the n-type layer may include the following steps:

[0129] First, at least two first metal layers 31 and at least two second metal layers 32 are formed on the surface of the epitaxial layer 20 .

[0130] When preparing the first metal layer 31 , the coating rate of the first metal layer 31 is controlled to be less than or equal to 2 angstroms / second, and the first metal layer 31 with a thickness of 50 angstroms to 150 angstroms is prepared.

[0131] Exemplarily, when preparing the first metal layer 31 , the plating rate of the first metal is controlled to be 1 angstrom / second, and the first metal layer 31 with a thickness of 100 angstroms is prepared.

[0132] Exemplarily, the first metal layer 31 includes an Au layer.

[0133] When preparing the second metal layer 32 , the coating rate of the second metal layer 32 is controlled to be less than or equal to 2 angstroms / second, and the second metal layer 32 with a thickness of 250 angstroms to 350 angstroms is prepared.

[0134] Exemplarily, when preparing the second metal layer 32 , the plating rate of the second metal is controlled to be 1 angstrom / second, and the second metal layer 32 with a thickness of 300 angstroms is prepared.

[0135] Exemplarily, the second metal layer 32 includes an AuGe layer.

[0136] In the disclosed embodiment, the coating rates of the first metal layer 31 and the second metal layer 32 are controlled at a relatively low speed. The lower the coating rate, the better the density of the metal layer. The better the density, the stronger the high temperature resistance of the obtained electrode 30.

[0137] Then, a protection layer 33 is formed on a surface of the second metal layer 32 which is farthest from the epitaxial layer 20 and which is farthest from the epitaxial layer 20 .

[0138] The protective layer 33 includes at least one of an Au layer, a Ni layer and a Pt layer.

[0139] When preparing the protective layer 33 , the coating rate of the protective layer 33 is controlled to be less than or equal to 4 angstroms / second, and the protective layer 33 having a thickness of 400 angstroms to 600 angstroms is prepared.

[0140] Exemplarily, when preparing the protective layer 33 , the coating speed of the protective layer 33 is controlled to be 3 angstroms / second, and the protective layer 33 with a thickness of 500 angstroms is prepared.

[0141] Exemplarily, the protection layer 33 includes an Au layer.

[0142] Controlling the coating rate of the protective layer 33 at a relatively low speed is beneficial to improving the compactness of the protective layer 33 and enhancing the high temperature resistance of the electrode 30 .

[0143] Furthermore, the coating rate of the protective layer 33 is higher than the coating rates of the first metal layer 31 and the second metal layer 32 , which is beneficial to improving the coating speed of the protective layer 33 and improving the preparation efficiency of the electrode 30 .

[0144] After step S12, the following steps are also included:

[0145] In the first step, the annealing temperature is controlled to be 380° C. to 450° C. for 5 seconds to 150 seconds, and the nitrogen introduction rate is controlled to be 2 L / min to 10 L / min, so as to anneal the electrode 30 .

[0146] Exemplarily, during annealing, the annealing temperature is controlled to be 400° C. and lasts for 50 seconds, while the nitrogen injection rate is controlled to be 6 L / min.

[0147] Under the above annealing conditions, Ge in the AuGe layer can be rapidly diffused to the second semiconductor layer 23 , so that the electrode 30 and the second semiconductor layer 23 can obtain better ohmic contact characteristics.

[0148] At the same time, by controlling the annealing temperature within the above range, it is possible to avoid the annealing temperature being too low so that Ge cannot diffuse quickly into the second semiconductor layer 23 ; at the same time, it is also possible to avoid the annealing temperature being too high so that the metal layer undergoes morphological changes.

[0149] The second step is, Figure 8 As shown, a passivation layer 50 is formed in the groove 24 and on the second semiconductor layer 23 , so that the passivation layer 50 covers the electrode 30 .

[0150] Specifically, it may include: using plasma enhanced chemical vapor deposition (PECVD) technology or atomic layer deposition (ALD) technology to prepare SiO2, SiN x , Al2O3 and Ti3O5 material films.

[0151] Exemplarily, the passivation layer 50 may include a plurality of first material layers and a plurality of second material layers alternately stacked, wherein the first material layers and the second material layers have different refractive indices, so that a distributed Bragg reflection layer can be formed by alternately stacking material layers with different refractive indices.

[0152] As an example, the passivation layer 50 may include a plurality of Ti3O5 layers and a plurality of SiO2 layers stacked alternately, wherein the thickness of the passivation layer 50 is 0.5 μm to 2 μm, and the effective reflection band of the passivation layer 50 is 500 nm to 700 nm.

[0153] The third step is Fig. 9 As shown, after photolithography and development are performed on the passivation layer 50, patterning is performed on the electrode 30 and the isolation groove 25. The passivation layer 50 is removed from the patterned area using ICP dry etching technology to form a through hole connecting the electrode 30.

[0154] It should be noted that each through hole can be prepared by photolithography patterning and etching separately or by photolithography and etching simultaneously.

[0155] The fourth step is Figure 1 As shown, at least two pads 60 are prepared on the surface of the passivation layer 50 by using electron beam metal vacuum coating technology.

[0156] Fig.10 It is a test current and voltage characteristic curve diagram of a light emitting device provided in an embodiment of the present disclosure. Fig.10 In the figure, the blue curve is the characteristic curve V1 of the light emitting device in the related art, and the orange curve is the characteristic curve V2 of the light emitting device provided by the embodiment of the present disclosure.

[0157] like Fig.10 As shown, as the test current gradually increases, that is, under high current conditions, the operating voltage of the light-emitting device provided by the embodiment of the present disclosure is always lower than the operating voltage of the light-emitting device of the related art.

[0158] Table 1 below is a parameter table of the test current and voltage characteristic curve.

[0159] Table 1

[0160]

[0161]

[0162] According to Table 1, under the condition of high current, the operating voltage of the light emitting device provided by the embodiment of the present disclosure is always lower than the operating voltage of the light emitting device of the related art. Under the condition of high current driving the light emitting device, the operating voltage of the light emitting device provided by the embodiment of the present disclosure will not increase significantly, but can remain unchanged or increase slightly.

[0163] The disclosed embodiment adopts a stacked structure design of Au layer and AuGe layer, and matches the appropriate metal coating rate of each layer and RTA temperature curve, so that an ideal ohmic contact feature can be formed between the electrode and the epitaxial layer. The electrode obtained under the above preparation conditions has almost no morphological changes after annealing the alloy under metallographic microscope observation or FIB analysis, which ensures the smooth progress of subsequent process from the perspective of visual perception and actual process reliability, and ensures that the process technology route can be smoothly mass-produced.

[0164] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting device, characterized in that: The light-emitting device comprises an epitaxial layer (20) and an electrode (30), wherein the electrode (30) is located on the surface of the epitaxial layer (20), and the electrode (30) comprises at least two first metal layers (31) and at least two second metal layers (32) which are alternately stacked, wherein the first metal layer (31) comprises an Au layer, and the second metal layer (32) comprises an AuGe layer.

2. The light emitting device according to claim 1, characterized in that: The thickness of the first metal layer (31) is 50 angstroms to 150 angstroms, and the thickness of the second metal layer (32) is 250 angstroms to 350 angstroms.

3. The light emitting device according to claim 1 or 2, characterized in that: The electrode (30) further comprises a protective layer (33), wherein the protective layer (33) is located on a surface of the second metal layer (32) which is farthest from the epitaxial layer (20) and is farthest from the epitaxial layer (20).

4. The light emitting device according to claim 3, characterized in that: The thickness of the protective layer (33) is 400 angstroms to 600 angstroms.

5. The light emitting device according to claim 3, characterized in that: The protective layer (33) includes at least one of an Au layer, a Ni layer and a Pt layer.

6. A method for preparing a light emitting device, characterized in that: The preparation method comprises: forming an epitaxial layer; An electrode is formed on the surface of the epitaxial layer. The electrode includes at least two first metal layers and at least two second metal layers which are alternately stacked. The first metal layer includes an Au layer, and the second metal layer includes an AuGe layer.

7. The preparation method according to claim 6, characterized in that: The preparation method further comprises: When preparing the first metal layer, controlling the coating rate of the first metal layer to be less than or equal to 2 angstroms / second, and preparing the first metal layer with a thickness of 50 angstroms to 150 angstroms; When preparing the second metal layer, the coating rate of the second metal layer is controlled to be less than or equal to 2 angstroms / second, and the second metal layer with a thickness of 250 angstroms to 350 angstroms is prepared.

8. The preparation method according to claim 6, characterized in that: Forming an electrode on the surface of the epitaxial layer comprises: forming at least two first metal layers and at least two second metal layers on the surface of the epitaxial layer; A protective layer is formed on a surface of the second metal layer farthest from the epitaxial layer and away from the epitaxial layer, the protective layer comprising at least one of an Au layer, a Ni layer, and a Pt layer.

9. The preparation method according to claim 8, characterized in that: The preparation method further includes: when preparing the protective layer, controlling the coating rate of the protective layer to be less than or equal to 4 angstroms / second, and preparing the protective layer with a thickness of 400 angstroms to 600 angstroms.

10. The preparation method according to any one of claims 6 to 9, characterized in that: After forming an electrode on the surface of the epitaxial layer, the method further comprises: The electrode is annealed by controlling the annealing temperature to be 380° C. to 450° C. for 5 seconds to 150 seconds and controlling the nitrogen introduction rate to be 2 L / min to 10 L / min.

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