Display device

Abstract

A display device includes: a display panel, including a plurality of pads, wherein the plurality of pads include a plurality of first pads, a plurality of second pads and a plurality of third pads, wherein a first pad column, a second pad column and a third pad column each include a first pad, a second pad and a third pad, wherein only the first pad in the first pad column, the second pad in the second pad column and the third pad in the third pad column are connected to a connecting line, wherein, in the first pad column, the second pad and the third pad that are not connected to the connecting line are in a floating state.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0131935, filed on October 4, 2023, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more embodiments relate to a display device, and more particularly, to a display device having improved reliability and quality. Background Art

[0003] The display device visually displays data. The display device may provide an image by using a light emitting diode. The use of the display device has been diversified, and various designs for improving the quality of the display device have been tried. Summary of the invention

[0004] One or more embodiments include a display device.

[0005] Additional embodiments will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of embodiments of the invention.

[0006] According to one or more embodiments, a display device includes: a display panel including a plurality of pads; and a driving chip including a plurality of buffers corresponding to the plurality of pads, wherein the plurality of pads include: a plurality of first pads arranged in a first direction; a plurality of second pads arranged in the first direction and spaced apart from the first pads in a second direction intersecting the first direction; and a plurality of third pads arranged in the first direction and spaced apart from the second pads in the second direction, wherein a first pad column, a second pad column, and a third pad column each include a first pad, a second pad, and a third pad arranged in the second direction, wherein the first pad column, the second pad column, and the third pad column are spaced apart from each other in the first direction, wherein only the first pad in the first pad column, the second pad in the second pad column, and the third pad in the third pad column are connected to a connecting line, and wherein, in the first pad column, the second pad and the third pad that are not connected to the connecting line are in a floating state.

[0007] In an embodiment, a signal may not be applied to the second and third pads in the first pad column that are not connected to the connection line.

[0008] In an embodiment, when a signal is applied to the first pad connected to the connection line, the signal may be applied to the sub-pixel circuit through the connection line.

[0009] In an embodiment, in the second pad column, the first pad and the third pad that are not connected to the connection line may be in a floating state.

[0010] In an embodiment, in the third pad column, the first pad and the second pad that are not connected to the connection line may be in a floating state.

[0011] In an embodiment, the first pad group may include a first pad column, a second pad column, and a third pad column, wherein the first pad group may be arranged in a first direction.

[0012] In an embodiment, the first pads connected to the connection wires may be spaced apart from each other, wherein two of the first pads not connected to the connection wires are disposed between the first pads connected to the connection wires.

[0013] In an embodiment, the second pads connected to the connection wires may be spaced apart from each other, wherein two of the second pads not connected to the connection wires are disposed between the second pads connected to the connection wires.

[0014] In an embodiment, the third pads connected to the connection lines may be spaced apart from each other, wherein two of the third pads not connected to the connection lines are disposed between the third pads connected to the connection lines.

[0015] According to one or more embodiments, a display device includes: a display panel including a plurality of pads; and a driving chip including a plurality of buffers corresponding to the plurality of pads, wherein the plurality of pads include: a plurality of first pads arranged in a first direction; a plurality of second pads arranged in the first direction and spaced apart from the first pads in a second direction intersecting the first direction; and a plurality of third pads arranged in the first direction and spaced apart from the second pads in the second direction, wherein a first pad column, a second pad column, a third pad column, and a fourth pad column each include a first pad, a second pad, and a third pad arranged in the second direction, wherein the first pad column, the second pad column, the third pad column, and the fourth pad column are spaced apart from each other in the first direction, wherein only the first pad in the first pad column, the second pad in the second pad column, the third pad in the third pad column, and the second pad in the fourth pad column are connected to a connection line, and wherein, in the first pad column, the second pad and the third pad that are not connected to the connection line are in a floating state.

[0016] In an embodiment, in the second pad column, the first pad and the third pad that are not connected to the connection line may be in a floating state.

[0017] In an embodiment, in the third pad column, the first pad and the second pad that are not connected to the connection line may be in a floating state.

[0018] In an embodiment, in the fourth pad column, the first pad and the third pad that are not connected to the connection line may be in a floating state.

[0019] In an embodiment, the second pad group may include a first pad column, a second pad column, a third pad column, and a fourth pad column, wherein the second pad group may be arranged in the first direction.

[0020] In an embodiment, the first pads connected to the connection lines may be spaced apart from each other, wherein three of the first pads that are not connected to the connection lines are disposed between the first pads connected to the connection lines.

[0021] In an embodiment, the second pads connected to the connection wires may be spaced apart from each other, wherein one of the second pads not connected to the connection wire is disposed between the second pads connected to the connection wires.

[0022] In an embodiment, the third pads connected to the connection lines may be spaced apart from each other, wherein three of the third pads that are not connected to the connection lines are disposed between the third pads connected to the connection lines.

[0023] According to one or more embodiments, a display device includes: a display panel including a plurality of pads; and a driving chip including a plurality of buffers corresponding to the plurality of pads, wherein the plurality of pads include: a plurality of first pads arranged in a first direction; and a plurality of second pads arranged in the first direction and spaced apart from the plurality of first pads in a second direction intersecting the first direction, wherein a first pad column and a second pad column each include a first pad and a second pad arranged in the second direction, wherein the first pad column and the second pad column are spaced apart from each other in the first direction, wherein a first pad in the first pad column and a second pad in the second pad column are connected to a connecting line, and wherein, in the first pad column, a second pad that is not connected to the connecting line is in a floating state.

[0024] In an embodiment, in the second pad column, first pads not connected to the connection line may be in a floating state.

[0025] In an embodiment, the third pad group may include a first pad column and a second pad column, wherein the third pad group may be arranged in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects, features and advantages of certain embodiments of the present invention will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0027] Figure 1A is a perspective view of an electronic device according to an embodiment;

[0028] Figure 1B is an exploded perspective view of an electronic device according to an embodiment;

[0029] Figure 1C is a cross-sectional view of a display device connected to a circuit board according to an embodiment;

[0030] Figure 2 is a cross-sectional view of a display device according to an embodiment;

[0031] Figure 3 is a plan view of a display panel according to an embodiment;

[0032] Figure 4 is a schematic equivalent circuit diagram of a sub-pixel circuit included in a display device according to an embodiment;

[0033] Figure 5 is a schematic cross-sectional view of a display panel according to an embodiment;

[0034] Figure 6 is a schematic plan view of a plurality of pads arranged in a chip region of a display panel according to an embodiment;

[0035] Figure 7 According to the embodiment Figure 6 a schematic cross-sectional view of at least some of the plurality of pads;

[0036] Figure 8 is a schematic plan view of a plurality of pads arranged in a chip region of a display panel according to an embodiment;

[0037] Fig. 9 is a schematic plan view of a plurality of pads arranged in a chip region of a display panel according to an embodiment; and

[0038] Fig.10 is a schematic plan view of a plurality of pads arranged in a chip region of a display panel according to an embodiment. DETAILED DESCRIPTION

[0039] Now will refer to embodiment in detail, the example of embodiment is illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements from time to time. In this respect, the current embodiment can have different forms, and should not be construed as being limited to the description set forth herein. Accordingly, the embodiments are described below only by reference to the accompanying drawings to explain the various aspects of the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the items listed in the relevant. Throughout the disclosure, the statement "at least one of a, b and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or its variant.

[0040] Since the present description allows for various changes and numerous embodiments, certain embodiments will be shown in the drawings and described in the written description. The effects and features of one or more embodiments and their implementation methods will become apparent through the following detailed description of one or more embodiments in conjunction with the drawings. However, the embodiments may have different forms and should not be construed as being limited to the description set forth herein.

[0041] One or more embodiments will be described in more detail below with reference to the accompanying drawings. Those elements that are identical or corresponding to each other are given the same reference numerals regardless of the figure numbers, and redundant descriptions thereof are omitted.

[0042] It will be understood that when an element is referred to as being in relation to another element (e.g., "on" another element), it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being in relation to another element (such as "directly on" another element), there are no intervening elements present.

[0043] It will be understood that although the terms "first", "second", "third", etc. may be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

[0044] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be limiting. As used herein, the singular forms "one" and "the (described)" are intended to include plural forms including "at least one", unless the context clearly indicates otherwise. "At least one" is not to be interpreted as being limited to "one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the items listed in the relevant list. It will be further understood that the term "comprising" and its variations and / or "including" and its variations when used in this specification indicate the presence of stated features, regions, wholes, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their combinations.

[0045] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that in addition to the orientation shown in the accompanying drawings, relative terms are also intended to cover different orientations of the device. For example, if the device in one of the drawings is flipped, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawings, the exemplary term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device in one of the drawings is flipped, the element described as being "below" or "below" the other elements will then be oriented "above" the other elements. Therefore, the exemplary terms "below" or "below" can cover both upper and lower orientations.

[0046] It will be understood that, as used herein, the terms “comprising,” “including,” and “having” specify the presence of stated features or elements, but do not preclude the addition of one or more other features or elements.

[0047] It will be further understood that when a layer, region or element is referred to as being "on" another layer, region or element, it can be directly or indirectly on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0048] For the convenience of explanation, the size of the elements in the drawings may be exaggerated or reduced. For example, since the size and thickness of the elements in the drawings are arbitrarily illustrated for the convenience of explanation, the following embodiments are not limited thereto.

[0049] When the embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially at the same time or in the reverse order of the described order.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0051] As used herein, the expression "A and / or B" refers to A, B, or A and B. In addition, the expression "at least one of A and B" refers to A, B, or A and B.

[0052] It will be further understood that when layers, regions or elements are referred to as being connected to each other, they may be directly connected to each other, or they may be indirectly connected to each other, with intervening layers, regions or elements therebetween. For example, when layers, regions or elements are referred to as being electrically connected to each other, they may be directly electrically connected to each other, or they may be indirectly electrically connected to each other, with intervening layers, regions or elements therebetween.

[0053] The x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broad sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0054] Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions shown herein, but rather include deviations in shapes resulting, for example, from manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the present disclosure.

[0055] Figure 1A is a perspective view of an electronic device ED according to the embodiment. Figure 1B is an exploded perspective view of an electronic device ED according to an embodiment. Figure 1C is a cross-sectional view of a display device DD connected to a circuit board CF according to an embodiment.

[0056] In this description, an electronic device ED of a mobile phone terminal is shown as an example. The electronic device ED described herein can be applied to large electronic devices such as televisions and monitors, and can also be applied to small and medium-sized electronic devices such as tablet personal computers, car navigation systems, game consoles, and smart watches.

[0057] In the examples and with reference to Figure 1A , the electronic device ED can display an image IM on the display surface ED-IS. An icon image is shown as an example of the image IM. The display surface ED-IS is oriented parallel to a plane defined by the first direction DR1 and the second direction DR2. The third direction DR3 indicates a normal direction of the display surface ED-IS (i.e., a thickness direction of the electronic device ED). The display surface ED-IS includes a display area ED-DA and a non-display area ED-NDA disposed adjacent to the display area ED-DA.

[0058] As used herein, the phrase "when viewed in a plane or in a plan view" may refer to when viewed in a third direction DR3. The third direction DR3 separates the front (or top) surface and the rear (or bottom) surface of each layer or unit described below. However, the combination of the first direction DR1 to the third direction DR3 may be changed to another combination.

[0059] In the examples and with reference to Figure 1B and Figure 1C , the electronic device ED may include a window WM, a display device DD, and a receiving member BC. Although not shown, the electronic device ED may further include an optical member disposed between the window WM and the display device DD. The optical member may include a polarizer.

[0060] In an embodiment, the window WM may be provided on the display device DD and may transmit an image provided from the display device DD to the outside. The window WM includes a transmission area TA and a non-transmission area NTA. The transmission area TA may overlap with the display area ED-DA and may have a shape corresponding to the display area ED-DA. The window WM may include a base layer and a functional layer provided on the base layer. The functional layer may include a protective layer and an anti-fingerprint layer. The base layer of the window WM may be formed of glass, sapphire, or plastic.

[0061] In an embodiment, the non-transmission area NTA may overlap the non-display area ED-NDA and may have a shape corresponding to the non-display area ED-NDA. The non-transmission area NTA may be an area having a relatively low transmittance compared to the transmittance of the transmission area TA. The non-transmission area NTA may be defined by a frame pattern arranged in a partial area of ​​the base layer of the window WM, and an area in which the frame pattern is not arranged may be defined as the transmission area TA. However, one or more embodiments are not limited thereto, and the non-transmission area NTA may be omitted.

[0062] According to an embodiment, the display device DD may include a display panel DP and an input sensor ISU. According to an embodiment, the display panel DP may be one of a liquid crystal display panel, an electrophoretic display panel, a microelectromechanical system (MEMS) display panel, an electrowetting display panel, an organic light emitting display panel, an inorganic light emitting display panel, and a quantum dot light emitting display panel, and is not particularly limited. Hereinafter, it is assumed that the display panel DP is an organic light emitting display panel.

[0063] In an embodiment, the input sensor ISU may include one of a capacitive sensor, an optical sensor, an ultrasonic sensor, and an inductive sensor. The input sensor ISU may be formed on the display panel DP through a continuous process, or may be separately manufactured and then attached to the upper side of the display panel DP through an adhesive layer, and is not limited to any one embodiment.

[0064] In an embodiment, the display device DD may further include a driving chip DC connected to the circuit board CF. Although an embodiment in which the driving chip DC is mounted on the display panel DP is shown, the present invention is not limited thereto. The driving chip DC may generate a driving signal required for the operation of the display panel DP based on a control signal transmitted from the circuit board CF.

[0065] In an embodiment, a circuit board CF electrically coupled to the display panel DP may be bent and disposed on the rear surface of the display panel DP. The receiving member BC may receive the display device DD and may be coupled to the window WM. The circuit board CF may be disposed on the base substrate SUB (refer to Figure 2 ) and can be electrically connected to the circuit element layer DP-CL (reference Figure 2 ). Although not shown, the electronic device ED may further include a main board, and an electronic module, a camera module, and a power module mounted on the main board.

[0066] In an embodiment, the display panel DP may include a bending area BA and first and second non-bending areas NBA1 and NBA2 spaced apart from each other in a third direction DR3 , wherein the bending area BA is disposed between the first and second non-bending areas NBA1 and NBA2 .

[0067] In an embodiment, the bending area BA may be defined as an area where the display panel DP is bent along a virtual bending axis BX extending in the first direction DR1. The first non-bending area NBA1 may be defined as an area overlapping the transmissive area TA, and the second non-bending area NBA2 may be defined as an area connected to the circuit board CF.

[0068] In an embodiment, when the bending area BA is bent about the virtual bending axis BX, the circuit board CF and the driving chip DC may be bent in a direction toward the rear surface of the display panel DP and disposed on the rear surface of the display panel DP.

[0069] Although not shown, in an embodiment, an additional configuration may be arranged to compensate for a step between the circuit board CF and the rear surface of the display panel DP caused by the bending area BA.

[0070] According to an embodiment, in the second direction DR2, the width of the first non-bending area NBA1 may be greater than the width of the bending area BA and the width of the second non-bending area NBA2. However, the present invention is not limited thereto, and the width of the bending area BA in the second direction DR2 may decrease in a direction from the first non-bending area NBA1 to the second non-bending area NBA2, and is not limited to any one embodiment.

[0071] In the embodiment, as an example of the electronic device ED, a mobile phone terminal has been described above. However, in the embodiment, it is sufficient for the electronic device ED to include two or more electrically combined electronic components. The display panel DP and the driving chip DC mounted on the display panel DP may correspond to different electronic components, respectively, and these may constitute the electronic device ED alone, and the present invention is not limited thereto.

[0072] In an embodiment, for example, a display panel DP and a circuit board CF connected to the display panel DP may be sufficient to constitute the electronic device ED, and a main board and an electronic module mounted on the main board may be sufficient to constitute the electronic device ED. Hereinafter, the electronic device ED according to one or more embodiments will be described focusing on the coupling structure between the display panel DP and the driving chip DC mounted on the display panel DP.

[0073] Figure 2 is a cross-sectional view of a display device DD according to an embodiment. Figure 2 In the reference Figure 1C The bending area BA of the display panel DP is described as an area corresponding to the second non-bending area NBA2. Figure 3 is a plan view of a display panel DP according to an embodiment.

[0074] In the examples and with reference to Figure 2 The display panel DP includes a base substrate SUB, and a circuit element layer DP-CL, a display element layer DP-OLED, and a packaging layer TFL disposed on the base substrate SUB. The input sensor ISU may be disposed on the packaging layer TFL.

[0075] In an embodiment, the display panel DP includes a display area DP-DA and a non-display area DP-NDA. Figure 1A The display area ED-DA or Figure 1B The transmissive area TA shown in FIG. 1 corresponds to the transmissive area TA shown in FIG. 1 , and the non-display area DP-NDA of the display panel DP corresponds to the transmissive area TA shown in FIG. 1 . Figure 1A The non-display area ED-NDA shown in Figure 1B Corresponding to the non-transmitting area NTA shown in .

[0076] In an embodiment, the base substrate SUB may include at least one plastic film. The base substrate SUB is a flexible substrate, and may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0077] In an embodiment, the circuit element layer DP-CL includes at least one intermediate insulating layer and a circuit element. The intermediate insulating layer includes at least one intermediate inorganic layer and at least one intermediate organic layer. The circuit element includes a signal line and a pixel driving circuit.

[0078] In an embodiment, the display element layer DP-OLED includes a plurality of organic light emitting diodes. The display element layer DP-OLED may further include an organic layer such as a pixel defining layer. The encapsulation layer TFL encapsulates the display element layer DP-OLED. As an example, the encapsulation layer TFL may include a stacked structure of an inorganic layer / organic layer / inorganic layer. The encapsulation layer TFL protects the display element layer DP-OLED from moisture, oxygen, and foreign matter such as dust particles. However, the present invention is not limited thereto, and the encapsulation layer TFL may further include an additional insulating layer. For example, an optical insulating layer for controlling the refractive index may be further included.

[0079] In an embodiment, an encapsulation substrate may be provided instead of the encapsulation layer TFL. In this case, the encapsulation substrate may face the base substrate SUB and may be bonded to the base substrate SUB via a separate adhesive member. The circuit element layer DP-CL and the display element layer DP-OLED may be disposed between the encapsulation substrate and the base substrate SUB.

[0080] In an embodiment, the input sensor ISU may be directly disposed on the display panel DP. As used herein, the phrase "element A is directly disposed on element B" means that no adhesive layer is disposed between element A and element B. In an embodiment, the input sensor ISU may be manufactured with the display panel DP through a continuous process. However, the present invention is not limited thereto, and the input sensor ISU may be provided as a separate panel and bonded to the display panel DP through an adhesive layer. As another example, the input sensor ISU may be omitted.

[0081] In the examples and with reference to Figure 3 , the display panel DP may include a plurality of pixels PX, a gate driving circuit GDC, a plurality of signal lines SGL, and a plurality of pads DP-PD and a plurality of pads DP-CPD.

[0082] In an embodiment, the pixels PX are arranged in the display area DP-DA. Each of the pixels PX includes an organic light emitting diode and a pixel driving circuit connected to the organic light emitting diode. The gate driving circuit GDC and the signal line SGL may be included in Figure 2 The circuit element layer DP-CL is shown in FIG.

[0083] In an embodiment, the gate driving circuit GDC is configured to sequentially output gate signals to the plurality of gate lines GL. The gate driving circuit GDC may include a plurality of thin film transistors formed by the same process as the driving circuit of the pixel PX (e.g., a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process). The display panel DP may further include another driving circuit configured to provide a light emitting control signal to the pixel PX.

[0084] In an embodiment, the signal line SGL includes a gate line GL, a data line DL, a power line PL, and a control signal line CSL. Each of the gate lines GL is connected to a corresponding pixel PX in the pixels PX, and each of the data lines DL is connected to a corresponding pixel PX in the pixels PX. The power line PL is connected to the pixel PX. The control signal line CSL may be configured to provide a control signal to the gate drive circuit GDC.

[0085] In an embodiment, the signal line SGL overlaps the display area DP-DA and the non-display area DP-NDA. Each of the signal lines SGL may include a pad portion and a line portion. The line portion overlaps the display area DP-DA and the non-display area DP-NDA. The pad portion is connected to the end of the line portion. The pad portion may overlap the pad area described below.

[0086] In an embodiment, the display panel DP may include a display pad. The display pad may include a pad DP-PD arranged in the chip area DCA and a pad DP-CPD arranged in the first pad area PCA1. The pad DP-PD arranged in the chip area DCA and the pad DP-CPD arranged in the first pad area PCA1 may be arranged in the second non-bending area NBA2.

[0087] In an embodiment, a plurality of pads DP-PD may be arranged in the chip area DCA. Figure 1C ) can be mounted on the chip area DCA. A plurality of pads DP-PD are electrically connected to the driving chip DC to transmit the electrical signal received from the driving chip DC to the signal line SGL. Hereinafter, the arrangement of the plurality of pads DP-PD and the connection line CGL connected to the plurality of pads DP-PD in the following figures will be described in more detail.

[0088] In an embodiment, the pads DP-CPD may be arranged in the first pad area PCA1. The pads DP-CPD may be arranged in the first direction DR1. The pads DP-PD in the chip area DCA and the pads DP-CPD in the first pad area PCA1 may be connected to each other through a bridge signal line S-CL.

[0089] In an embodiment, the circuit board CF may include substrate pads CF-PD electrically connected to the display panel DP. The substrate pads CF-PD may be arranged in a second pad area PCA2 defined in the circuit board CF. The substrate pads CF-PD may be arranged in a first direction DR1.

[0090] In addition, in the embodiment, the pads DP-CPD in the first pad area PCA1 and the substrate pads CF-PD in the second pad area PCA2 may be arranged in a 1:1 correspondence relationship, and are not limited to any one embodiment.

[0091] In an embodiment, the second pad area PCA2 of the circuit board CF may be disposed on the first pad area PCA1. The pads DP-CPD in the first pad area PCA1 are electrically connected to the substrate pads CF-PD included in the circuit board CF to transmit the electrical signals received from the circuit board CF to the pads DP-PD in the chip area DCA. The circuit board CF may be rigid or flexible. For example, when the circuit board CF is flexible, a flexible printed circuit board may be provided as the circuit board CF.

[0092] In an embodiment, the circuit board CF may include a timing control circuit configured to control the operation of the display panel DP. The timing control circuit may be mounted in the circuit board CF in the form of an integrated chip. In addition, although not shown, the circuit board CF may include a timing control circuit configured to control the input sensor ISU (see Figure 2 ) input sensing circuit.

[0093] Figure 4 is a schematic equivalent circuit diagram of any one sub-pixel circuit PC included in a display device according to an embodiment.

[0094] In the examples and with reference to Figure 4 , the sub-pixel circuit PC may include a plurality of thin film transistors and at least one capacitor. In an embodiment, the sub-pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3 and a storage capacitor Cst.

[0095] In an embodiment, each of the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 may be an oxide semiconductor thin film transistor including a semiconductor layer composed of an oxide semiconductor or a silicon semiconductor thin film transistor including a semiconductor layer composed of polycrystalline silicon. Each thin film transistor may include a first electrode and a second electrode, and depending on the type of the thin film transistor, the first electrode may be one of a source electrode and a drain electrode and the second electrode may be the other of the source electrode and the drain electrode. In addition, each thin film transistor may include a gate electrode.

[0096] In an embodiment, the first thin film transistor T1 may be a driving thin film transistor. A first electrode of the first thin film transistor T1 may be connected to a driving voltage line VDL configured to supply a driving power supply voltage ELVDD, and a second electrode of the first thin film transistor T1 may be connected to a pixel electrode of the organic light emitting diode OLED. A gate electrode of the first thin film transistor T1 may be connected to a first node N1. The first thin film transistor T1 may be configured to control an amount of current flowing from the driving voltage line VDL through the organic light emitting diode OLED in response to a voltage of the first node N1.

[0097] In an embodiment, the second thin film transistor T2 may be a switching thin film transistor. A first electrode of the second thin film transistor T2 may be connected to the data line DL, and a second electrode of the second thin film transistor T2 may be connected to the first node N1. A gate electrode of the second thin film transistor T2 may be connected to the scan line SL. When a scan signal is supplied to the scan line SL, the second thin film transistor T2 may be turned on to electrically connect the data line DL and the first node N1 to each other.

[0098] In an embodiment, the third thin film transistor T3 may be an initialization thin film transistor and / or a sensing thin film transistor. A first electrode of the third thin film transistor T3 may be connected to the second node N2, and a second electrode of the third thin film transistor T3 may be connected to the initialization voltage line INL. A gate electrode of the third thin film transistor T3 may be connected to the scan line SL.

[0099] In an embodiment, when a scan signal is supplied to the scan line SL, the third thin film transistor T3 may be turned on to electrically connect the initialization voltage line INL and the second node N2 to each other. In some embodiments, the third thin film transistor T3 may be turned on according to a signal received through the scan line SL to transmit an initialization voltage from the initialization voltage line INL to the pixel electrode of the organic light emitting diode OLED and initialize the pixel electrode of the organic light emitting diode OLED.

[0100] In an embodiment, when a scan signal is supplied to the scan line SL, the third thin film transistor T3 may be turned on to sense characteristic information about the organic light emitting diode OLED. The third thin film transistor T3 may have both the above-mentioned function as an initialization thin film transistor and the above-mentioned function as a sensing thin film transistor, or may have either function. The initialization operation and the sensing operation of the third thin film transistor T3 may be performed separately or simultaneously. When the third thin film transistor T3 has the function as a sensing thin film transistor, the initialization voltage line INL may be referred to as a sensing line.

[0101] In an embodiment, the storage capacitor Cst may be connected between the first node N1 and the second node N2. For example, the first capacitor plate of the storage capacitor Cst may be connected to the gate electrode of the first thin film transistor T1, and the second capacitor plate of the storage capacitor Cst may be connected to the pixel electrode of the organic light emitting diode OLED.

[0102] In an embodiment, the counter electrode of the organic light emitting diode OLED may be connected to a common voltage line VSL configured to provide a common power voltage ELVSS.

[0103] In the embodiment, although Figure 4 The sub-pixel circuit PC including three thin film transistors and one storage capacitor is shown, but one or more embodiments are not limited thereto. In another embodiment, the number of thin film transistors or the number of storage capacitors may be variously modified according to the design of the sub-pixel circuit PC.

[0104] Figure 5 is a schematic cross-sectional view of a display panel DP according to an embodiment. More specifically, Figure 5 It is along Figure 3 The line Ι-Ι' is intercepted Figure 3 Schematic cross-sectional view of a display panel DP.

[0105] In the examples and with reference to Figure 5 The base substrate SUB may include a first base layer 100a, a first barrier layer 100b, a second base layer 100c, and a second barrier layer 100d. In an embodiment, the first base layer 100a, the first barrier layer 100b, the second base layer 100c, and the second barrier layer 100d may be sequentially stacked in a thickness direction of the base substrate SUB.

[0106] In an embodiment, at least one of the first substrate layer 100a and the second substrate layer 100c may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate.

[0107] In an embodiment, the first barrier layer 100b and the second barrier layer 100d are barrier layers for preventing external foreign matter from invading, and each may include a material such as silicon nitride (SiN x ), silicon oxide (SiO 2 ) or silicon oxynitride (SiO x N y ) of an inorganic material having a single layer structure or a multilayer structure.

[0108] In an embodiment, the buffer layer 111 may be disposed on the base substrate SUB. The buffer layer 111 may include silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) or silicon oxide (SiO 2 ) of an inorganic insulating material, and may have a single-layer structure or a multi-layer structure including the above-mentioned inorganic insulating material.

[0109] In an embodiment, the inorganic insulating layer IIL may be disposed on the buffer layer 111. The inorganic insulating layer IIL may include a first gate insulating layer 112, a second gate insulating layer 113, and an interlayer insulating layer 114.

[0110] In an embodiment, the sub-pixel circuit PC may be arranged in the display area DP-DA. The sub-pixel circuit PC may include a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0111] In an embodiment, the semiconductor layer Act may be disposed on the buffer layer 111. The semiconductor layer Act may include polycrystalline silicon. In another embodiment, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, or an organic semiconductor. The semiconductor layer Act may include a channel region and a drain region and a source region respectively arranged on both sides of the channel region.

[0112] In an embodiment, the gate electrode GE may be disposed above the semiconductor layer Act. The gate electrode GE may overlap the channel region. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multilayer structure or a single-layer structure including the above materials.

[0113] In an embodiment, the first gate insulating layer 112 may be disposed between the semiconductor layer Act and the gate electrode GE. The first gate insulating layer 112 may include a silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x ) inorganic insulating material. ZnO x It can be ZnO and / or ZnO 2 .

[0114] In an embodiment, the second gate insulating layer 113 may be disposed on the gate electrode GE. The second gate insulating layer 113 may cover the gate electrode GE. The second gate insulating layer 113 may include a silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x ) of inorganic insulating materials.

[0115] In an embodiment, the second capacitor plate CE2 of the storage capacitor Cst may be disposed on the second gate insulating layer 113. The second capacitor plate CE2 may overlap the gate electrode GE disposed thereunder. In this regard, the gate electrode GE and the second capacitor plate CE2 overlapping each other with the second gate insulating layer 113 therebetween may constitute the storage capacitor Cst. That is, the gate electrode GE may serve as the first capacitor plate CE1 of the storage capacitor Cst.

[0116] In the embodiment and as described above, the storage capacitor Cst and the thin film transistor TFT may overlap each other. However, the present invention is not limited thereto. For example, the storage capacitor Cst may not overlap with the thin film transistor TFT. That is, the first capacitor plate CE1 of the storage capacitor Cst may be spaced apart from the gate electrode GE of the thin film transistor TFT as an element separated from the gate electrode GE of the thin film transistor TFT.

[0117] In an embodiment, the second capacitor plate CE2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including the above materials.

[0118] In an embodiment, the interlayer insulating layer 114 may be disposed on the second capacitor plate CE2. The interlayer insulating layer 114 may cover the second capacitor plate CE2. The interlayer insulating layer 114 may include a silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x The interlayer insulating layer 114 may have a single layer structure or a multilayer structure including the above-mentioned inorganic insulating material.

[0119] In an embodiment, each of the drain electrode DE and the source electrode SE may be located on the interlayer insulating layer 114. Each of the drain electrode DE and the source electrode SE may be connected to the semiconductor layer Act through a contact hole defined in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114. The drain electrode DE and the source electrode SE may include a highly conductive material. The drain electrode DE and the source electrode SE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multilayer structure or a single layer structure including the above materials. For example, the drain electrode DE and the source electrode SE may have a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0120] In an embodiment, the organic insulating layer OIL may be disposed on the inorganic insulating layer IIL. The organic insulating layer OIL may include a first organic insulating layer 115 and a second organic insulating layer 116. Figure 5 The organic insulating layer OIL including two layers is shown, but the present invention is not limited thereto. The organic insulating layer OIL may include three layers or four layers.

[0121] In an embodiment, the first organic insulating layer 115 may cover the drain electrode DE and the source electrode SE. The first organic insulating layer 115 may include an organic insulating material such as a general commercial polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, and a mixture thereof.

[0122] In an embodiment, the connection electrode CM may be disposed on the first organic insulating layer 115. At this point, the connection electrode CM may be connected to the drain electrode DE or the source electrode SE through a contact hole in the first organic insulating layer 115. The connection electrode CM may include a highly conductive material. The connection electrode CM may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multilayer structure or a single layer structure including the above materials. For example, the connection electrode CM may have a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0123] In an embodiment, the second organic insulating layer 116 may be disposed on the connection electrode CM. The second organic insulating layer 116 may cover the connection electrode CM. The second organic insulating layer 116 may include a material that is the same as or different from that of the first organic insulating layer 115 .

[0124] In an embodiment, a light emitting diode may be disposed on the second organic insulating layer 116. For example, an organic light emitting diode OLED may be disposed on the second organic insulating layer 116. In another embodiment, although not shown, an inorganic light emitting diode may be disposed on the second organic insulating layer 116.

[0125] In an embodiment, the organic light emitting diode OLED may emit red light, green light, or blue light, or may emit red light, green light, blue light, or white light. The organic light emitting diode OLED may include a first electrode 211, an emission layer 212b, a functional layer 212f, a second electrode 213, and a capping layer 215. The first electrode 211 may be a pixel electrode (e.g., an anode) of the organic light emitting diode OLED, and the second electrode 213 may be a counter electrode (e.g., a cathode) of the organic light emitting diode OLED.

[0126] In an embodiment, the first electrode 211 may be disposed on the second organic insulating layer 116. The first electrode 211 may be electrically connected to the connection electrode CM through a contact hole defined in the second organic insulating layer 116. The first electrode 211 may include an indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). In an embodiment, the first electrode 211 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a mixture thereof. In an embodiment, the first electrode 211 may further include a reflective layer on / under the above-mentioned reflective layer and made of ITO, IZO, ZnO or In 2 O 3 For example, the first electrode 211 may have a multi-layer structure of ITO / Ag / ITO.

[0127] In an embodiment, a pixel defining layer 118 having an opening defined therein exposing at least a portion of the first electrode 211 may be disposed on the first electrode 211. An emission region of light emitted from the organic light emitting diode OLED may be defined by the opening defined in the pixel defining layer 118. For example, the width of the opening may correspond to the width of the emission region.

[0128] In an embodiment, the pixel defining layer 118 may include an organic insulating material. In another embodiment, the pixel defining layer 118 may include an inorganic insulating material such as silicon nitride, silicon oxynitride or silicon oxide. In yet another embodiment, the pixel defining layer 118 may include an organic insulating material and an inorganic insulating material. In an embodiment, the pixel defining layer 118 may include a light-shielding material. The light-shielding material may include a resin or paste containing carbon black, carbon nanotubes or a black dye, metal (e.g., nickel, aluminum, molybdenum and alloys thereof) particles, metal oxide (e.g., chromium oxide) particles or metal nitride (e.g., chromium nitride) particles. When the pixel defining layer 118 includes a light-shielding material, the reflection of external light caused by the metal structure disposed below the pixel defining layer 118 can be reduced.

[0129] In an embodiment, the spacer 119 may be disposed on the pixel defining layer 118. The spacer 119 may include an organic insulating material such as polyimide. In another embodiment, the spacer 119 may include an organic insulating material such as silicon nitride (SiN x ) or silicon oxide (SiO 2 ) of an inorganic insulating material, or may include an organic insulating material and an inorganic insulating material.

[0130] In an embodiment, the spacer 119 may include the same material as that of the pixel defining layer 118. In this case, the pixel defining layer 118 and the spacer 119 may be formed together during a mask process using a half-tone mask, etc. In another embodiment, the spacer 119 and the pixel defining layer 118 may include different materials.

[0131] In an embodiment, the emission layer 212b may be disposed in the opening of the pixel defining layer 118. The emission layer 212b may include a high molecular weight or low molecular weight organic material that emits light of a specific color.

[0132] In an embodiment, the functional layer 212f may include a first functional layer 212a and a second functional layer 212c. The first functional layer 212a may be disposed between the first electrode 211 and the emission layer 212b, and the second functional layer 212c may be disposed between the emission layer 212b and the second electrode 213. However, at least one of the first functional layer 212a and the second functional layer 212c may be omitted. Hereinafter, an embodiment in which each of the first functional layer 212a and the second functional layer 212c is disposed will be mainly described.

[0133] In an embodiment, the first functional layer 212a may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer 212c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer 212a and / or the second functional layer 212c may be a common layer that completely covers the base substrate SUB like the second electrode 213 described below.

[0134] In an embodiment, the second electrode 213 may be disposed on the functional layer 212f. The second electrode 213 may include a conductive material having a low work function. For example, the second electrode 213 may include a (semi) transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or an alloy thereof. In another embodiment, the second electrode 213 may further include a (semi) transparent layer such as ITO, IZO, ZnO or In2O3 located on the (semi) transparent layer including the above materials. 2 O 3 layer.

[0135] In embodiments, the capping layer 215 may be disposed on the second electrode 213. The capping layer 215 may include an inorganic material such as lithium fluoride (LiF) and / or an organic material.

[0136] In an embodiment, the encapsulation layer TFL may be disposed on the organic light emitting diode OLED. The encapsulation layer TFL may cover the organic light emitting diode OLED. The encapsulation layer TFL may be disposed on the second electrode 213 and / or the capping layer 215. In an embodiment, the encapsulation layer TFL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 5 An encapsulation layer TFL including a first inorganic encapsulation layer 310 , an organic encapsulation layer 320 , and a second inorganic encapsulation layer 330 sequentially stacked on each other is shown.

[0137] In an embodiment, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic materials among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may have a single-layer structure or a multi-layer structure including the above materials. The organic encapsulation layer 320 may include a polymer material. Examples of polymer materials may include acrylic resins, epoxy resins, polyimides and polyethylene. In an embodiment, the organic encapsulation layer 320 may include acrylate.

[0138] In an embodiment, the input sensing layer 40 may be disposed on the encapsulation layer TFL and may include a first touch insulating layer 410 , a second touch insulating layer 420 , a first conductive layer 430 , a third touch insulating layer 440 , a second conductive layer 450 , and a planarization layer 460 .

[0139] In an embodiment, the first touch insulating layer 410 may be disposed on the second inorganic encapsulation layer 330, and the second touch insulating layer 420 may be disposed on the first touch insulating layer 410. In an embodiment, the first touch insulating layer 410 and the second touch insulating layer 420 may include an inorganic insulating material and / or an organic insulating material. For example, the first touch insulating layer 410 and the second touch insulating layer 420 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0140] In an embodiment, at least one of the first touch insulating layer 410 and the second touch insulating layer 420 may be omitted. For example, the first touch insulating layer 410 may be omitted. In this case, the second touch insulating layer 420 may be disposed on the second inorganic encapsulation layer 330, and the first conductive layer 430 may be disposed on the second touch insulating layer 420.

[0141] In an embodiment, the first conductive layer 430 may be disposed on the second touch insulating layer 420, and the third touch insulating layer 440 may be disposed on the first conductive layer 430. In an embodiment, the third touch insulating layer 440 may include an inorganic insulating material and / or an organic insulating material. For example, the third touch insulating layer 440 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0142] In an embodiment, the second conductive layer 450 may be disposed on the third touch insulating layer 440. The touch electrode TE of the input sensing layer 40 may have a structure in which the first conductive layer 430 and the second conductive layer 450 are connected to each other. In another embodiment, the touch electrode TE may be formed in one of the first conductive layer 430 and the second conductive layer 450, and may include a metal wire provided in the corresponding conductive layer. Each of the first conductive layer 430 and the second conductive layer 450 may include at least one of aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), and indium tin oxide (ITO), and may have a single-layer structure or a multilayer structure including the above materials. For example, each of the first conductive layer 430 and the second conductive layer 450 may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0143] In an embodiment, the planarization layer 460 may cover the second conductive layer 450. The planarization layer 460 may include an organic insulating material.

[0144] Figure 6 as well as Figures 8 to 10 is a schematic plan view of a plurality of pads DP-PD arranged in a chip area DCA of a display panel according to an embodiment. Figure 7 According to the embodiment Figure 6 Schematic cross-sectional view of at least some of the multiple pads DP-PD. Figure 7 It is along Figure 6 The line II-II' is intercepted Figure 6 Schematic cross-sectional view of a display panel.

[0145] In the examples and with reference to Figure 6 , a plurality of pads DP-PD may be arranged on the display panel DP (refer to Figure 3 ) in the chip area DCA. The plurality of pads DP-PD in the chip area DCA may include a first pad PD1, a second pad PD2, and a third pad PD3. The first pad PD1 may be arranged in a first direction DR1. The second pad PD2 may be arranged in the first direction DR1 and may be spaced apart from the first pad PD1 in the second direction DR2. The third pad PD3 may be arranged in the first direction DR1 and may be spaced apart from the second pad PD2 in the second direction DR2.

[0146] In the embodiment, the first pad PD1 is connected to the display area DP-DA (refer to Figure 3 ) may be the smallest, and the shortest distance between the third pad PD3 and the display area DP-DA of the display panel DP may be the largest. The shortest distance between the second pad PD2 and the display area DP-DA of the display panel DP may be the middle distance between the shortest distance between the first pad PD1 and the display area DP-DA of the display panel DP and the shortest distance between the third pad PD3 and the display area DP-DA of the display panel DP. However, the present invention is not limited thereto.

[0147] In an embodiment, the plurality of pads DP-PD in the chip area DCA may include a first pad column PDL1, a second pad column PDL2, and a third pad column PDL3. Each of the first pad column PDL1, the second pad column PDL2, and the third pad column PDL3 may include a first pad PD1, a second pad PD2, and a third pad PD3 arranged in the second direction DR2. The first pad column PDL1, the second pad column PDL2, and the third pad column PDL3 may be spaced apart from each other in the first direction DR1. The shortest distance between the first pad PD1 and the second pad PD2 may be smaller than the shortest distance between the first pad PD1 and the third pad PD3.

[0148] In the examples and with reference to Figure 7, a plurality of pads DP-PD may be provided on the base substrate SUB and the inorganic insulating layer IIL (refer to Figure 5 ). More specifically, a plurality of pads DP-PD may be disposed on the second gate insulating layer 113. The plurality of pads DP-PD may be disposed on the same layer and include Figure 5 The material of the second capacitor plate CE2 of the storage capacitor Cst shown in FIG.

[0149] In an embodiment, a plurality of buffers BP may be arranged at a driving chip DC in a 1:1 correspondence with a plurality of pads DP-PD. An anisotropic conductive film ACF may be provided between the plurality of buffers BP and the plurality of pads DP-PD, and the anisotropic conductive film ACF may include a conductive ball CB containing nickel (Ni). The plurality of buffers BP of the driving chip DC and the plurality of pads DP-PD of the chip area DCA of the display panel DP may be electrically connected to each other through the conductive ball CB. Therefore, through the plurality of pads DP-PD, an electrical signal may be applied from the driving chip DC to the sub-pixel circuit PC of the display panel DP.

[0150] In an embodiment, in the first pad column PDL1, only the first pad PD1 can be connected to the connection line CGL. When a signal is applied to the first pad PD1 in the first pad column PDL1, the signal can be applied to the sub-pixel circuit PC through the connection line CGL connected to the first pad PD1. In the second pad column PDL2, only the second pad PD2 can be connected to the connection line CGL, and in the third pad column PDL3, only the third pad PD3 can be connected to the connection line CGL. In other words, the signal can be applied from the driving chip DC to the sub-pixel circuit PC only through the second pad PD2 in the second pad column PDL2 and the third pad PD3 in the third pad column PDL3.

[0151] In an embodiment, in the first pad column PDL1, the second and third pads PD2 and PD3 not connected to the connection line CGL may be in a floating state. No signal may be applied from the driving chip DC to the second and third pads PD2 and PD3 not connected to the connection line CGL in the first pad column PDL1.

[0152] In an embodiment, in the second pad column PDL2, the first and third pads PD1 and PD3 not connected to the connection line CGL may be in a floating state. No signal may be applied from the driving chip DC to the first and third pads PD1 and PD3 not connected to the connection line CGL in the second pad column PDL2.

[0153] In an embodiment, in the third pad column PDL3, the first and second pads PD1 and PD2 not connected to the connection line CGL may be in a floating state. No signal may be applied from the driving chip DC to the first and second pads PD1 and PD2 not connected to the connection line CGL in the third pad column PDL3.

[0154] In an embodiment, the plurality of pads DP-PD in the chip area DCA may include a first pad group PDG1.

[0155] The first pad group PDG1 may include a first pad column PDL1 , a second pad column PDL2 , and a third pad column PDL3 .

[0156] The first pad group PDG1 may be arranged in the first direction DR1.

[0157] In an embodiment, among the first pads PD1, the first pads PD1 connected to the connection line CGL may be spaced apart from each other, wherein two first pads PD1 disposed therebetween are not connected to the connection line CGL. Among the second pads PD2, the second pads PD2 connected to the connection line CGL may be spaced apart from each other, wherein two second pads PD2 disposed therebetween are not connected to the connection line CGL. Among the third pads PD3, the third pads PD3 connected to the connection line CGL may be spaced apart from each other, wherein two third pads PD3 disposed therebetween are not connected to the connection line CGL.

[0158] In the examples and with reference to Figure 8 , a plurality of pads DP-PD may be arranged in a chip area DCA of a display panel DP. The plurality of pads DP-PD in the chip area DCA may include a first pad PD1, a second pad PD2, and a third pad PD3. The first pad PD1 may be arranged in a first direction DR1. The second pad PD2 may be arranged in the first direction DR1 and may be spaced apart from the first pad PD1 in the second direction DR2. The third pad PD3 may be arranged in the first direction DR1 and may be spaced apart from the second pad PD2 in the second direction DR2.

[0159] In an embodiment, the plurality of pads DP-PD in the chip area DCA may include a first pad column PDL1, a second pad column PDL2, a third pad column PDL3, and a fourth pad column PDL4. Each of the first pad column PDL1, the second pad column PDL2, the third pad column PDL3, and the fourth pad column PDL4 may include a first pad PD1, a second pad PD2, and a third pad PD3 arranged in the second direction DR2. The first pad column PDL1, the second pad column PDL2, the third pad column PDL3, and the fourth pad column PDL4 may be spaced apart from each other in the first direction DR1.

[0160] In an embodiment, in the first pad column PDL1, only the first pad PD1 can be connected to the connection line CGL. When a signal is applied to the first pad PD1 in the first pad column PDL1, the signal can be applied from the driving chip DC to the sub-pixel circuit PC through the connection line CGL connected to the first pad PD1. In the second pad column PDL2, only the second pad PD2 can be connected to the connection line CGL, and in the third pad column PDL3, only the third pad PD3 can be connected to the connection line CGL. In the fourth pad column PDL4, only the second pad PD2 can be connected to the connection line CGL. In other words, the signal can be applied from the driving chip DC to the sub-pixel circuit PC only through the second pad PD2 in the second pad column PDL2, the third pad PD3 in the third pad column PDL3, and the second pad PD2 in the fourth pad column PDL4.

[0161] In an embodiment, in the first pad column PDL1, the second and third pads PD2 and PD3 not connected to the connection line CGL may be in a floating state. No signal may be applied from the driving chip DC to the second and third pads PD2 and PD3 not connected to the connection line CGL in the first pad column PDL1.

[0162] In an embodiment, in the second pad column PDL2, the first and third pads PD1 and PD3 not connected to the connection line CGL may be in a floating state. No signal may be applied from the driving chip DC to the first and third pads PD1 and PD3 not connected to the connection line CGL in the second pad column PDL2.

[0163] In an embodiment, in the third pad column PDL3, the first and second pads PD1 and PD2 not connected to the connection line CGL may be in a floating state. No signal may be applied from the driving chip DC to the first and second pads PD1 and PD2 not connected to the connection line CGL in the third pad column PDL3.

[0164] In an embodiment, in the fourth pad column PDL4, the first and third pads PD1 and PD3 not connected to the connection line CGL may be in a floating state. No signal may be applied from the driving chip DC to the first and third pads PD1 and PD3 not connected to the connection line CGL in the fourth pad column PDL4.

[0165] In an embodiment, the plurality of pads DP-PD in the chip area DCA may include a second pad group PDG2. The second pad group PDG2 may include first, second, third, and fourth pad columns PDL1, PDL2, PDL3, and PDL4. The second pad group PDG2 may be arranged in the first direction DR1.

[0166] In an embodiment, among the first pads PD1, the first pads PD1 connected to the connection line CGL may be spaced apart from each other, wherein three first pads PD1 disposed therebetween are not connected to the connection line CGL. Among the second pads PD2, the second pads PD2 connected to the connection line CGL may be spaced apart from each other, wherein one second pad PD2 disposed therebetween is not connected to the connection line CGL. Among the third pads PD3, the third pads PD3 connected to the connection line CGL may be spaced apart from each other, wherein three third pads PD3 disposed therebetween are not connected to the connection line CGL.

[0167] In the examples and with reference to Fig. 9 , a plurality of pads DP-PD may be arranged in the chip area DCA of the display panel DP. The plurality of pads DP-PD in the chip area DCA may include a first pad PD1 and a second pad PD2. The first pad PD1 may be arranged in a first direction DR1. The second pad PD2 may be arranged in the first direction DR1 and may be spaced apart from the first pad PD1 in the second direction DR2.

[0168] In an embodiment, the plurality of pads DP-PD in the chip area DCA may include a first pad column PDL1 and a second pad column PDL2. Each of the first pad column PDL1 and the second pad column PDL2 may include a first pad PD1 and a second pad PD2 arranged in the second direction DR2. The first pad column PDL1 and the second pad column PDL2 may be spaced apart from each other in the first direction DR1.

[0169] In an embodiment, in the first pad column PDL1, only the first pad PD1 may be connected to the connection line CGL. When a signal is applied only to the first pad PD1 in the first pad column PDL1, the signal may be applied from the driving chip DC to the sub-pixel circuit PC through the connection line CGL connected to the first pad PD1. In the second pad column PDL2, only the second pad PD2 may be connected to the connection line CGL. When a signal is applied only to the second pad PD2 in the second pad column PDL2, the signal may be applied from the driving chip DC to the sub-pixel circuit PC through the connection line CGL connected to the second pad PD2.

[0170] In an embodiment, in the first pad column PDL1, the second pads PD2 not connected to the connection line CGL may be in a floating state. No signal may be applied from the driving chip DC to the second pads PD2 not connected to the connection line CGL in the first pad column PDL1.

[0171] In an embodiment, in the second pad column PDL2, the first pads PD1 not connected to the connection line CGL may be in a floating state. No signal may be applied from the driving chip DC to the first pads PD1 not connected to the connection line CGL in the second pad column PDL2.

[0172] In an embodiment, the plurality of pads DP-PD in the chip area DCA may include a third pad group PDG3. The third pad group PDG3 may include a first pad column PDL1 and a second pad column PDL2. The third pad group PDG3 may be arranged in the first direction DR1.

[0173] In an embodiment, among the first pads PD1, the first pads PD1 connected to the connection line CGL may be spaced apart from each other, wherein one first pad PD1 disposed therebetween is not connected to the connection line CGL. Among the second pads PD2, the second pads PD2 connected to the connection line CGL may be spaced apart from each other, wherein one second pad PD2 disposed therebetween is not connected to the connection line CGL.

[0174] In the examples and with reference to Fig.10 , a plurality of pads DP-PD may be arranged in the chip area DCA of the display panel DP. The plurality of pads DP-PD may include a first pad PD1, a second pad PD2, and a third pad PD3. The first pad PD1 may be arranged in a first direction DR1. The second pad PD2 may be arranged in the first direction DR1 and may be spaced apart from the first pad PD1 in the second direction DR2. The third pad PD3 may be arranged in the first direction DR1 and may be spaced apart from the second pad PD2 in the second direction DR2.

[0175] In an embodiment, the plurality of pads DP-PD in the chip area DCA may include a first pad column PDL1 and a second pad column PDL2. Each of the first pad column PDL1 and the second pad column PDL2 may include a first pad PD1, a second pad PD2, and a third pad PD3 arranged in the second direction DR2. The first pad column PDL1 and the second pad column PDL2 may be spaced apart from each other in the first direction DR1.

[0176] In an embodiment, in the first pad column PDL1, only the first pad PD1 may be connected to the connection line CGL. When a signal is applied only to the first pad PD1 in the first pad column PDL1, the signal may be applied from the driving chip DC to the sub-pixel circuit PC through the connection line CGL connected to the first pad PD1. In the second pad column PDL2, only the second pad PD2 may be connected to the connection line CGL. When a signal is applied only to the second pad PD2 in the second pad column PDL2, the signal may be applied from the driving chip DC to the sub-pixel circuit PC through the connection line CGL connected to the second pad PD2.

[0177] In an embodiment, in the first pad column PDL1, the second and third pads PD2 and PD3 not connected to the connection line CGL may be in a floating state. No signal may be applied from the driving chip DC to the second and third pads PD2 and PD3 not connected to the connection line CGL in the first pad column PDL1.

[0178] In an embodiment, in the second pad column PDL2, the first and third pads PD1 and PD3 not connected to the connection line CGL may be in a floating state. No signal may be applied from the driving chip DC to the first and third pads PD1 and PD3 not connected to the connection line CGL in the second pad column PDL2.

[0179] In an embodiment, the plurality of pads DP-PD in the chip area DCA may include a fourth pad group PDG4. The fourth pad group PDG4 may include a first pad column PDL1 and a second pad column PDL2. The fourth pad group PDG4 may be arranged in the first direction DR1.

[0180] In an embodiment, among the first pads PD1, the first pads PD1 connected to the connection line CGL may be spaced apart from each other, wherein one first pad PD1 disposed therebetween is not connected to the connection line CGL. Among the second pads PD2, the second pads PD2 connected to the connection line CGL may be spaced apart from each other, wherein one second pad PD2 disposed therebetween is not connected to the connection line CGL.

[0181] When only the first pad PD1 among the multiple pads DP-PD of the chip area DCA is connected to the connecting line CGL, and the signal is applied from the driving chip DC to the sub-pixel circuit PC of the display panel DP through the first pad PD1 and the connecting line CGL, the connecting lines CGL may be arranged to be adjacent to each other, and therefore, the nickel (Ni) included in the conductive ball CB may be oxidized in a high temperature and high humidity reliability environment, and the resistance of the conductive ball CB and the connecting line CGL may increase due to the loss of nickel (Ni), thereby preventing current from flowing.

[0182] In an embodiment, in order to prevent oxidation of nickel (Ni) included in the conductive balls CB, the connection wires CGL need to be spaced as far apart as possible. According to one or more embodiments, oxidation of nickel (Ni) included in the conductive balls CB can be prevented by spacing the connection wires CGL as far apart as possible, and thus, current can be prevented from not flowing due to increased resistance of the connection wires CGL.

[0183] According to one or more of the above-described embodiments, a display device with improved reliability and quality can be realized. However, one or more embodiments are not limited to such effects.

[0184] It should be understood that the embodiments described herein should be considered in a descriptive sense only, and not for the purpose of limitation. The description of the features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Accordingly, the scope of the various embodiments of the present invention should be interpreted as including all changes or modifications that can be obtained from the technical ideas of the various embodiments in addition to the embodiments disclosed herein. In addition, embodiments or parts of embodiments can be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A display device, comprising: A display panel including a plurality of pads; as well as A driving chip comprising a plurality of buffers corresponding to the plurality of pads, Wherein, the plurality of pads include: A plurality of first pads arranged in a first direction; a plurality of second pads arranged in the first direction and spaced apart from the plurality of first pads in a second direction crossing the first direction; and a plurality of third pads arranged in the first direction and spaced apart from the plurality of second pads in the second direction, wherein the first pad column, the second pad column and the third pad column each include the first pad, the second pad and the third pad arranged in the second direction, wherein the first pad column, the second pad column and the third pad column are spaced apart from each other in the first direction, wherein only the first pad in the first pad column, the second pad in the second pad column, and the third pad in the third pad column are connected to a connection line, and Among them, in the first pad column, the second pad and the third pad that are not connected to the connection line are in a floating state.

2. The display device according to claim 1, wherein: A signal is not applied to the second pad and the third pad in the first pad column that are not connected to the connection line.

3. The display device according to claim 1, wherein: When a signal is applied to the first pad connected to the connection line, the signal is applied to the sub-pixel circuit through the connection line.

4. The display device according to claim 1, wherein: In the second pad column, the first pad and the third pad that are not connected to the connection line are in a floating state.

5. The display device according to claim 1, wherein: In the third pad column, the first pad and the second pad that are not connected to the connection line are in a floating state.

6. The display device according to claim 1, wherein: The first pad group includes the first pad column, the second pad column and the third pad column, and Wherein, the first pad group is arranged in the first direction.

7. The display device according to claim 6, wherein: The first pads connected to the connection line are spaced apart from each other, wherein two of the first pads not connected to the connection line are disposed between the first pads connected to the connection line.

8. The display device according to claim 6, wherein: The second pads connected to the connection line are spaced apart from each other, wherein two of the second pads not connected to the connection line are disposed between the second pads connected to the connection line.

9. The display device according to claim 6, wherein: The third pads connected to the connection line are spaced apart from each other, wherein two of the third pads not connected to the connection line are disposed between the third pads connected to the connection line.

10. A display device, comprising: A display panel including a plurality of pads; as well as A driving chip comprising a plurality of buffers corresponding to the plurality of pads, Wherein, the plurality of pads include: A plurality of first pads arranged in a first direction; a plurality of second pads arranged in the first direction and spaced apart from the plurality of first pads in a second direction crossing the first direction; and a plurality of third pads arranged in the first direction and spaced apart from the plurality of second pads in the second direction, wherein the first pad column, the second pad column, the third pad column and the fourth pad column each include the first pad, the second pad and the third pad arranged in the second direction, wherein the first pad column, the second pad column, the third pad column and the fourth pad column are spaced apart from each other in the first direction, wherein only the first pad in the first pad column, the second pad in the second pad column, the third pad in the third pad column, and the second pad in the fourth pad column are connected to a connection line, and Among them, in the first pad column, the second pad and the third pad that are not connected to the connection line are in a floating state.

11. The display device according to claim 10, wherein: In the second pad column, the first pad and the third pad that are not connected to the connection line are in a floating state.

12. The display device according to claim 10, wherein: In the third pad column, the first pad and the second pad that are not connected to the connection line are in a floating state.

13. The display device according to claim 10, wherein: In the fourth pad column, the first pad and the third pad that are not connected to the connection line are in a floating state.

14. The display device according to claim 10, wherein: The second pad group includes the first pad column, the second pad column, the third pad column and the fourth pad column, and Wherein, the second pad group is arranged in the first direction.

15. The display device according to claim 10, wherein: The first pads connected to the connection line are spaced apart from each other, wherein three of the first pads that are not connected to the connection line are disposed between the first pads connected to the connection line.

16. The display device according to claim 10, wherein: The second pads connected to the connection line are spaced apart from each other, wherein one of the second pads not connected to the connection line is disposed between the second pads connected to the connection line.

17. The display device according to claim 10, wherein: The third pads connected to the connection line are spaced apart from each other, wherein three of the third pads that are not connected to the connection line are disposed between the third pads connected to the connection line.

18. A display device comprising: A display panel including a plurality of pads; as well as A driving chip comprising a plurality of buffers corresponding to the plurality of pads, Wherein, the plurality of pads include: a plurality of first pads arranged in a first direction; and a plurality of second pads arranged in the first direction and spaced apart from the plurality of first pads in a second direction crossing the first direction, The first pad column and the second pad column each include the first pad and the second pad arranged in the second direction, wherein the first pad column and the second pad column are spaced apart from each other in the first direction, wherein the first pads in the first pad column and the second pads in the second pad column are connected to a connection line, and Among them, in the first pad column, the second pads not connected to the connection line are in a floating state.

19. The display device according to claim 18, wherein: In the second pad column, the first pads not connected to the connection line are in a floating state.

20. The display device according to claim 18, wherein: The third pad group includes the first pad column and the second pad column, Wherein, the third pad group is arranged in the first direction.

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