Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, and the semiconductor structure comprises a substrate which is provided with a first side and a second side, and the second side is opposite to the first side; a back-end process layer disposed on the first side of the substrate; a plurality of first metal structures penetrating the substrate; and the plurality of second metal structures are arranged in the substrate, extend from the second side of the substrate to the first side and are arranged corresponding to the plurality of first metal structures.

Description

Technical Field

[0001] The present application relates to a semiconductor structure, and more particularly to a semiconductor structure including an embedded metal-insulator-metal (MIM) capacitor. Background Art

[0002] Semiconductor devices are widely used in various electronic products, such as personal computers, mobile phones, digital cameras and other electronic devices. The size of electronic components such as existing semiconductor device application products has a trend of getting smaller and smaller, but due to the physical characteristics of capacitors, they still need to occupy more space, so semiconductor devices still need to continue to move towards the goal of miniaturization. Summary of the invention

[0003] The present application provides a semiconductor structure, including: a substrate having a first side and a second side, the second side being opposite to the first side; a back-end process layer disposed on the first side of the substrate; a plurality of first metal structures penetrating the substrate; and a plurality of second metal structures disposed in the substrate, extending from the second side of the substrate toward the first side, and disposed correspondingly to the plurality of first metal structures.

[0004] The present application provides a semiconductor structure, comprising: a first semiconductor unit, comprising: a first substrate, having a first side and a second side, the second side being opposite to the first side; a first back-end process layer, arranged on the first side of the first substrate; a plurality of first metal structures, penetrating the first substrate; and a plurality of second metal structures, arranged in the first substrate, extending from the second side of the first substrate toward the first side, and arranged corresponding to the plurality of first metal structures; and a second semiconductor unit, electrically connected to the first semiconductor unit, the second semiconductor unit comprising: a second substrate, having a first side and a second side, the second side being opposite to the first side; a second back-end process layer, arranged on the first side of the second substrate; a plurality of third metal structures, penetrating the second substrate; and a plurality of fourth metal structures, arranged in the second substrate, extending from the second side of the second substrate toward the first side, and arranged corresponding to the plurality of third metal structures.

[0005] The present application provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, on which a base plate is disposed, the base plate having a first side and a second side, the second side being opposite to the first side, wherein a back-end process layer is disposed on the first side of the base plate, and a plurality of first metal structures penetrate the base plate; arranging a plurality of lead holes (via) in the base plate, the plurality of lead holes extending from the second side of the base plate toward the first side, and being disposed corresponding to the plurality of first metal structures; and filling metal into the plurality of lead holes to form a plurality of second metal structures.

[0006] The present application uses silicon via technology to make an embedded capacitor structure in a wafer. This structure uses two silicon via processes to form silicon vias on the front wafer surface and silicon vias on the rear wafer surface. The silicon vias on the front wafer surface and the silicon vias on the rear wafer surface can be used as upper and lower electrodes of a silicon capacitor, respectively, and form a vertical embedded capacitor with a substrate sandwiched between the two. This process step can be completed together in the stacking process of a three-dimensional IC, which can save process steps and costs. Specifically, this process only needs to perform an additional silicon via process on the rear wafer surface after performing a traditional silicon via process (after forming silicon vias on the front wafer surface), and then continue to perform subsequent stacking processes to form silicon vias on the rear wafer surface, so that silicon vias on the front wafer surface and silicon vias on the rear wafer surface can be formed as upper and lower electrodes of the embedded capacitor. In addition, since the rear wafer surface generally only has silicon vias turned on, and no other routing is arranged, its wiring is simple. Compared with making silicon vias from the front wafer surface, due to the complex wiring of the front wafer surface, it will be necessary to add an additional copper layer, resulting in the complexity of the circuit. In addition, the process of the present application can easily produce a conductive structure in which multiple semiconductor units (chips) are stacked on each other, thereby greatly increasing the storage space of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 , Figure 3 and Figure 4 According to an embodiment of the present application, a top view of a semiconductor structure;

[0008] Figure 2 and Figure 5 A schematic cross-sectional view of a semiconductor structure is provided in accordance with an embodiment of the present application;

[0009] Figure 6A-6H The present invention is a cross-sectional schematic diagram of a method for manufacturing a semiconductor structure according to an embodiment of the present application.

[0010] Reference Numbers

[0011] 10,100:Semiconductor structure

[0012] 12,120,122:Substrate

[0013] 12a, 120a, 122a: first side of substrate

[0014] 12b, 120b, 122b: Second side of the substrate

[0015] 14: Back-end of line (BEOL) layer

[0016] 14a, 140a, 142a: Metal layer

[0017] 14b, 140b, 142b: Interlayer window

[0018] 16,18,160,162,180,182:Metal structure

[0019] 18': Partial structure of metal structure 18

[0020] 20,22,200,202,220,222: Bump

[0021] 24,240,242: redistribution layer

[0022] 26,260,262: Part of the substrate

[0023] 28,280,282: Metal-Insulator-Metal (MIM) Capacitors

[0024] 30: Matrix

[0025] 32:Viscose

[0026] 34: Substrate

[0027] 36: Patterned photoresist layer

[0028] 38: Lead hole

[0029] 40:Metal materials

[0030] 101,102:Semiconductor unit

[0031] 140,142: Back-end process layer DETAILED DESCRIPTION

[0032] Figure 1 FIG. 1 is a top view of a semiconductor structure 10 according to an embodiment of the present application. Figure 2 For along Figure 1 Schematic diagram of the cross section obtained by the A-A' section line. Figure 1 and Figure 2 The semiconductor structure 10 includes a substrate 12, a back end of line (BEOL) layer 14, a plurality of metal structures 16, and a plurality of metal structures 18. The substrate 12 has a first side 12a and a second side 12b opposite to the first side 12a. The back end of line layer 14 is disposed on the first side 12a of the substrate 12. The metal structure 16 penetrates the substrate 12. The metal structure 18 is disposed in the substrate 12, extending from the second side 12b of the substrate 12 toward the first side 12a, and is disposed corresponding to the metal structure 16. In the present application, the disposition of the metal structure 16 and the metal structure 18 may include different corresponding methods, which will be described in detail later.

[0033] In one embodiment, the substrate 12 may include a hard substrate or a flexible substrate. The hard substrate may include, for example, a silicon substrate or a glass substrate, but the present application is not limited thereto. The flexible substrate may include, for example, a polyimide (PI) substrate, a polyethylene terephthalate (PET) substrate, or a polycarbonate (PC) substrate, but the present application is not limited thereto.

[0034] In one embodiment, the back-end process layer 14 may include multiple metal layers 14a. Different metal layers 14a are connected by vias 14b filled with metal materials. In one embodiment, copper may be selected as the metal material filled in the vias 14b.

[0035] In one embodiment, the metal structure 16 and the metal structure 18 may include copper or other suitable metal conductive materials. In one embodiment, in the metal structure 16 and the metal structure 18, an oxide material layer as an insulating layer and a tantalum (Ta) metal layer as a seed layer may be further included between the filled metal conductive material and the substrate 12 to facilitate subsequent filling, for example, of a copper metal layer. In one embodiment, the metal structure 16 and the metal structure 18 may include a columnar structure, for example, a cylindrical structure or a columnar structure of any other shape. In the present application, the metal structure 16 may be referred to as a frontside through-silicon via (TSV), and the metal structure 18 may be referred to as a backside through-silicon via.

[0036] In one embodiment, the corresponding arrangement of the metal structure 16 and the metal structure 18 may include one metal structure 16 corresponding to one metal structure 18, such as Figure 1 and Figure 2 That is, one TSV on the front wafer surface corresponds to one TSV on the back wafer surface.

[0037] In one embodiment, the semiconductor structure 10 further includes a plurality of bumps 20, a plurality of bumps 22, and a redistribution layer (RDL) 24. Figure 2 As shown. The bump 20 is disposed on the back-end process layer 14. The bump 22 is disposed on the metal structure 16. The redistribution layer 24 is disposed on the second side 12b of the substrate 12, covering the metal structure 16 and the metal structure 18, and exposing the bump 22. Figure 2 In the embodiment, the bump 20 , the back-end process layer 14 , the metal structure 16 , and the bump 22 form a conductive path, which can electrically connect the semiconductor structure 10 to other semiconductor structures.

[0038] In one embodiment, one of the metal structures 16, one of the metal structures 18, and a portion 26 of the substrate 12 between the metal structures 16 and 18 form a single set of Metal-Insulator-Metal (MIM) capacitors 28. In the present application, the MIM capacitors 28 may be embedded MIM capacitors.

[0039] It is worth mentioning that due to the simple structure of this embodiment, the semiconductor structure 10 can be easily configured with hundreds to thousands of MIM capacitors 28, and its overall capacitance can easily reach the capacitance of an ultra-small capacitor, for example, 0.1pF to 33pF, which can replace traditional ultra-small capacitors.

[0040] Figure 3 FIG. 1 is a top view of a semiconductor structure 10 according to another embodiment of the present application. Figure 3 An embodiment similar to Figure 1 and Figure 2 The main difference between the embodiments shown is the corresponding configuration and arrangement of the metal structure 16 and the metal structure 18. Figure 3 In one embodiment, the metal structure 16 may include a columnar structure, such as a cylindrical structure or a columnar structure of any other shape. The metal structure 18 may include a rectangular structure, such as a rectangular groove structure or a columnar structure of any other shape, but the present application is not limited thereto, and other suitable structural shapes are also applicable to the present application.

[0041] like Figure 3 As shown, in one embodiment, the corresponding arrangement of the metal structure 16 and the metal structure 18 may include a plurality of metal structures 16 corresponding to one of the metal structures 18 , that is, a plurality of front wafer surface TSVs corresponding to one rear wafer surface TSV.

[0042] In one embodiment, one of the metal structures 16, the partial structure 18' of the metal structure 18, and the partial region 26 of the substrate 12 between the metal structure 16 and the partial structure 18' of the metal structure 18 form a single set of MIM capacitors 28. In the present application, the MIM capacitors 28 may be embedded MIM capacitors.

[0043] It is worth mentioning that due to the simple structure of this embodiment, the semiconductor structure 10 can be easily configured with hundreds to thousands of MIM capacitors 28, and its overall capacitance can easily reach the capacitance of an ultra-small capacitor, for example, 0.1pF to 33pF, which can replace traditional ultra-small capacitors.

[0044] Figure 4 FIG. 1 is a top view of a semiconductor structure 10 according to another embodiment of the present application. Figure 4 An embodiment similar to Figure 1 and Figure 2 The main difference between the illustrated embodiments lies in the corresponding manner in which the metal structures 16 and 18 are disposed.

[0045] like Figure 4 As shown, in one embodiment, the corresponding arrangement of the metal structure 16 and the metal structure 18 is as follows: the metal structures 16 are arranged to form a matrix 30, and the metal structures 18 are arranged on both sides of the matrix 30, that is, a front wafer surface silicon via located on the outside of the matrix 30 corresponds to a rear wafer surface silicon via.

[0046] In one embodiment, one of the metal structures 16, one of the metal structures 18, and a portion 26 of the substrate 12 between the metal structures 16 and 18 form a single set of MIM capacitors 28. In the present application, the MIM capacitors 28 may be embedded MIM capacitors.

[0047] It is worth mentioning that due to the simple structure of this embodiment, the semiconductor structure 10 can be easily configured with hundreds to thousands of MIM capacitors 28, and its overall capacitance can easily reach the capacitance of an ultra-small capacitor, for example, 0.1pF to 33pF, which can replace traditional ultra-small capacitors.

[0048] Figure 5 FIG. 1 is a cross-sectional view of a semiconductor structure 100 according to an embodiment of the present application. Figure 5 The semiconductor structure 100 includes a semiconductor unit 101 and a semiconductor unit 102 , and the semiconductor unit 101 and the semiconductor unit 102 are electrically connected.

[0049] The semiconductor unit 101 includes a substrate 120, a back-end process layer 140, a plurality of metal structures 160, and a plurality of metal structures 180. The substrate 120 has a first side 120a and a second side 120b opposite to the first side 120a. The back-end process layer 140 is disposed on the first side 120a of the substrate 120. The metal structure 160 penetrates the substrate 120. The metal structure 180 is disposed in the substrate 120, extending from the second side 120b of the substrate 120 toward the first side 120a, and is disposed corresponding to the metal structure 160.

[0050] In one embodiment, the substrate 120 may include a hard substrate or a flexible substrate. The hard substrate may include, for example, a silicon substrate or a glass substrate, but the present application is not limited thereto. The flexible substrate may include, for example, a polyimide (PI) substrate, a polyethylene terephthalate (PET) substrate, or a polycarbonate (PC) substrate, but the present application is not limited thereto.

[0051] In one embodiment, the back-end process layer 140 may include multiple metal layers 140a. Different metal layers 140a are connected by vias 140b filled with metal materials. In one embodiment, copper may be selected as the metal material filled in the vias 140b.

[0052] In one embodiment, the metal structure 160 and the metal structure 180 may include copper or other suitable metal conductive materials. In one embodiment, in the metal structure 160 and the metal structure 180, an oxide material layer as an insulating layer and a tantalum (Ta) metal layer as a seed layer are further included between the filled metal conductive material and the substrate 120 to facilitate subsequent filling, for example, of a copper metal layer. In one embodiment, the metal structure 160 and the metal structure 180 may include a columnar structure, for example, a cylindrical structure or a columnar structure of any other shape. In the present application, the metal structure 160 may be referred to as a front wafer surface silicon via, and the metal structure 180 may be referred to as a rear wafer surface silicon via.

[0053] In one embodiment, the corresponding arrangement of the metal structure 160 and the metal structure 180 may include one metal structure 160 corresponding to one metal structure 180, such as Figure 5 As shown, that is, one front wafer side TSV corresponds to one back wafer side TSV.

[0054] In one embodiment, the semiconductor unit 101 further includes a plurality of bumps 200, a plurality of bumps 220, and a redistribution layer 240. Figure 5 As shown. The bump 200 is disposed on the back-end process layer 140. The bump 220 is disposed on the metal structure 160. The redistribution layer 240 is disposed on the second side 120b of the substrate 120, covering the metal structure 160 and the metal structure 180, and exposing the bump 220. In the semiconductor unit 101, the bump 200, the back-end process layer 140, the metal structure 160, and the bump 220 can be electrically connected to each other, so that the semiconductor unit 101 is electrically connected to other semiconductor units.

[0055] In one embodiment, one of the metal structures 160, one of the metal structures 180, and a portion 260 of the substrate 120 between the metal structures 160 and 180 form a single set of MIM capacitors 280. In the present application, the MIM capacitors 280 may be embedded MIM capacitors.

[0056] It is worth mentioning that due to the simple structure of this embodiment, the semiconductor unit 101 can be easily configured with hundreds to thousands of MIM capacitors 280, and its overall capacitance can easily reach the capacitance of an ultra-small capacitor, for example, 0.1pF to 33pF, which can replace traditional ultra-small capacitors.

[0057] like Figure 5As shown, the semiconductor unit 102 includes a substrate 122, a back-end process layer 142, a plurality of metal structures 162, and a plurality of metal structures 182. The substrate 122 has a first side 122a and a second side 122b opposite to the first side 122a. The back-end process layer 142 is disposed on the first side 122a of the substrate 122. The metal structure 162 penetrates the substrate 122. The metal structure 182 is disposed in the substrate 122, extending from the second side 122b of the substrate 122 toward the first side 122a, and is disposed corresponding to the metal structure 162.

[0058] In one embodiment, the substrate 122 may include a hard substrate or a flexible substrate. The hard substrate may include, for example, a silicon substrate or a glass substrate, but the present application is not limited thereto. The flexible substrate may include, for example, a polyimide (PI) substrate, a polyethylene terephthalate (PET) substrate, or a polycarbonate (PC) substrate, but the present application is not limited thereto.

[0059] In one embodiment, the back-end process layer 142 may include multiple metal layers 142a. Different metal layers 142a are connected by vias 142b filled with metal materials. In one embodiment, copper may be selected as the metal material filled in the vias 142b.

[0060] In one embodiment, the metal structure 162 and the metal structure 182 may include copper or other suitable metal conductive materials. In one embodiment, in the metal structure 162 and the metal structure 182, an oxide material layer as an insulating layer and a tantalum (Ta) metal layer as a seed layer are further included between the filled metal conductive material and the substrate 122 to facilitate subsequent filling, for example, of a copper metal layer. In one embodiment, the metal structure 162 and the metal structure 182 may include a columnar structure, for example, a cylindrical structure or a columnar structure of any other shape. In the present application, the metal structure 162 may be referred to as a front wafer surface silicon via, and the metal structure 182 may be referred to as a rear wafer surface silicon via.

[0061] In one embodiment, the corresponding arrangement of the metal structure 162 and the metal structure 182 may include one metal structure 162 corresponding to one metal structure 182, such as Figure 5 As shown, that is, one front wafer side TSV corresponds to one back wafer side TSV.

[0062] In one embodiment, the semiconductor unit 102 further includes a plurality of bumps 202, a plurality of bumps 222, and a redistribution layer 242. Figure 5As shown. The bump 202 is disposed on the back-end process layer 142. The bump 222 is disposed on the metal structure 162. The redistribution layer 242 is disposed on the second side 122b of the substrate 122, covering the metal structure 162 and the metal structure 182, and exposing the bump 222. In the semiconductor unit 102, the bump 202, the back-end process layer 142, the metal structure 162, and the bump 222 form a conductive path, which can electrically connect the semiconductor unit 102 to other semiconductor units.

[0063] like Figure 5 As shown, the metal structure 160 in the semiconductor unit 101 and the metal structure 162 in the semiconductor unit 102 are electrically connected via conductive paths (bumps / metal layers / vias) in the semiconductor unit 101 and the semiconductor unit 102 .

[0064] In one embodiment, one of the metal structures 162, one of the metal structures 182, and a portion 262 of the substrate 122 between the metal structures 162 and 182 form a single set of MIM capacitors 282. In the present application, the MIM capacitors 282 may be embedded MIM capacitors.

[0065] It is worth mentioning that due to the simple structure of this embodiment, the semiconductor unit 102 can be easily configured with hundreds to thousands of MIM capacitors 282, and its overall capacitance can easily reach the capacitance of an ultra-small capacitor, for example, 0.1pF to 33pF, which can replace traditional ultra-small capacitors.

[0066] In the present application, the capacitance of the entire semiconductor structure can be expanded by connecting a plurality of upper and lower semiconductor units (capacitors) in series.

[0067] Figure 6A-6H The cross-sectional view of the semiconductor structure manufacturing method is shown in FIG. Fig. 6A , providing a substrate 12, which has a first side 12a and a second side 12b opposite to the first side 12a. A plurality of metal structures 16 are arranged in the substrate 12, and the metal structures 16 extend from the first side 12a of the substrate 12 to the second side 12b, and can be pre-arranged in the substrate 12 by, for example, a silicon through-hole process. A back-end process layer 14 is arranged on the first side 12a of the substrate 12. The back-end process layer 14 includes a plurality of metal layers 14a, and different layers of the metal layers 14a are connected by vias 14b filled with metal materials, and are electrically connected to the metal structures 16. A plurality of bumps 20 are arranged on the back-end process layer 14, and are electrically connected to the plurality of metal layers 14a.

[0068] Please refer to Figure 6B Then, the substrate 12 is placed on the backing 34 by means of glue 32. Figure 6BAs shown, the first side 12 a of the substrate and the backing 34 are bonded to each other via the adhesive 32 .

[0069] Please refer to Figure 6C Next, the second side 12b of the substrate 12 is subjected to chemical mechanical polishing until the metal structure 16 is exposed. The metal structure 16 is called a front wafer through silicon via.

[0070] Please refer to Fig.6D Then, a patterned photoresist layer 36 is formed on the second side 12 b of the substrate 12 .

[0071] like Fig. 6E As shown, the substrate 12 is etched with the patterned photoresist layer 36 as a mask to form a plurality of vias 38, and the patterned photoresist layer 36 is removed. The vias 38 are disposed in the substrate 12, extending from the second side 12b of the substrate 12 toward the first side 12a, and are disposed corresponding to the metal structure 16.

[0072] like Fig. 6F As shown, metal material 40 is filled into the lead hole 38 to form a plurality of metal structures 18. In this example, the metal structure 18 is called a rear wafer surface silicon via. The corresponding arrangement of the metal structure 16 and the metal structure 18 is that one metal structure 16 corresponds to one metal structure 18. That is, one front wafer surface silicon via corresponds to one rear wafer surface silicon via.

[0073] like Figure 6G As shown, a plurality of bumps 22 are disposed on the metal structure 16. A redistribution layer 24 is disposed on the second side 12b of the substrate 12, covering the metal structure 16 and the metal structure 18, and exposing the bumps 22.

[0074] like Figure 6H As shown, the substrate 34 is removed to complete the fabrication of the semiconductor structure 10, wherein one of the metal structures 16, one of the metal structures 18, and a portion 26 of the substrate 12 located between the metal structures 16 and 18 form a single group of MIM capacitors 28, such as embedded MIM capacitors.

[0075] The present application uses silicon via technology to make an embedded capacitor structure in a wafer. This structure uses two silicon via processes to form silicon vias on the front wafer surface and silicon vias on the rear wafer surface. The silicon vias on the front wafer surface and the silicon vias on the rear wafer surface can be used as upper and lower electrodes of a silicon capacitor, respectively, and form a vertical embedded capacitor with a substrate sandwiched between the two. This process step can be completed together in the stacking process of a three-dimensional IC, which can save process steps and costs. Specifically, this process only needs to perform an additional silicon via process on the rear wafer surface after performing a traditional silicon via process (after forming silicon vias on the front wafer surface), and then continue to perform subsequent stacking processes to form silicon vias on the rear wafer surface, so that silicon vias on the front wafer surface and silicon vias on the rear wafer surface can be formed as upper and lower electrodes of the embedded capacitor. In addition, since the rear wafer surface generally only has silicon vias turned on, and no other routing is arranged, its wiring is simple. Compared with making silicon vias from the front wafer surface, due to the complex wiring of the front wafer surface, it will be necessary to add an additional copper layer, resulting in the complexity of the circuit. In addition, the process of the present application can easily produce a conductive structure in which multiple semiconductor units (chips) are stacked on each other, thereby greatly increasing the storage space of the capacitor.

[0076] The components of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present invention, and can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments of this document, and understand that such equivalent structures do not deviate from the spirit and scope of the embodiments of the present invention, and can make various changes, substitutions and adjustments.

Claims

1. A semiconductor structure, characterized in that: include: A substrate having a first side and a second side, the second side being opposite to the first side; A back-end process layer is disposed on the first side of the substrate; A plurality of first metal structures extending through the substrate; as well as A plurality of second metal structures are disposed in the substrate, extending from the second side of the substrate toward the first side, and are disposed corresponding to the plurality of first metal structures.

2. The semiconductor structure according to claim 1, wherein: The first metal structures and the second metal structures include copper.

3. The semiconductor structure according to claim 1, wherein: The plurality of first metal structures and the plurality of second metal structures include columnar structures.

4. The semiconductor structure according to claim 3, characterized in that One of the first metal structures corresponds to one of the second metal structures.

5. The semiconductor structure according to claim 3, wherein: The plurality of first metal structures form a matrix, and the plurality of second metal structures are disposed on both sides of the matrix.

6. The semiconductor structure according to claim 1, wherein: The plurality of first metal structures include columnar structures, and the plurality of second metal structures include rectangular structures.

7. The semiconductor structure according to claim 6, wherein: A plurality of the first metal structures corresponds to one of the second metal structures.

8. The semiconductor structure according to claim 1, wherein: It further includes a plurality of first bumps disposed on the back-end process layer.

9. The semiconductor structure according to claim 1, wherein: It further includes a plurality of second bumps disposed on the plurality of first metal structures.

10. The semiconductor structure according to claim 9, wherein: The invention further comprises a redistribution layer, which is disposed on the second side of the substrate, covers the plurality of first metal structures and the plurality of second metal structures, and exposes the plurality of second bumps.

11. The semiconductor structure according to claim 1, wherein: One of the plurality of first metal structures, one of the plurality of second metal structures, and a partial area of ​​the substrate located between the first metal structure and the second metal structure form a metal-insulator-metal capacitor.

12. A semiconductor structure, characterized in that: include: A first semiconductor unit, comprising: A first substrate having a first side and a second side, the second side being opposite to the first side; A first back-end process layer is disposed on the first side of the first substrate; A plurality of first metal structures extending through the first substrate; and a plurality of second metal structures disposed in the first substrate, extending from the second side of the first substrate toward the first side, and disposed corresponding to the plurality of first metal structures; and a second semiconductor unit, electrically connected to the first semiconductor unit, the second semiconductor unit comprising: a second substrate having a first side and a second side, the second side being opposite to the first side; A second back-end process layer is disposed on the first side of the second substrate; A plurality of third metal structures extending through the second substrate; and A plurality of fourth metal structures are disposed in the second substrate, extending from the second side of the second substrate toward the first side, and are disposed corresponding to the plurality of third metal structures.

13. The semiconductor structure according to claim 12, wherein: The plurality of first metal structures of the first semiconductor unit are electrically connected to the plurality of third metal structures of the second semiconductor unit.

14. The semiconductor structure according to claim 12, wherein: One of the plurality of first metal structures, one of the plurality of second metal structures, and a partial area of ​​the first substrate located between the first metal structure and the second metal structure form a metal-insulator-metal capacitor.

15. The semiconductor structure according to claim 12, wherein: One of the third metal structures, one of the fourth metal structures, and a portion of the second substrate located between the third metal structure and the fourth metal structure form a metal-insulator-metal capacitor.

16. A method for manufacturing a semiconductor structure, characterized in that: include: A substrate is provided, on which a base plate is disposed, the base plate having a first side and a second side, the second side being opposite to the first side, wherein a back-end process layer is disposed on the first side of the base plate, and a plurality of first metal structures penetrate the base plate; Disposing a plurality of lead holes in the substrate, the plurality of lead holes extending from the second side of the substrate toward the first side and being disposed corresponding to the plurality of first metal structures; as well as Filling metal into the plurality of lead holes to form a plurality of second metal structures.

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