Using tile sizing to improve computational resource utilization in physical layout verification and DRC

Abstract

A computing system that can parse a physical verification file to identify physical verification operations to be performed on a layout design describing an integrated circuit. The computing system can divide input data corresponding to the layout design into a plurality of data tiles of non-uniform size, associate the data tiles with processing tasks that are processed in parallel by processing cores of the computing system, and assign the processing tasks to the processing cores based on the size of the data tiles. The computing system can assign processing tasks associated with data tiles having larger relative sizes to the processing cores before assigning processing tasks associated with data tiles having smaller relative sizes to the processing cores. The computing system can assign processing tasks independently of the content of the data tiles. The processing cores can process the processing tasks in parallel to perform the physical verification operations described in the physical verification file.

Description

Technical Field

[0001] The present application relates generally to electronic design automation and, more particularly, to facilitating computing resource utilization with tile sizing. Background Art

[0002] In the design flow of manufacturing integrated circuits, the physical design of the integrated circuit can describe specific geometric elements, which is generally called the layout design. These geometric elements are usually polygons that define the shapes that will be created in various materials to manufacture the integrated circuit. Typically, the designer will select groups of geometric elements that represent circuit device components (e.g., contacts, gates, etc.) and place them in the design area. These groups of geometric elements can be custom designed, selected from a previously created design library, or a combination of both. Once the groups of geometric elements representing circuit device components are placed, geometric elements representing connecting lines will be placed between these geometric elements according to predetermined paths. These lines will form the wiring for interconnecting electronic devices.

[0003] Descriptions of the physical design of integrated circuits can be provided in a number of different formats. The Graphic Data System II (GDSII) format is a popular format for transmitting and archiving two-dimensional (2D) graphical circuit layout data. Among other features, it can include a hierarchy of structures, each of which includes layout elements (e.g., polygons, paths or multiple lines, circles, and text boxes). Other formats include an open source format called Open Access, Milkyway, EDDM, and the Open Artwork System Interchange Standard (OASIS). These various industry formats are used to define geometric information in a physical design or layout design used to manufacture an integrated circuit. Once the design is complete, the layout portion of the physical design can be used by a manufacturing tool to manufacture the circuit using a photolithography process.

[0004] Before manufacturing, the physical design and the mask design built based on the physical design can be analyzed by various physical verification processes. For these physical verification processes, the physical design can be divided into uniformly sized areas to allow them to be interchangeably used by multiple different processing cores in the computing device that implements the physical verification process. These areas can be arrays of rectangular or square areas. Alternatively, these areas can include different shapes. The size can be a few microns or tens of microns. These areas or computing units can be called tiles or windows. In fact, the number of tiles may reach hundreds of thousands or even millions.

[0005] While partitioning of the physical design allows a computing device to perform parallel processing based on tiles of interchangeable sizes, the processing time for each tile typically varies based on the geometric pattern data within the tile. Scheduling tile processing across the processing cores of a computing device with unknown processing times can result in an unbalanced processing load and inefficient resource utilization. This trend toward inefficient resource utilization increases significantly as the number of processing cores reserved for the physical verification process increases. Attempting content-based tile scheduling to more effectively balance the processing load across processing cores is often impractical because predicting the time it will take a processing core to process a given tile has proven difficult and will typically consume more processing time and resources than is saved. Summary of the invention

[0006] The present application discloses a computing system that can parse a physical verification file to identify physical verification operations to be performed on a layout design describing an integrated circuit. The computing system can divide the input data corresponding to the layout design into a plurality of data tiles of non-uniform size, associate the data tiles with processing tasks to be processed in parallel by the processing cores of the computing system, and assign the processing tasks to the processing cores according to the size of the data tiles. The computing system can assign processing tasks associated with data tiles of larger relative size to the processing cores, and then assign processing tasks associated with data tiles of smaller relative size to the processing cores. The computing system can assign processing tasks independently of the content of the data tiles. The processing cores can process processing tasks in parallel to perform the physical verification operations described in the physical verification file. The embodiments will be described in more detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 and Figure 2 An example of a computer system that can be used to implement various embodiments is shown.

[0008] Figure 3 An example of a physical verification system with parallel processing based on tile sizing of computing resource utilization that can be implemented according to various embodiments is shown.

[0009] Figure 4 An exemplary flow diagram of parallel processing with tile-sizing based computing resource utilization that may be implemented in accordance with various embodiments is shown.

[0010] Figure 5 An example of non-uniformly partitioning a design scope into multiple layout design tiles that can be implemented according to various embodiments is shown.

[0011] Figure 6 Examples of parallel processing based on tile sizing of computing resource utilization that can be implemented according to various examples are shown. DETAILED DESCRIPTION

[0012] Illustrative operating environment

[0013] Various examples may be implemented by executing software instructions by a computing device 101 (e.g., a programmable computer). Figure 1 An illustrative example of a computing device 101 is shown. As shown, computing device 101 includes a computing unit 103 having a processor unit 105 and a system memory 107. Processor unit 105 can be any type of programmable electronic device for executing software instructions, but is typically a microprocessor. System memory 107 can include read-only memory (ROM) 109 and random access memory (RAM) 111. As will be appreciated by one of ordinary skill in the art, both read-only memory (ROM) 109 and random access memory (RAM) 111 can store software instructions that are executed by processor unit 105.

[0014] The processor unit 105 and the system memory 107 are directly or indirectly connected to one or more peripheral devices 115-123 via the bus 113 or an alternative communication structure. For example, the processor unit 105 or the system memory 107 can be directly or indirectly connected to one or more additional storage devices, such as a hard drive 117 (which can be magnetic and / or removable), a removable optical drive 119, and / or a flash memory card. The processor unit 105 and the system memory 107 can also be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input device 121 can include, for example, a keyboard, a pointing device (such as a mouse, a touchpad, a stylus, a trackball, or a joystick), a scanner, a camera, and a microphone. The output device 123 can include, for example, a display, a printer, and a speaker. In various examples of computing devices 101, one or more peripheral devices 115-123 can be installed internally in the computing unit 103. Alternatively, one or more peripheral devices 115-123 can be located outside the housing of the computing unit 103 and connected to the bus 113 via, for example, a universal serial bus (USB) connection.

[0015] In some implementations, the computing unit 103 may be directly or indirectly connected to a network interface 115 for communicating with other devices that make up the network. The network interface 115 may convert data and control signals from the computing unit 103 into network messages according to one or more communication protocols (e.g., the Transmission Control Protocol (TCP) and the Internet Protocol (IP)). In addition, the network interface 115 may be connected to the network using any suitable connection agent (or combination of agents), including, for example, a wireless transceiver, a modem, or an Ethernet connection. These network interfaces and protocols are well known in the art and are therefore not discussed in detail herein.

[0016] It should be understood that computing device 101 is described by way of example only and is not intended to be limiting. Various embodiments may use a device including Figure 1 The components of computing device 101 shown in FIG. 1 may be implemented by one or more computing devices, which computing devices only include Figure 1 A subset of the components shown in, or an alternative combination of components, including Figure 1 For example, various embodiments may be implemented using a multi-processor computer, multiple single-processor and / or multi-processor computers arranged in a network, or some combination of the two.

[0017] In some implementations, processor unit 105 may have multiple processor cores. Figure 2 An example of a multi-core processor unit 105 that can be used for various embodiments is shown. As shown, the processor unit 105 includes multiple processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B and a memory cache (cache) 205A and 205B respectively. As those of ordinary skill in the art will appreciate, computing engines 203A and 203B may include logic devices for performing various computing functions, such as obtaining software instructions and then performing the operations specified in the instructions obtained. These operations may include, for example, adding, subtracting, multiplying and comparing numbers to perform logical operations (such as AND, OR, NOR and XOR) and retrieving data. Then each computing engine 203A and 203B can use its corresponding memory cache 205A and 205B to quickly store and retrieve data and / or instructions for execution.

[0018] Each processor core 201A and 201B is connected to an interconnect 207. The specific configuration of the interconnect 207 may vary depending on the architecture of the processor unit 105. For some processor cores 201A and 201B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation, and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. For other processor units 201A and 201B, such as the Opteron 500 from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as an interconnect bus. TM and Athlon TMIn a dual-core processor, interconnect 207 may be implemented as a system request interface device. In any case, processor cores 201A and 201B communicate with input / output interface 209 and memory controller 210 via interconnect 207. Input / output interface 209 provides a communication interface to bus 113. Similarly, memory controller 210 controls the exchange of information in system memory 107. In some implementations, processor unit 105 may include additional components, such as a high-level cache memory that can be shared by processor cores 201A and 201B. It should also be understood that Figure 1 and Figure 2 The computer network descriptions shown in are provided by way of example only and are not intended to imply any limitation as to the scope of use or functionality of alternative embodiments.

[0019] Using tile sizing to improve computing resource utilization

[0020] Figure 3 An example of a physical verification system with parallel processing based on tile sizing of computing resource utilization that can be implemented according to various embodiments is shown. Figure 4 An exemplary flow chart of parallel processing with tile-sizing-based computing resource utilization that can be implemented according to various embodiments is shown. Figure 3 and Figure 4 , a physical verification system 300 may receive a layout design 301 describing an electronic system (e.g., an integrated circuit). The layout design 301 may define geometric information that can be used to manufacture the integrated circuit, which may be specified in a Graphic Data System II (GDSII) format, an Open Access format, a Milkyway format, an EDDM format, an Open Artwork System Interchange Standard (OASIS) format, etc. The physical verification system 300 may also receive a physical verification file 302 that describes a physical verification operation to be performed on the layout design 301, such as specified in a standard verification rule format (SVRF), etc. In some embodiments, the physical verification file 302 may identify at least a portion of the layout design 301 (sometimes referred to as a design scope) to be subjected to a physical verification operation, and identify outputs to be generated by the physical verification operation.

[0021] Physical verification system 300 may include pre-processing system 310 to identify input data, such as input data corresponding to layout design 301, to be processed in parallel by a computing system, such as implementing physical verification operations of physical verification tool 330. Pre-processing system 310 may include parsing system 312 to Figure 4In block 401 of the present invention, parsing system 312 may parse physical verification file 302 to identify a physical verification operation to be performed on layout design 301 describing an electronic device. In some embodiments, physical verification file 302 may describe input data utilized by the physical verification operation, the type of physical verification operation performed on the input data, and output generated by the physical verification operation based on the input data.

[0022] The pre-processing system 310 may include a design input system 314, Figure 4 In block 402, design input system 314 may identify at least a portion of layout design 301 to be subjected to a physical verification operation based on physical verification file 302. In some embodiments, design input system 314 may determine input data from parsed physical verification file 302 and identify the portion of layout design 301 corresponding to the input data. Physical verification tool 330 may be configured to perform a physical verification operation on the portion of layout design 301 based on the physical verification operation parsed from physical verification file 302.

[0023] The physical verification system 300 may include a parallel task allocation system 320 to control a parallel processing-based implementation of physical verification operations performed by a physical verification tool 330 using the portion of the layout design 301 corresponding to the input data in the physical verification file 302. The physical verification tool 330 is composed of a computing system (e.g., Figure 1 The computing device 101 in the embodiment can receive tasks assigned by the parallel task assignment system 320, and process the assigned tasks 321 in parallel to implement the physical verification operation described in the physical verification file 302.

[0024] The parallel task allocation system 320 may include a non-uniform tile partitioning system 322. Figure 4 In block 403 of FIG. 4 , non-uniform tile partitioning system 322 may partition the identified portion of layout design 301 into a plurality of layout design tiles having non-uniform sizes. Non-uniform tile partitioning system 322 may partition layout design 301 into layout design tiles having different areas and / or different shapes. In some embodiments, the partitioning or partitioning of layout design 301 by non-uniform tile partitioning system 322 may be performed independently of the content of layout design 301, such as independent of the geometric information within layout design 301. Figure 5 Embodiments of non-uniformly partitioning a design scope into a plurality of layout design tiles are described in more detail.

[0025] Figure 5 An example of non-uniformly dividing the design scope 500 into a plurality of layout design tiles 511-514 that can be implemented according to various embodiments is shown. Figure 5, the design scope 500 may correspond to at least a portion of a physical layout design describing an integrated circuit, which may include geometric information corresponding to the structure of the integrated circuit. In this example, the design scope 500 may be divided into a plurality of portions or tiles having non-uniform sizes (e.g., different areas and / or shapes). Figure 5 The tiles are shown adjacent to each other and not overlapping, but in some embodiments, the tiles may at least partially overlap.

[0026] A representative set of non-uniformly sized tiles 510 within the design scope 500 may include layout design tiles 511-514. Layout design tiles 511-514 may have different sizes, for example, layout design tile 511 is larger than layout design tiles 512-513, and layout design tiles 512 and 513 are larger than layout design tile 514. Each of layout design tiles 511-514 may include a portion of the design scope 500, which may include geometric information corresponding to the integrated circuit structure. In some embodiments, the amount and density of geometric information included in the layout design tiles 511-514 may be related to the processing time of the processing core to process the layout design tiles 511-514. Although Figure 5 A particular non-uniform size division of the design scope 500 is shown, but other embodiments may divide the design scope 500 into different non-uniform sizes (e.g., different areas and / or different shapes). For example, Figure 5 The particular non-uniform partitioning of the design scope 500 shown in does not affect the overall number of tiles, although it increases and decreases the size of the tiles compared to the uniformly sized tile approach. In the example of a non-uniform partitioning of the design scope that changes the number of tiles, such as reducing the size of the tiles, it may be at the expense of some other type of overhead that is typically related to the number of tiles to be processed.

[0027] Back to Figure 3 and Figure 4 , the parallel task allocation system 320 may include a size-based task scheduler 324, Figure 4 In block 404 of the embodiment, the size-based task scheduler 324 may associate the layout design tile with a processing task of a processing core in the computing system that implements the physical verification operation. In some embodiments, each layout design tile identified by the non-uniform tile partitioning system 322 may correspond to a separate processing task that can be processed by a processing core in the computing system. The processing task of the layout design tile may correspond to a portion of the physical verification operation described in the physical verification file 302.

[0028] exist Figure 4In block 405 of , the size-based task scheduler 324 may assign processing tasks to processing cores based on the size of the layout design tiles associated with the processing tasks. The size of the layout design tiles may correspond to the area of ​​the layout design tiles relative to the layout design 301. The size-based task scheduler 324 may sort the processing tasks based on the size of the data tiles associated with the processing tasks, and in some embodiments, may assign sorted processing tasks associated with layout design tiles of larger sizes before assigning sorted processing tasks associated with layout design tiles of smaller sizes. By calculating processing tasks corresponding to layout design tiles of larger sizes before processing tasks corresponding to layout design tiles of smaller sizes, the parallel task assignment system 320 may avoid delaying processing time-intensive tasks until the end of the parallel processing window and idling the processing cores when the last tasks complete processing. The size-based task scheduler 324 may provide the assigned tasks 321 to the physical verification tool 330, which, when executed by a processing core of a computing system implementing the physical verification tool 330, may perform physical verification operations described in the physical verification file 302. Reference will be made to the following. Figure 6 Embodiments of parallel processing for computing resource utilization based on task sizing are described in more detail.

[0029] Figure 6 Examples of parallel processing based on tile sizing of computing resource utilization that can be implemented according to various examples are shown. Figure 6 , a computing system having a plurality of processing cores 600-1 to 600-6 may allocate processing tasks, such as allocated task 620, based on the size of the tiles associated with the processing tasks. In some embodiments, a tile partitioning system implemented by the computing system may partition input data into tiles having non-uniform sizes, and a scheduler implemented by the computing system may prioritize processing tasks associated with tiles of larger sizes over processing tasks associated with tiles of smaller sizes, allocating processing tasks associated with tiles of larger sizes to processing cores 600-1 to 600-6.

[0030] The parallel processing of the assigned tasks 420 by the processing cores 600-1 to 600-6 may occur relative to the processing time 610, e.g., starting at a starting point 611 and ending at a synchronization point 612. The processing cores 600-1 to 600-6 may begin processing their respective assigned tasks 620 at the starting point 611. After the processing core completes processing one assigned task 420, the processing core may begin processing another task assigned by the scheduler. The processing cores 600-1 to 600-6 may continue to process the assigned tasks 420 until all assigned tasks 420 are completed by the processing cores 600-1 to 600-6, e.g., at a synchronization point 612. Since the size of the tile may be related to the processing time of the processing tasks associated with the tile, the order in which the processing tasks are assigned to the processing cores 600-1 to 600-6 may increase the likelihood that processing tasks with longer processing times will be assigned early in the parallel processing window (between the starting point 611 and the synchronization point 612). By completing processing tasks with longer processing times early in the parallel processing window, the scheduler can more effectively keep processing cores 600-1 through 600-6 active by assigning processing tasks with shorter processing times later in the parallel processing window.

[0031] Back to Figure 3 and Figure 4 , the physical verification tool 330 may perform physical verification operations on the layout design 301 by causing a processing core of a computing system implementing the physical verification tool 330 to process the assigned task 321. In some embodiments, the physical verification tool 330 may include one or more of a design rule checking system, an optical proximity correction system, a fill generation system, a parasitic extraction system, etc. For example, the design rule checking system may analyze the layout design 301 to determine whether the circuits in the layout design 301 comply with the design rules of a manufacturing plant capable of manufacturing the integrated circuit described by the layout design 301.

[0032] The optical proximity correction system may predict a printed image on a substrate produced by radiation or light exposure through one or more masks described by the mask layout design developed by layout design 301. Optical proximity correction tool 320 may compare the prediction of the printed image to a target image of an integrated circuit (e.g., as described in layout design 301 of the integrated circuit) and modify the mask layout design, such as by adjusting the mask design layout to change the amplitude of radiation or light transmitted by the masks generated by the mask design layout and increase the overall pattern fidelity printed on the integrated circuit.

[0033] The fill generation system may identify empty areas in layout design 301 and modify layout design 301 to fill the empty areas with data representing "dummy" or "fill" geometric elements, which may increase the density of structures to be formed in the layers of layout design 301. The parasitic extraction system may extract nets from layout design 301, identify parasitic values ​​in each extracted net, and generate an electrical representation of each extracted net based on the parasitic values. The parasitic values ​​may include resistance in the net, capacitance between the net and a ground plane having a corresponding ground voltage, coupling capacitance between adjacent nets, inductance, and the like.

[0034] The above-described systems and apparatus may use a dedicated processor system, a microcontroller, a programmable logic device, a microprocessor, or any combination thereof to perform some or all of the operations described herein. Some operations described herein may be implemented in software, and other operations may be implemented in hardware. Any operations, processes, and methods described herein may be performed by an apparatus, device, and / or system substantially similar to those described herein and with reference to the illustrated drawings.

[0035] The processing device may execute instructions or "code" stored in the memory. The memory may also store data. The processing device may include, but is not limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a network system locally or remotely via wireless transmission.

[0036] The processor memory can be integrated with the processing device, such as RAM or FLASH memory integrated in an integrated circuit microprocessor. In other examples, the memory may include independent devices, such as external disk drives, storage arrays, portable FLASH keychains, etc. The memory and the processing device can be operatively coupled together or communicate with each other through I / O ports, network connections, etc., and the processing device can read files stored on the memory. The relevant memory can be "read-only" (ROM) or not by design through permission settings. Other memory examples may include, but are not limited to, WORM, EPROM, EEPROM, FLASH, etc., which can be implemented in solid-state semiconductor devices. Other memories may include moving parts, such as known rotating disk drives. All of these memories can be "machine-readable" and can be read by the processing device.

[0037] The operating instructions or commands can be implemented or embodied in a tangible form of stored computer software (also called "computer program" or "code"). The program or code can be stored in a digital memory and read by a processing device. "Computer-readable storage media" (or "machine-readable storage media") can include all of the above types of memory, as well as future new technologies, as long as these memories can store digital information in the nature of computer programs or other data, at least temporarily, and the stored information can be "read" by appropriate processing devices. The term "computer-readable" is not limited to the "computer" used historically, that is, a complete mainframe, minicomputer, desktop or even laptop computer. On the contrary, "computer-readable" can include storage media that can be read by a processor, a processing device or any computing system. These media can be any available media that can be accessed locally and / or remotely by a computer or processor, including volatile and non-volatile media, as well as removable and non-removable media, or any combination thereof.

[0038] A program stored in a computer-readable storage medium may constitute a computer program product. For example, a storage medium may be used as a convenient means for storing or transmitting a computer program. For convenience, operations may be described as various interconnected or coupled functional blocks or schematic diagrams. However, in some cases, these functional blocks or schematic diagrams may be equivalently aggregated into a single logical device, program, or operation in a manner that does not clearly define boundaries.

[0039] in conclusion

[0040] Although the present application describes specific examples of implementing embodiments of the present invention, those skilled in the art will appreciate that numerous variations and permutations of the above systems and techniques fall within the spirit and scope of the present invention as set forth in the appended claims. For example, although specific terms are used above to refer to design processes, it should be understood that various examples of the present invention may be implemented using any desired combination of electronic design automation processes.

[0041] Those skilled in the art will also recognize that the concepts taught herein can be customized for specific applications in many other ways. In particular, those skilled in the art will recognize that the illustrated example is only one of many alternative implementations that will become apparent after reading this disclosure.

[0042] Although the specification may refer to "one", "another" or "some" examples in various places, this does not necessarily mean that each such reference is to the same example or examples, or that the feature applies to only a single example.

Claims

1. A method comprising: dividing, by a computing system, input data for processing by the computing system into a plurality of data tiles of non-uniform size; associating, by the computing system, the data tiles with processing tasks processed in parallel by processing cores of the computing system; as well as The processing tasks are assigned, by the computing system, to the processing cores based at least in part on a size of the data tile.

2. The method according to claim 1, wherein: Allocating, by the computing system, the processing tasks to the processing cores based at least in part on the size of the data tiles further comprises: sorting the processing tasks based on sizes of the data tiles associated with the processing tasks; and Processing tasks associated with data tiles having larger relative sizes are assigned to the processing cores based on the ordering before processing tasks associated with data tiles having smaller relative sizes are assigned to the processing cores.

3. The method according to claim 1, further comprising: A physical verification file is parsed by the computing system to identify physical verification operations to be performed on a layout design describing an integrated circuit, wherein the computing system is configured to perform the physical verification operations in parallel using the processing cores, and wherein the layout design is the input data.

4. The method according to claim 3, further comprising: At least a portion of the layout design to be subjected to the physical verification operation is identified by the computing system based on the physical verification file.

5. The method according to claim 3, wherein: Dividing the input data into a plurality of non-uniform data tiles further includes partitioning the layout design describing the integrated circuit into a plurality of portions of the layout design having different sizes.

6. The method according to claim 3, wherein: The processing cores in the computing system are configured to process the processing tasks in parallel to perform the physical verification operations described in the physical verification file.

7. The method according to claim 1, wherein: The allocation of the processing tasks to the processing cores is performed independently of the content of the data tiles.

8. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising: dividing input data for processing by the computing system into a plurality of data tiles of non-uniform size; associating the data tiles with processing tasks processed in parallel by processing cores of the computing system; as well as The processing tasks are assigned to the processing cores based at least in part on the size of the data tiles.

9. The device according to claim 8, wherein: The instructions are configured to cause the one or more processing devices to perform the operations further comprising: allocating the processing tasks to the processing cores based at least in part on the size of the data tiles by: sorting the processing tasks based on sizes of the data tiles associated with the processing tasks; and Processing tasks associated with data tiles having larger relative sizes are assigned to the processing cores based on the ordering before processing tasks associated with data tiles having smaller relative sizes are assigned to the processing cores.

10. The device according to claim 8, wherein: The operations that the instructions are configured to cause the one or more processing devices to perform also include parsing a physical verification file to identify physical verification operations to be performed on a layout design describing an integrated circuit, wherein the computing system is configured to perform the physical verification operations in parallel using the processing cores, and wherein the layout design is the input data.

11. The device according to claim 10, wherein: The instructions are configured to cause the one or more processing devices to perform the operations further comprising identifying at least a portion of the layout design to be subjected to the physical verification operation based on the physical verification file.

12. The device according to claim 10, wherein: Dividing the input data into a plurality of non-uniform data tiles further includes partitioning the layout design describing the integrated circuit into a plurality of portions of the layout design having different sizes.

13. The device according to claim 10, wherein: The processing cores in the computing system are configured to process the processing tasks in parallel to perform the physical verification operations described in the physical verification file.

14. The device according to claim 8, wherein: The allocation of the processing tasks to the processing cores is performed independently of the content of the data tiles.

15. A system comprising: a memory system configured to store computer-executable instructions; and A computing system, which in response to execution of the computer-executable instructions is configured to: dividing input data for processing by the computing system into a plurality of data tiles of non-uniform size; associating the data tiles with processing tasks processed in parallel by processing cores of the computing system; as well as The processing tasks are assigned to the processing cores based at least in part on the size of the data tiles.

16. The system of claim 15, wherein: The computing system, in response to execution of the computer-executable instructions, is further configured to: allocate the processing tasks to the processing cores based at least in part on the size of the data tiles by: sorting the processing tasks based on sizes of the data tiles associated with the processing tasks; as well as Processing tasks associated with data tiles having larger relative sizes are assigned to the processing cores based on the ordering before processing tasks associated with data tiles having smaller relative sizes are assigned to the processing cores.

17. The system of claim 15, wherein: The computing system is further configured, in response to execution of the computer-executable instructions, to parse a physical verification file to identify physical verification operations to be performed on a layout design describing an integrated circuit, wherein the computing system is configured to perform the physical verification operations in parallel using the processing cores, and wherein the layout design is the input data.

18. The system of claim 17, wherein: The computing system, responsive to execution of the computer-executable instructions, is further configured to: identify at least a portion of the layout design to be subjected to the physical verification operation based on the physical verification file.

19. The system of claim 17, wherein: The computing system, responsive to execution of the computer-executable instructions, is further configured to partition the input data into a plurality of non-uniform data tiles by partitioning the layout design describing the integrated circuit into a plurality of portions of the layout design having different sizes.

20. The system of claim 17, wherein: The processing cores in the computing system are configured to process the processing tasks in parallel to perform the physical verification operations described in the physical verification file, and wherein the allocation of the processing tasks to the processing cores is performed independently of the content of the data tiles.

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