Semiconductor device and memory device

Abstract

According to one embodiment, a semiconductor device includes: an operational amplifier having a first input terminal, a second input terminal, and an output terminal and outputting a first voltage from the output terminal; a first resistor having one end connected to the first input terminal and the other end connected to the output terminal; a plurality of second resistors connected in series and having one end connected to the first input terminal; a plurality of switches each having one end connected to a first node between two adjacent resistors of the plurality of second resistors and the other end connected to a second node, and receiving a digital code; and a current source circuit that is connected between the second node and a third node, one of the plurality of switches is turned on on the basis of the digital code, and the current source circuit causes a first current to flow from a part or all of the plurality of second resistors to the third node via the one switch in the turned-on state.

Description

Technical Field

[0001] Embodiments relate to a semiconductor device and a memory device. Background Art

[0002] Digital-to-analog conversion circuits and analog-to-digital conversion circuits are used in various semiconductor devices.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2002-76897 Summary of the invention

[0006] A semiconductor device of an embodiment includes: an operational amplifier having a first input terminal, a second input terminal and an output terminal, and outputting a first voltage from the output terminal; a first resistor having one end connected to the first input terminal and the other end connected to the output terminal; a plurality of second resistors having one end connected to the first input terminal and connected in series; a plurality of switches, each having one end connected to a first node between two adjacent resistors of the plurality of second resistors and the other end connected to a second node, and receiving a digital code; and a current source circuit, the current source circuit being connected between the second node and a third node, one of the plurality of switches being turned on based on the digital code, and the current source circuit causing a first current to flow from a part or all of the plurality of second resistors to the third node via the one switch in the turned-on state. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing a configuration example of a semiconductor device according to the first embodiment.

[0008] Figure 2 This is a circuit diagram showing a configuration example of a memory cell array of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a cross-sectional view showing a structural example of the semiconductor device according to the first embodiment.

[0010] Figure 4 This is a plan view showing a structural example of a memory cell of the semiconductor device according to the first embodiment.

[0011] Figure 5 This is a diagram for explaining the relationship between the threshold voltage of a memory cell and data.

[0012] Figure 6This is a schematic diagram showing a configuration example of a digital-analog conversion circuit and a drive circuit of the semiconductor device according to the first embodiment.

[0013] Figure 7 This is a circuit diagram showing a configuration example of a digital-analog conversion circuit and a drive circuit of the semiconductor device according to the first embodiment.

[0014] Figure 8 This is a circuit diagram showing a configuration example of a certain circuit in the semiconductor device according to the first embodiment.

[0015] Fig. 9 This is a circuit diagram showing a configuration example of a certain circuit in the semiconductor device according to the first embodiment.

[0016] Fig.10 This is a circuit diagram showing a configuration example of a certain circuit in the semiconductor device according to the first embodiment.

[0017] Fig.11 It is a diagram for explaining an operation example of the semiconductor device according to the first embodiment.

[0018] Fig.12 This is a circuit diagram showing a configuration example of a digital-analog conversion circuit and a drive circuit of a semiconductor device according to a second embodiment.

[0019] Fig.13 This is a circuit diagram showing a configuration example of a digital-analog conversion circuit and a drive circuit of a semiconductor device according to a third embodiment.

[0020] Fig.14 This is a circuit diagram showing a configuration example of a digital-analog conversion circuit and a drive circuit of a semiconductor device according to a fourth embodiment.

[0021] Fig.15 This is a circuit diagram showing a configuration example of a certain circuit of a semiconductor device according to a fourth embodiment.

[0022] Fig.16 This is a block diagram showing a configuration example of a semiconductor device according to a fifth embodiment.

[0023] Fig.17 This is a block diagram showing a configuration example of a semiconductor device according to a sixth embodiment.

[0024] Fig.18 This is a block diagram showing a configuration example of a semiconductor device according to the seventh embodiment. DETAILED DESCRIPTION

[0025] Reference Figures 1 to 18 , a semiconductor device according to an embodiment of the present invention is described.

[0026] (1) First Embodiment

[0027] Reference Figures 1 to 11 , a semiconductor device according to a first embodiment is described.

[0028] (a) Example of composition

[0029] <Overall composition>

[0030] Reference Figures 1 to 3 , the overall structure of the semiconductor device according to the first embodiment is described.

[0031] Figure 1 1 is a block diagram for explaining a configuration example of a system SYS including the semiconductor device 1 according to the present embodiment.

[0032] like Figure 1 As shown, the semiconductor device 1 of the present embodiment is a storage device 1 .

[0033] The storage device 1 is arranged in the storage system SYS.

[0034] The memory system SYS is connected to the host device 9 via a host bus. The host device 9 can request the memory system SYS to write data, read data, and erase data.

[0035] The host device 9 is, for example, a personal computer or a server. The host bus is, for example, a bus based on an interface standard such as an SD (registered trademark) interface, SAS (Serial attached SCSI (small computer system interface)), SATA (Serial ATA (advanced technology attachment)), PCIe (Peripheral component interconnect express) or NVMe (Non-volatile memory express). In addition, the storage system SYS can also be connected to the host device 9 via wireless communication.

[0036] The storage system SYS includes a storage device 1 and a storage controller 5 according to the present embodiment.

[0037] The memory controller 5 is electrically coupled to the memory device 1. The memory controller 5 sends a command CMD, an address ADD, and a plurality of control signals to the memory device 1.

[0038] The storage device 1 is a nonvolatile semiconductor storage device. For example, the storage device 1 of the present embodiment is a NAND flash memory 1 .

[0039] The storage device 1 receives a command CMD, an address ADD, and a plurality of control signals. Data DT is transferred between the storage device 1 and the storage controller 5. Hereinafter, the data DT transferred from the storage controller 5 to the storage device 1 during a write sequence is referred to as write data. The write data DT is written into the storage device 1. The data DT transferred from the storage device 1 to the storage controller 5 during a read sequence is referred to as read data. The read data DT is read from the storage device 1.

[0040] The memory device 1 includes, for example, a memory cell array 110 , a command register 120 , an address register 130 , a row control circuit 140 , a sense amplifier circuit 150 , a voltage generation circuit 160 , a temperature sensor 170 , an input / output circuit 180 , and a sequencer 190 .

[0041] The memory cell array 110 stores data. In the memory cell array 110, a plurality of bit lines and a plurality of word lines are provided. The memory cell array 110 includes a plurality of blocks BLK. Each block BLK is a collection of a plurality of memory cells. Each memory cell is associated with a bit line and a word line. The memory cell array 110 includes a plurality of selection gate lines for selecting control units in the memory cell array 110.

[0042] The internal structure of the memory cell array 110 will be described later.

[0043] The command register 120 temporarily stores the command CMD from the memory controller 5. The command CMD is a signal including a command for causing the sequencer 190 to execute a read sequence, a write sequence, an erase sequence, and the like, for example.

[0044] The address register 130 temporarily stores the address (selection address) ADD from the storage controller 5. The address ADD includes, for example, a block address, a page address (word line address), and a column address. For example, the block address, the page address, and the column address are used to select the block BLK, the word line, and the bit line (column), respectively. Hereinafter, the block selected based on the block address is referred to as a selected block. The word line selected based on the page address is referred to as a selected word line.

[0045] The row control circuit 140 controls the operation related to the row of the memory cell array 110. The row control circuit 140 selects a block BLK in the memory cell array 110 based on the block address. For example, the row control circuit 140 transfers the voltage applied to the wiring corresponding to the selected word line to the selected word line in the selected block BLK. The row control circuit 140 controls the selection and non-selection of the selection gate line based on the address ADD. The row control circuit 140 includes a word line switch and a row decoder, etc.

[0046] The sense amplifier circuit 150 controls the operation related to the column of the memory cell array 110. In the write sequence, the sense amplifier circuit 150 applies voltage to each bit line provided in the memory cell array 110 according to the write data DT from the memory controller 5. In the read sequence, the sense amplifier circuit 150 determines the data stored in the memory cell based on whether or not a current is generated or the change in the potential of the bit line. The sense amplifier circuit 150 transfers the data based on the determination result as read data to the memory controller 5. The sense amplifier circuit 150 includes a sense amplifier unit, a data latch circuit, a cache circuit, and the like.

[0047] The voltage generating circuit 160 generates a plurality of voltages for various operations of the storage device 1 in various operation sequences such as a read sequence, a write sequence, and an erase sequence. The voltage generating circuit 160 outputs the generated voltage to each circuit. The voltage generating circuit 160 can apply a predetermined voltage to wirings corresponding to word lines and bit lines based on the address ADD. The voltage generating circuit 160 includes, for example, a charge pump circuit 161, a drive circuit 162, and a digital-analog conversion circuit 163.

[0048] The input / output circuit 180 functions as an interface circuit on the storage device 1 side between the storage device 1 and the storage controller 5. When the storage device 1 is a NAND flash memory, the input / output circuit 180 communicates with the storage controller 5 based on a NAND interface standard such as ONFi (OpenNAND flash interface). The command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REn, the ready busy signal RBn, and the input / output signal DQ are used for communication between the storage device 1 and the storage controller 5.

[0049] The command latch enable signal CLE is a signal indicating that the input / output signal DQ received by the storage device 1 is a command CMD. The address latch enable signal ALE is a signal indicating that the signal DQ received by the storage device 1 is an address ADD. The write enable signal WEn is a signal for inputting the command input / output signal DQ of the storage device 1. The read enable signal REn is a signal for outputting the command input / output signal DQ of the storage device 1.

[0050] The ready busy signal RBn is a signal that notifies the storage device 1 to the storage controller 5 whether the storage device 1 is in a ready state to accept a command from the storage controller 5 or in a busy state to accept no command.

[0051] The input / output signal DQ is, for example, a signal set with an 8-bit width. The input / output signal DQ may include a command CMD, an address ADD, data DT, and the like.

[0052] The temperature sensor 170 measures the temperature of the chip (or package) of the storage device 1. The temperature sensor 170 transmits the temperature measurement result to the sequencer 190.

[0053] In addition, the temperature sensor 170 may also be disposed in the sequencer 190 .

[0054] The sequencer 190 controls the overall operation of the storage device 1. For example, the sequencer 190 controls each circuit based on the command CMD in the command register 120.

[0055] For example, the sequencer 190 generates a code (hereinafter also referred to as a digital code) CD based on the measurement result of the temperature. The code CD is represented by a digital value of 2 bits or more. The sequencer 190 sends the generated code CD to the voltage generating circuit 160. The voltage generating circuit 160 controls the magnitude of the voltage used for the operation of the storage device 1 based on the received code CD.

[0056] For example, the sequencer 190 includes a digital control circuit 191. The digital control circuit 191 generates various digital signals such as a code CD.

[0057] Alternatively, the code CD may be directly transmitted from the temperature sensor 170 to the voltage generating circuit 160 .

[0058] Hereinafter, each circuit of the circuits 120 to 190 other than the memory cell array 110 in the memory device 1 or a collection thereof is also referred to as a CMOS circuit (or peripheral circuit) 200 .

[0059] Figure 2 0 is a circuit diagram showing a circuit configuration of a certain block BLK in the memory cell array 110 .

[0060] like Figure 2 As shown, a block BLK includes multiple (e.g., 5) string units SU (SU0, SU1, SU2, SU3, SU4). Each string unit SU includes multiple NAND strings NS. The number of blocks in the memory cell array 110, the number of string units in the block BLK, and the number of NAND strings in the string unit SU are arbitrary.

[0061] Each NAND string NS includes a plurality of memory cells MT (MT0, MT1, MT2, ..., MTn-3, MTn-2, MTn-1) and a plurality of selection transistors ST1 and ST2. n is a natural number greater than 2. The plurality of memory cells MT are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2.

[0062] The memory cell MT stores data in a substantially nonvolatile manner.

[0063] The memory cell (also referred to as a memory cell transistor) MT is a field effect transistor having a control gate and a charge storage layer.

[0064] The gate of the selection transistor ST1 in each string unit SU is connected to a corresponding one of a plurality of selection gate lines SGD ( SGD0 , SGD1 , SGD2 , SGD3 , SGD4 ).

[0065] The gates of the selection transistors ST2 in the string units SU are connected to, for example, a selection gate line SGS in common. The gates of the selection transistors ST2 may be connected to different selection gate lines SGS for each string unit SU.

[0066] The control gates of the memory cells MT0, MT1, MT2, ..., MTn-3, MTn-2, MTn-1 belonging to the same block BLK are respectively connected to a corresponding one of a plurality of word lines WL (WL0, WL1, WL2, ..., WLn-3, WLn-2, ​​WLn-1).

[0067] The drains of the selection transistors ST1 of the NAND strings NS belonging to the same column in the memory cell array 110 are connected to corresponding one bit lines BL among a plurality of bit lines BL (BL0, BL1, ..., BLm-1), respectively. m is a natural number greater than or equal to 2.

[0068] The sources of the plurality of selection transistors ST2 are commonly connected to a source line SL.

[0069] The string unit SU is a collection of NAND strings NS connected to different bit lines BL and connected to the same selection gate line SGD.

[0070] The block BLK is a collection of a plurality of string units SU that share a plurality of word lines WL. The memory cell array 110 is a collection of a plurality of blocks BLK that share a plurality of bit lines BL.

[0071] Hereinafter, a collection of memory cells MT commonly connected to the same word line WL in each string unit SU (memory cell group) is also referred to as a cell unit CU (or memory group).

[0072] Figure 3 1 is a cross-sectional view showing a structural example of a memory cell array in a case where the semiconductor device 1 according to the present embodiment is a NAND flash memory.

[0073] like Figure 3 As shown, the memory cell array 110 includes a semiconductor substrate (hereinafter also referred to as a substrate) 20, conductive layers 21, 22 (22a, 22b, 22c), 28, and insulating layers 31, 32, 34, 38. The memory cell array 110 has a structure (stacked wiring 300) in which a plurality of conductive layers 22 (22a, 22b, 22c) are stacked in the Z direction.

[0074] An insulating layer 38 is provided on the upper surface of the semiconductor substrate 20. The insulating layer 38 covers, for example, the CMOS circuit 200 such as the row control circuit 140 and the sense amplifier circuit 150 on the semiconductor substrate 20.

[0075] The conductive layer 21 is provided on the upper surface of the insulating layer 38. The conductive layer 21 is, for example, a plate-shaped layer extending along the XY plane. The conductive layer 21 is used as a source line SL. The conductive layer 21 contains, for example, silicon doped with phosphorus.

[0076] An insulating layer 31 is provided on the upper surface of the conductive layer 21. A conductive layer 22a is provided on the upper surface of the insulating layer 31. The conductive layer 22a is, for example, a plate-shaped layer extending along the XY plane. The conductive layer 22a is used as a selection gate line SGS. The conductive layer 22a contains, for example, tungsten.

[0077] On the upper surface of the conductive layer 22a, the insulating layer 32 and the conductive layer 22b are alternately stacked in the Z direction. The conductive layer 22b is, for example, a plate-shaped layer extending along the XY plane. The stacked plurality of conductive layers 22b are used as word lines WL0, ..., WLn-1 in order from the semiconductor substrate 20 side. The conductive layer 22b contains, for example, tungsten.

[0078] A conductive layer 22c is provided above the uppermost conductive layer 22b via an insulating layer 32. The conductive layer 22c is, for example, a plate-shaped layer extending along the XY plane. The conductive layer 22c is used as a selection gate line SGD. The conductive layer 22c contains, for example, tungsten.

[0079] An insulating layer 34 is provided on the upper surface of the conductive layer 22c. The insulating layer 34 may also be composed of a plurality of insulating layers. A conductive layer 28 is provided on the upper surface of the insulating layer 34. The conductive layer 28 is, for example, a linear layer extending along the Y direction. The conductive layer 28 is used as a bit line BL. In a region not shown in the figure, a plurality of conductive layers 28 are arranged along the X direction. The conductive layer 28 contains, for example, copper.

[0080] Hereinafter, a structure including a plurality of stacked conductive layers 22 and a plurality of insulating layers 31 and 32 is referred to as a stacked wiring 300 .

[0081] The storage columns MP are each arranged in the stacked wiring 300 so as to extend along the Z direction. The storage columns MP penetrate the insulating layer 32 and the conductive layer 22. The bottom of the storage column MP is in contact with the conductive layer 21. The portion where the storage column MP intersects with the conductive layer 22a functions as a selection transistor ST2. The portion where the storage column MP intersects with a conductive layer 22b functions as a storage cell MT. The portion where the storage column MP intersects with the conductive layer 22c functions as a selection transistor ST1.

[0082] Each of the storage pillars MP includes, for example, a core member 24, a semiconductor layer 25, and a laminated film (also referred to as a storage layer) 26. The core member 24 is arranged to extend along the Z direction. For example, the upper end of the core member 24 is located at a position higher than the conductive layer 22c. The lower end of the core member 24 reaches the conductive layer 21. The semiconductor layer 25 covers the periphery of the core member 24. In the lower part of the storage pillar MP, a portion of the semiconductor layer 25 is in contact with the conductive layer 21. Except for the portion where the semiconductor layer 25 is in contact with the conductive layer 21, the laminated film 26 covers the side and bottom surfaces of the semiconductor layer 25. The core member 24 includes, for example, an insulator such as silicon oxide. The semiconductor layer 25 contains, for example, silicon.

[0083] Figure 4 This is a plan view showing an example of the structure of a memory column of a NAND flash memory.

[0084] Figure 4 2 is a cross-sectional view for explaining the structure of the memory column MP. Figure 4 , a cross section along the XY plane of the memory pillar MP at a position where the conductive layer 22 b is arranged is shown.

[0085] For example, the memory pillar MP has a circular (or elliptical) planar shape when viewed from the Z direction. The semiconductor layer 25 covers the side surfaces of the cylindrical core member 24. The stacked film 26 is provided between the semiconductor layer 25 and the conductive layer 22b.

[0086] The stacked film 26 includes a tunnel insulating layer 261, a charge storage layer 262, and a block insulating layer 263. The tunnel insulating layer 261, the charge storage layer 262, and the block insulating layer 263 are stacked in a direction parallel to the surface (XY plane) of the semiconductor substrate 20.

[0087] The tunnel insulating layer 261 is provided between the semiconductor layer 25 and the charge storage layer 262. The tunnel insulating layer 261 is a tunnel barrier between the semiconductor layer 25 and the charge storage layer 262. When a voltage of a certain magnitude is applied between the conductive layer 22b and the semiconductor layer 25, charges move between the semiconductor layer 25 and the charge storage layer 262 due to the tunnel effect. The tunnel insulating layer 261 contains, for example, silicon oxide.

[0088] The charge storage layer 262 is provided between the tunnel insulating layer 261 and the blocking insulating layer 263. For example, the charge storage layer 262 is a charge trapping film capable of holding (trapping) charges. In this case, the charge storage layer 262 contains silicon nitride. However, the charge storage layer 262 may also be a floating gate electrode. The floating gate electrode contains silicon.

[0089] The blocking insulating layer 263 is provided between the charge storage layer 262 and the conductive layer 22b. The blocking insulating layer 263 prevents the movement of charges between the charge storage layer 262 and the conductive layer 22b. The blocking insulating layer 263 contains, for example, silicon oxide and (or) aluminum oxide.

[0090] In the memory column MP, the semiconductor layer 25 is used as a channel region (current path) of the memory cells MT0, ..., MTn-1 and the selection transistors ST1 and ST2. The memory device 1 enables the current through the memory column MP to flow between the bit line BL and the contact LI (source line SL) by turning on the memory cells MT0, ..., MTn-1 and the selection transistors ST1 and ST2.

[0091] return Figure 3 A columnar contact CV is provided on the upper surface of the semiconductor layer 25 in the storage column MP. In the illustrated area, two contact CVs corresponding to two storage columns MP among the six storage columns MP are shown. The storage column MP that does not overlap with the gap SHE and to which the contact CV is not connected is connected to the contact CV in an area not illustrated (for example, an area in the depth direction or the front direction of the paper).

[0092] A conductive layer 28 (a bit line BL) contacts the upper surface of the contact CV. In each space divided by the gaps SLT and SHE, a contact CV is connected to a conductive layer 28. At each conductive layer 28, a storage column MP disposed between adjacent gaps SLT and SHE is electrically connected to a storage column MP disposed between two adjacent gaps SHE.

[0093] The slit SLT has, for example, a portion arranged along the XZ plane. The slit SLT divides and separates the conductive layer 22. The contact LI in the slit SLT is arranged along the slit SLT. A portion of the upper end of the contact LI contacts the insulating layer 34. The lower end of the contact LI contacts the conductive layer 21. The contact LI is used, for example, as a portion of the source line SL. The spacer SP is at least arranged between the contact LI and the conductive layers 22a, 22b, and 22c. The contact LI and the conductive layers 22a, 22b, and 22c are separated and insulated by the spacer SP.

[0094] The gap SHE, for example, has a portion arranged along the X-Z plane. The gap SHE at least divides and disconnects the conductive layer 22c. The upper end of the gap SHE contacts the insulating layer 34. The lower end of the gap SHE contacts the insulating layer 32 between the uppermost conductive layer 22b and the conductive layer 22c. The gap SHE, for example, includes an insulator such as silicon oxide. The upper end of the gap SHE may be aligned with the upper end of the gap SLT or may not be aligned. The upper end of the gap SHE may be aligned with the upper end of the storage column MP or may not be aligned.

[0095] The plurality of elements TR and RES may be provided on the semiconductor substrate 20 below the memory cell array 110 .

[0096] For example, the field effect transistor TR is provided in a well region 27 of the semiconductor substrate 20. The well region 27 is a semiconductor region partitioned by an insulator 29a having an STI (Shallow trench isolation) structure.

[0097] The field effect transistor includes two source / drain electrodes 41 ( 41 a , 41 b ), a gate insulating film 42 , and a gate electrode 43 .

[0098] The source / drain 41a, 41b are arranged in the well region 27. The source / drain 41a, 41b are each a diffusion layer (impurity semiconductor region). The gate insulating film 42 is arranged on the well region 27 between the two source / drains 41a, 41b. The gate electrode 43 is arranged on the gate insulating film 42. The portion in the well region 27 opposite to the gate electrode 43 becomes the channel region of the field effect transistor TR. For example, the gate electrode 43 includes a single layer of polycrystalline silicon, or a stack of polycrystalline silicon and silicides such as nickel silicide (NiSi), nickel platinum silicide (NiPtSi) and cobalt silicide (CoSi). For example, the gate electrode 43 includes a stack of silicon nitride (SiN), polycrystalline silicon, tungsten (W) and tungsten silicide (WSi). For example, the gate electrode 43 includes aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the gate electrode 43 includes a stack of aluminum oxide (AlO), aluminum cobalt copper (AlCoCu), aluminum titanium nitride (AlTiN), aluminum titanium nitride (AlTiN), aluminum titanium oxynitride (AlTiON), tantalum nitride (TaN), and titanium nitride (TiN). For example, the gate electrode 43 includes a stack of silicides such as nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi), polysilicon, and titanium nitride (TiN). For example, the gate electrode 43 includes a stack of tungsten (W), tungsten silicon nitride (WSiN), tungsten (W), titanium nitride (TiN), polysilicon, and titanium nitride (TiN). In addition, the stack described here may also include a case where it does not include all layers but only includes a part of the layers.

[0099] The contact 46a is provided on the gate electrode 43. The contact 46b is provided on the source / drain 41. The plurality of contacts 46a and 46b are electrically connected to a plurality of wirings (metal layers) 47a and 47b in the insulating layer (interlayer insulating film) 38, respectively.

[0100] For example, the resistor (resistance element) RES is disposed on the insulator 29b in the semiconductor substrate 20. The resistor RES includes a conductive layer (resistance layer) 45. The conductive layer 45 has the same stacked structure as the gate electrode 43. For example, the conductive layer 45 includes a single layer of polycrystalline silicon, or a stack of polycrystalline silicon and silicides such as nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi). For example, the conductive layer 45 includes a stack of silicon nitride (SiN), polycrystalline silicon, tungsten (W), and tungsten silicide (WSi). For example, the conductive layer 45 includes aluminum (Al), titanium (Ti), and / or tantalum (Ta). For example, the conductive layer 45 includes a stack of aluminum oxide (AlO), aluminum cobalt copper (AlCoCu), aluminum titanium nitride (AlTiN), aluminum titanium nitride (AlTiN), aluminum titanium oxynitride (AlTiON), tantalum nitride (TaN), and titanium nitride (TiN). For example, the conductive layer 45 includes a stack of silicides such as nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi), polysilicon, and titanium nitride (TiN). For example, the conductive layer 45 includes a stack of tungsten (W), tungsten silicon nitride (WSiN), tungsten (W), titanium nitride (TiN), polysilicon, and titanium nitride (TiN). In addition, the stack described here may include only a part of the layers instead of all the layers.

[0101] The contact 46c is provided on the upper surface of the conductive layer 45. The contact 46c is connected to the wiring 47c in the insulating layer 38.

[0102] The resistor RES may be provided on the semiconductor region of the semiconductor substrate 20 .

[0103] The resistor RES may be formed using a metal layer in the insulating layer 38 .

[0104] The field effect transistor TR and the resistor RES are electrically connected to other elements on the semiconductor substrate 20 via the wirings 47a, 47b, and 47c. Thus, a CMOS circuit 200 such as the row control circuit 140 and the voltage generation circuit 160 is formed on the semiconductor substrate 20 below the memory cell array 110.

[0105] In addition, the structure of the storage device 1 of this embodiment is not limited to Figure 3 as well as Figure 4 For example, the memory cell array 110 and the CMOS circuit 200 may be formed on different chips (semiconductor substrates). In this case, the chip of the memory cell array 110 is stacked on the chip of the CMOS circuit 200 in the Z direction. The chip of the memory cell array 110 is bonded to the chip of the CMOS circuit 200 via a conductive member.

[0106] Figure 5 It is a diagram for explaining the relationship between data stored in the memory cell MT and the threshold voltage of the memory cell MT.

[0107] like Figure 5 As shown, the memory cell MT can take multiple states corresponding to the threshold voltage. Multiple memory cells contain characteristic deviations. Considering the characteristic deviations, data is associated with a distribution of voltage values ​​centered on a certain threshold voltage (hereinafter referred to as threshold voltage distribution) 999 (999a, 999b, 999c, 999d).

[0108] The memory cell MT can assume an erased state and more than one programmed state.

[0109] exist Figure 5 In the figure, the "Er" state corresponds to the erased state (the state in which data is erased), and the "A", "B", ..., "z" states correspond to the programmed states (the state in which data is programmed). In addition, the "z" state shows, for convenience, the programming state corresponding to the highest threshold voltage (threshold voltage distribution) among the multiple programming states that the memory cell MT can take.

[0110] SLC (Single Level Cell) is 1 bit / cell and can take 2 states ("Er" and "A" states). MLC (Multi Level Cell) is 2 bits / cell and can take 4 states ("Er", "A", "B" and "C" states). TLC (Triple Level Cell) is 3 bits / cell and can take 8 states ("Er", "A", "B", ..., "F" and "G" states). QLC (Quad Level Cell) is 4 bits / cell and can take 16 states ("0", "1", "2", ..., "E" and "F" states). PLC (Penta Level Cell) is 5 bits / cell and can take 32 states ("0", "1", "2", ..., "U" and "V" states). HLC (HexaLevel Cell) is 6 bits / cell and can take 64 states ("0", "1", "2", ..., "BA" and "BB" states). 7LC (Seven Level Cell) is 7 bits / cell and can take 128 states ("0", "1", "2", ..., "DM" and "DN" states).

[0111] exist Figure 5In the example, the threshold voltage distribution 999a of the memory cell MT in the "Er" state is less than the voltage VAR. The threshold voltage distribution 999b of the memory cell MT in the "A" state is greater than the voltage VAR and less than the voltage VBR (>VAR). The threshold voltage distribution 999c of the memory cell MT in the "B" state is greater than the voltage VBR and less than the voltage VCR (>VBR). The threshold voltage distribution 999d of the memory cell MT in the "z" state is greater than the voltage VzR and less than the voltage VREAD.

[0112] The voltages (voltage values) VAR, VBR, ..., VzR are each a voltage used for reading data. Hereinafter, the voltages VAR, VBR, ..., VzR are each also referred to as a determination level or a read level. The voltages VAR to VzR are also collectively referred to as a voltage (read voltage) VCGR. The voltage VREAD is, for example, a voltage applied to a word line (non-selected word line) WL that does not include a read object during a read operation. When the voltage VREAD is applied to the memory cell MT, the memory cell MT is turned on regardless of the data stored in the memory cell MT. Based on the result of the on (ON) / off (OFF) of the memory cell MT related to the applied read level, the data stored in the memory cell MT is determined.

[0113] In order to verify the writing of data, voltages VAV, VBV, ..., VzV are set for each state. Voltage VAV is higher than the read level VAR and is below the lower limit value of the desired threshold voltage distribution 999b in the "A" state. Voltage VBV is higher than the read level VBR and is below the lower limit value of the desired threshold voltage distribution 999c in the "B" state. Voltage VzV is higher than the read level VzR and is below the lower limit value of the desired threshold voltage distribution 999d in the "z" state.

[0114] To verify data erasure, a voltage VErV is set between the threshold voltage distribution 999a of the Er state and the threshold voltage distribution 999b of the A state. For example, voltage VErV is lower than voltage VAR and is greater than the upper limit of the desired threshold voltage distribution 999a of the Er state.

[0115] Hereinafter, each of the voltages VErV, VAV, VBV, . . . , VzV is also referred to as a verify level.

[0116] Regarding the verification of each state, when a verification level is applied to the memory cell MT, whether the verification of the state of each memory cell MT related to data writing or data erasure has passed (or failed) is determined based on whether the memory cell MT is turned on. Whether the executed action sequence is successful is verified based on whether the number of passes / fails of the verification of the states of the plurality of memory cells is within an allowable range.

[0117] The characteristics of the memory cell MT vary according to the temperature of the chip (package), and therefore, it is preferable to adjust the voltage value of each read level and the voltage value of each verification level according to the temperature of the chip.

[0118] As mentioned above Figure 1 As shown, the memory device (semiconductor device) 1 of the present embodiment includes a digital-to-analog conversion circuit 163 in a voltage generation circuit 160 .

[0119] Hereinafter, the digital-analog conversion circuit 163 is referred to as a DA conversion circuit 163 .

[0120] The DA conversion circuit 163 receives the code CD and operates based on the code CD.

[0121] The driving circuit 162 outputs various voltages for operating the memory cell array 110 to the row control circuit 140 and the sense amplifier circuit 150 using the voltage boosted by the charge pump circuit 161 .

[0122] The drive circuit 162 outputs various adjusted voltages to the wiring connected to the word line WL, the wiring connected to the selection gate lines SGD and SGS, and the wiring connected to the source line SL, according to the conversion result of the code CD by the DA conversion circuit 163. For example, when the value of the code CD increases, the output voltage of the drive circuit 162 increases.

[0123] As described above, in the present embodiment, the magnitude of the output voltage of the driving circuit 162 is controlled by the DA conversion circuit 163 based on the code CD.

[0124] Figure 6 1 is a circuit diagram showing a configuration example of the drive circuit 162 and the DA conversion circuit 163 in the voltage generation circuit 160 in the storage device 1 according to the present embodiment.

[0125] The driving circuit 162 includes a plurality of drivers DRV.

[0126] The DA conversion circuit 163 includes a plurality of DA converters DAC.

[0127] One DA converter DAC is connected to one driver DRV. A set of one DA converter DAC and one driver DRV is sometimes regarded as one circuit unit (DA converter or driver).

[0128] Each DA converter DAC receives the code CD from the sequencer 190. As described above, the code CD is a digital signal (digital value) generated based on the result of the temperature measurement by the temperature sensor 170.

[0129] The DA converter DAC supplies an analog signal (eg, voltage and / or current) based on the code CD to the driver DRV.

[0130] The driver DRV supplies an output voltage Vout having a magnitude corresponding to the analog signal from the DA converter DAC to the memory cell array 110 via the row control circuit 140. The output voltage Vout is supplied to the word line WL, the selection gate lines SGD and SGS, or the source line SL.

[0131] The output voltage Vout of the driver DRV is, for example, a verification level (verification voltage) for a write sequence or a read level (read voltage) for a read sequence.

[0132] The output voltage Vout of the driver DRV may include a program voltage, a non-selection voltage VREAD, or a voltage supplied to the selection gate lines SGD, SGS, and the like.

[0133] In this way, the magnitude of the output voltage Vout of the driver DRV is controlled based on the result of the DA conversion process of the DA converter DAC.

[0134] In addition, the output signal Vout of the driver DRV may also be supplied to the sense amplifier circuit 150 .

[0135] Figure 7 1 is a circuit diagram showing the internal configuration of the drive circuit 162 and the DA conversion circuit 163 in the storage device (semiconductor device) 1 according to the present embodiment.

[0136] In the driving circuit 162 , the driver DRV includes an operational amplifier 50 and a resistor 51 .

[0137] The operational amplifier 50 includes two input terminals IT1 and IT2 and one output terminal OT. One input terminal IT1 is an inverting (reverse) input terminal. The inverting input terminal IT1 is connected to the node ND1. The other input terminal IT2 is a non-inverting input terminal. The non-inverting input terminal IT2 is connected to the node ND2.

[0138] The output terminal OT is an output node of the driver DRV and is electrically connected to, for example, a wiring connected to the word line WL, a wiring connected to the selection gate line SGD, a wiring connected to the selection gate line SGS, or a wiring connected to the source line SL.

[0139] The voltage Vin of the node ND1 is supplied to the inverting input terminal IT1. The magnitude of the voltage Vin is controlled to be the same magnitude as the voltage (e.g., voltage Vcenter) of the non-inverting input terminal IT2 by the operational amplification operation of the operational amplifier 50. As a result, the current Iin flows through the inverting input terminal IT1 and the node ND1. The voltage Vin does not depend on the resistance value of the resistor 51 and the current value of the current Iin.

[0140] For example, the potential of the node ND2 is set to a voltage Vcenter having a certain voltage value by the voltage generation circuit 160. For example, the voltage Vcenter is applied to the node ND2 via the voltage node NVA. Thus, the voltage Vcenter is supplied from the node ND2 to the non-inverting input terminal IT2.

[0141] The resistor 51 is connected to the operational amplifier 50. One end of the resistor 51 is connected to the inverting input terminal IT1 of the operational amplifier 50. The other end of the resistor 51 is connected to the output terminal OT of the operational amplifier 50. The resistor 51 has a resistance value R1. For example, the resistor 51 is used Figure 3 It is formed by a resistor body RES.

[0142] The operational amplifier 50 and the resistor 51 form an inverting amplifier circuit. Hereinafter, a group (driver) DRV composed of the operational amplifier 50 and the resistor 51 is also referred to as a drive amplifier DRV.

[0143] For example, the operational amplifier 50 forming an inverting amplifier circuit outputs a voltage Vout corresponding to the sum of the potential of the input terminal IT1 and the potential of the input terminal IT2 from the output terminal OT.

[0144] The DA converter DAC includes a resistor string (also referred to as a resistor network or a resistor circuit) RS, a plurality of switches SW, and a current source circuit 59 .

[0145] One end (input node) NDa of the resistor string RS is connected to the inverting input terminal IT1 of the operational amplifier 50 via the node ND1 .

[0146] The other end (output node) NDb of the resistor string RS is connected to the non-inverting input terminal IT2 of the operational amplifier 50 via the node ND2 .

[0147] The resistor string RS includes a plurality of resistors 55 connected in series. For example, the resistor string RS includes M resistors 55. M is a natural number greater than 1. The resistance value of each resistor 55 is the same. Each resistor 55 has a resistance value R2. For example, the resistor 55 uses Figure 3 The resistor RES is formed. The resistance value R2 of the resistor 55 can be, for example, a value in the range of 10Ω to 10kΩ. A more specific example of the resistance value R2 is 1kΩ.

[0148] A plurality of switches SW (SW<1>, SW<2>, . . . , SW<M-1>, SW<M>) are connected to the resistor string RS. The number of switches SW is M. One switch SW is associated with one resistor 55 .

[0149] Each switch SW is connected to a connection node NDc between two resistors 55 .

[0150] In each of the plurality of switches SW, one end of the switch SW is connected to the corresponding connection node NDc. The other end of each switch SW is connected to the node NDd. Hereinafter, the connection node NDc is also referred to as a tap.

[0151] Between the resistor string RS and the node NDd, a plurality of switches SW are connected in parallel to each other.

[0152] For example, the switch SW is a MOS (Metal-Oxide-Semiconductor) switch or a field effect transistor.

[0153] An input node NX1 of the current source circuit 59 is connected to the node NDd. A node NX2 of the current source circuit 59 is connected to the ground node NDz.

[0154] The current source circuit 59 draws a portion of the current (current Ir) flowing in the resistor string RS via one of the switches SW in the on state. The current source circuit 59 causes the current Ir to flow from the node NDc connected to the switch SW in the on state to the ground node NDz. The magnitude of the current Ir can be determined by the driving force of the current source circuit 59.

[0155] In the DA converter DAC, one digital value represented by a code CD is allocated to each of the plurality of switches SW.

[0156] The number of bits of the code CD corresponds to the number of resistors 55 in the resistor string RS. For example, when the number of resistors 55 in the resistor string RS is 256, the number of bits of the code CD is 8 bits.

[0157] In addition, the number of resistors 55 is not limited to 256. The number of resistors 55 may be 512 (2 9) or 1024 (2 10 In this case, the number of bits of the code CD is 9 bits or 10 bits or more. The number of resistors 55 may also be 128 (2 7 In this case, the number of bits of the code CD is 7 bits or less.

[0158] Different 8-bit codes are assigned to the switches SW so that one switch SW can be identified from the plurality of switches SW. One switch SW is activated by the digital value of one 8-bit code CD.

[0159] When the DA converter DAC is operated, one of the plurality of switches SW is turned on based on the supplied code CD, and the remaining switches SW of the plurality of switches SW are turned off.

[0160] For example, the digital values ​​of the code CD are respectively assigned to the plurality of switches SW in such a manner that the digital value of the code CD increases in order from the node NDb side of the resistor string RS (the non-inverting input terminal IT2 side of the operational amplifier 50) toward the node NDa side of the resistor string RS (the inverting input terminal IT1 side of the operational amplifier 50).

[0161] Among the plurality of switches SW, the switch SW<1> closest to the node NDb is assigned the first digital code CD. Among the plurality of switches SW, the switch SW<M> closest to the node NDa is assigned the last digital code CD.

[0162] For example, when the digital code CD is represented by an 8-bit digital value, the switch SW<1> of the first stage has the first code (for example, "00000000") CD. When the digital code CD is represented by an 8-bit digital value, the switch SW<M (M=256)> of the last stage (the 256th) has the 256th code (for example, "11111111") CD.

[0163] Regarding the current path between the inverting input terminal IT and the current source circuit 59 , the number of resistors 55 that are in an effective state on the current path changes according to the value of the code CD.

[0164] When the value of the code CD is small, the number of resistors 55 that are in an effective state on the current path (the current path from the node NDa to the node NDc) between the inverting input terminal IT1 and the current source circuit 59 is large. In contrast, when the value of the code CD is large, the number of resistors 55 that are in an effective state on the current path between the inverting input terminal IT1 and the current source circuit 59 is smaller than when the value of the code CD is small.

[0165] As a result, the current Iin flowing through the inverting input terminal IT1 of the operational amplifier 50 increases as the digital value of the code CD increases.

[0166] As described above, in the DA conversion circuit 163 of the storage device 1 of the present embodiment, the conversion value from the digital value (code CD) to the analog value (current Iin) in the DA converter DAC changes relatively monotonically.

[0167] The current source circuit 59 is electrically connected to a connection node NDc in the resistor string RS via a switch SW in an on state.

[0168] For example, which switch SW among the plurality of switches SW is selectively turned on depends on the temperature of the storage device 1 .

[0169] <Current source circuit>

[0170] Reference Figure 8 , Fig. 9 as well as Fig.10 , a configuration example of the current source circuit 59 in the DA conversion circuit 163 of the storage device 1 according to the present embodiment will be described.

[0171] Figure 8 : is a circuit diagram showing an example of a current source circuit 59A used in the DA converter DAC.

[0172] The current source circuit 59A is a current source having a circuit configuration (OP-amp+Tr method) including an operational amplifier and a field effect transistor. The OP-amp+TR method current source circuit 59A can make the change in current relatively stable even if the output voltage changes.

[0173] The current source circuit 59A includes an operational amplifier 901 , a field effect transistor 902 , and a resistor 903 .

[0174] The operational amplifier 901 includes an inverting input terminal IT1 a , a non-inverting input terminal IT2 a , and an output terminal OTa.

[0175] The field effect transistor 902 includes a gate and two sources / drains (two nodes). For example, the field effect transistor 902 is an n-channel MOS (Metal-Oxide-Semiconductor) transistor.

[0176] Hereinafter, a field effect transistor is also simply referred to as a transistor.

[0177] The inverting input terminal IT1a of the operational amplifier 901 is connected to one end of the resistor 903 via the node ND90a. The non-inverting input terminal IT2a of the operational amplifier 901 is connected to the voltage node NV1 to which the voltage Vr is applied. The output terminal OTa of the operational amplifier 901 is connected to the gate of the field effect transistor 902.

[0178] One source / drain of the field effect transistor 902 is connected to the node ND90b. The other source / drain of the field effect transistor 902 is connected to one end of a resistor 903. The other end of the resistor 903 is connected to a ground node. The resistor 903 has a resistance value Ra.

[0179] For example, the node ND90b is connected to the node NDd.

[0180] The operational amplifier 901 supplies the output voltage Vg to the gate of the field effect transistor 902 based on a calculation process using the voltage Vr and the potential of the node ND90 a .

[0181] The field effect transistor 902 causes the current Ir to flow with a driving force corresponding to the output voltage Vg of the operational amplifier 901 .

[0182] Figure 8 The magnitude of the current Ir in the current source circuit 59A has the following relationship.

[0183] Ir=Vr / Ra

[0184] The current source circuit 59A can flow a current of a single polarity.

[0185] so, Figure 8 The current source circuit 59A functions as a current source.

[0186] Fig. 9 is shown with Figure 8 A circuit diagram of an example of a different current source circuit 59B.

[0187] like Fig. 9 As shown, the current source circuit 59B includes four field effect transistors 911 , 912 , 913 , 914 and a current source element 915 .

[0188] The current source circuit 59B is a current mirror type current source. The current mirror type current source circuit 59B has a small circuit scale. The current mirror type current source circuit 59B can relatively easily cope with a low power supply voltage.

[0189] The current source circuit 59B is a current mirror circuit having a cascode structure.

[0190] Each of the transistors 911, 912, 913, and 914 has a gate and two sources and drains (two nodes). Each of the transistors 911, 912, 913, and 914 is an n-channel MOS transistor.

[0191] The gate of the transistor 911 is connected to the gate of the transistor 912 .

[0192] One source / drain of the transistor 911 is connected to the ground node, and the other source / drain of the transistor 911 is connected to the node ND91a.

[0193] One source / drain of the transistor 912 is connected to the ground node, and the other source / drain of the transistor 912 is connected to the node ND91b.

[0194] The gate of the transistor 913 is connected to the gate of the transistor 914 .

[0195] One source / drain of the transistor 913 is connected to the other source / drain of the transistor 911 via the node ND91 a .

[0196] One source / drain of the transistor 914 is connected to the other source / drain of the transistor 912 via the node ND91 b .

[0197] The other source / drain of the transistor 913 is connected to the gates of the transistors 911 and 912 .

[0198] The gates of the transistors 913 and 914 are connected to the voltage node NV2a. The bias voltage Vbias is supplied to the gates of the transistors 913 and 914 via the voltage node NV2a.

[0199] The element 915 is connected between the other source / drain of the transistor 913 and the voltage node NV2b. For example, a voltage V1 such as a power supply voltage or a reference voltage is supplied to the voltage node NV2b. The element 915 includes a resistor or a current source (for example, Figure 8 or the following Fig.10 current source circuit).

[0200] The other source and drain of the transistor 914 are connected to the node ND91c. The node ND91c is connected to the node NDd.

[0201] The transistors 913 and 914 operate by a driving force corresponding to the bias voltage Vbias.

[0202] The transistors 911 and 912 operate according to the potential of the other source / drain of the transistor 913 .

[0203] The current source circuit 59B can flow a current Ir of a single polarity through a current mirror circuit including cascode-connected transistors 911 , 912 , 913 , and 914 .

[0204] Fig. 9 The circuit 59B can form the current source circuit 59 with a smaller circuit area.

[0205] Fig.10 is shown with Figure 8 as well as Fig. 9 A circuit diagram of an example of a different current source circuit 59C.

[0206] Fig.10 The current source circuit 59C is an operational amplifier (OP-amp) current source. The OP-amp current source circuit 59C can set the polarity of the output current to two directions: negative polarity and positive polarity.

[0207] The current source circuit 59C includes an operational amplifier 920 and a plurality of resistors 921 , 922 , 923 , 924 , and 925 .

[0208] The operational amplifier 920 has an inverting input terminal IT1c, a non-inverting input terminal IT2c, and an output terminal OTc. The inverting input terminal IT1c is connected to the node ND92a. The non-inverting input terminal IT2c is connected to the node ND92b. The output terminal OT2 is connected to the node ND92c.

[0209] One end of the resistor 921 is connected to the inverting input terminal IT1c via the node ND92a. The other end of the resistor 921 is connected to the voltage node NV3a. The voltage Vrm is supplied to the voltage node NV3a.

[0210] One end of the resistor 922 is connected to the non-inverting input terminal IT2c via the node ND92b. The other end of the resistor 922 is connected to the voltage node NV3b. The voltage Vrp is supplied to the voltage node NV3b.

[0211] One end of the resistor 923 is connected to the inverting input terminal IT1c via the node ND92a, and the other end of the resistor 923 is connected to the output terminal OTc via the node ND92c.

[0212] One end of the resistor 924 is connected to the output terminal OTc and the other end of the resistor 923 via the node ND92c. The other end of the resistor 924 is connected to the node ND92d.

[0213] One end of the resistor 925 is connected to the other end of the resistor 924 via the node ND92d. The other end of the resistor 925 is connected to the non-inverting input terminal IT2c and one end of the resistor 922 via the node ND92b.

[0214] The resistors 921 and 922 each have a resistance value of Rb. The resistor 923 has a resistance value of Rc. The resistor 924 has a resistance value of Rd. The resistor 925 has a resistance value of Re. The magnitude of the resistance value Re corresponds to "Rc-Rd".

[0215] The current source circuit 59C outputs the current Ir from the node ND92d. For example, the node ND92d is connected to the node NDd.

[0216] Fig.10 The magnitude of the current Ir in the current source circuit 59C has the following relationship.

[0217] Ir=(Rc / Rb)×(Vrp-Vrm) / Rd

[0218] In this way, the current source circuit 59C functions as a current source through the operation of the operational amplifier 920 .

[0219] The current source circuit 59 can cause the current Ir to flow through the node ND92d in both positive and negative polarities.

[0220] also, Figure 8 , Fig. 9 as well as Fig.10 The circuits 59A, 59B, and 59C are examples of the current source circuit 59. The current source circuit 59 of the DA converter DAC may also have Figure 8 , Fig. 9 as well as Fig.10 Circuit configuration other than the configuration of .

[0221] (b) Action example

[0222] Reference Fig.11 , an operation example of the drive circuit 162 and the DA conversion circuit 163 in the semiconductor device 1 of the present embodiment will be described.

[0223] In the memory device (eg, NAND flash memory) 1 as the semiconductor device of the present embodiment, the drive circuit 162 and the DA conversion circuit 163 operate when supplying voltages to the word lines WL, the select gate lines SGD and SGS, and the source lines SL in the write sequence and the read sequence.

[0224] For example, the DA conversion circuit 163 contributes to the adjustment of the voltage values ​​of the verification level and the read level according to the temperature of the memory device 1 .

[0225] In the storage device 1 of the present embodiment, the temperature sensor 170 senses the temperature of the chip (or package) at a certain timing and transmits the temperature measurement result to the sequencer 190 .

[0226] For example, the sequencer 190 receives the measurement result of the temperature sensor 170. In the sequencer 190, the digital control circuit 191 generates a code CD having a digital value corresponding to the measurement result and the command CMD based on the temperature measurement result and the command CMD in the command register 120. The sequencer 190 sends the generated code CD to the voltage generation circuit 160.

[0227] The voltage generating circuit 160 receives the code CD and transmits the received code CD to the DA conversion circuit 163 .

[0228] The DA conversion circuit 163 receives the code CD. In the DA conversion circuit 163, each DA converter DAC controls the on and off of the plurality of switches SW based on the code CD. As a result, one switch SW corresponding to the code CD among the plurality of switches SW is turned on.

[0229] exist Fig.11 In the example, the switch SW [CD: N] having the code CD of "N" is turned on. N is an integer greater than 0. For example, N is less than M. For example, the maximum value that N can take is M-1. In addition, for example, N also corresponds to the number of resistors 55 present on the current path between the node NDb at the other end of the resistor string RS and the position of the switch SW in the on state.

[0230] The node (contact point) NDc connected to the on-state switch SW[CD:N] is electrically connected to the node NDd. As in this example, when the switch SW[CD:N] having the code CD of "N" is on, the M-N resistors 55 are connected to the current source circuit 59 via the on-state switch SW[CD:N].

[0231] In this way, the number of resistors 55 that become effective as the current path of the current Iin is determined based on the number (address) of the switch SW in the on state indicated by the code CD.

[0232] The current source circuit 59 allows the current Ir to flow from the connection node NDc toward the ground node NDz via the switch SW [CD:N] in the on state.

[0233] The magnitude of the current Iin corresponds to the number of resistors 55 (here, M-N) through which the current Iin flows.

[0234] The current Iin flows through the connection node NDc to which the switch SW in the on state is connected.

[0235] The current Iz, which is a remaining part of the current Iin, flows from the non-inverting input terminal IT2 of the operational amplifier 50 toward the current source circuit 59 via the switch SW [CD:N] in the on state.

[0236] The relationship between the current Iin and the current Ir is expressed by the following equation 1.

[0237] Iin=(N / M)×Ir…(Formula 1)

[0238] Here, "M" represents the number of resistors 55 in the resistor string RS. M is a natural number greater than 1. "N" represents a value corresponding to the number assigned to the switch SW in the on state. For example, N is a natural number greater than 0 (zero). N and M can be binary numbers or decimal numbers.

[0239] As an example, when the number (M) of resistors 55 is 256, "N" has any value in the range from 0 to 255. When "N" is 0, from the viewpoint of circuit design, the current Iin becomes 0. However, the current Iin has a weak current value due to the wiring resistance included in the circuit and / or the deviation of the characteristics between the elements forming the circuit.

[0240] In addition, the value of "N" can also be expressed in other words as the value indicating the number of resistors 55 existing from the node NDb at the other end of the resistor string RS to the position of the switch SW in the on state.

[0241] In addition, the value of "N" can also be said to be the value corresponding to the position where the connection node NDc of the resistor string RS is connected (short-circuited) to the input node NX1 (or node NDd) of the current source circuit 59 via the switch SW in the on state among the multiple connection nodes (contact points of the resistor body 55) NDc in the resistor string RS.

[0242] Alternatively, the value of "N" can also be said to be the number of resistors 55 among the multiple (M) resistors 55 in the resistor string RS that do not exist between the switch SW in the on state and one end (input node) NDa of the resistor string NS.

[0243] As shown in Expression 1, the current Iin can be determined independently of the resistance value R1 of the resistor 51 and the resistance value R2 of the resistor 55 .

[0244] Through the DA converter DAC, the current Iin as an analog value of a certain size can be obtained from the digital value N represented by the code CD.

[0245] For example, assume that the number of resistors 55 is 256 and the code CD is an 8-bit digital value. In this case, when the first switch SW<0> is selectively turned on, the magnitude of the current Iin becomes substantially zero. When the 256th switch SW<256> is selectively turned on, the magnitude of the current Iin is approximately (255 / 256)×Ir.

[0246] The output voltage Vout of the driver DRV is expressed by the following equation 2.

[0247] Vout=Vcenter+R1×(N / M)×Ir…(Formula 2)

[0248] Here, “Vcenter” indicates a voltage supplied to the non-inverting input terminal IT2 of the operational amplifier 50 . “ R1 ” indicates a resistance value of the resistor 51 .

[0249] For example, "Vcenter", "M" and "Ir" in Formula 2 are design parameters set for the DA converter DAC and the driver DRV. As described above, "N" in Formula 2 is a variable corresponding to the digital code CD based on the temperature of the storage device 1 and the command CMD.

[0250] Therefore, in Formula 2, the magnitude of the output voltage Vout can be controlled according to the value of “N”.

[0251] In this way, the magnitude of the output voltage Vout can be adjusted according to the code CD which is a digital value.

[0252] As described above, in the voltage generating circuit 160 of the storage device 1 according to the present embodiment, the DA converter DAC and the driver DRV operate.

[0253] As a result, in this embodiment, a voltage having an adjusted voltage value is supplied to the wiring in the memory cell array 110 .

[0254] (c) Summary

[0255] In a NAND flash memory, as the number of bits that can be stored in one memory cell increases, the permissible range of variation of the verification level and the read level with respect to each threshold voltage distribution becomes smaller.

[0256] In addition, the characteristics of the memory cell vary depending on the temperature of the chip.

[0257] Therefore, it is desired to adjust the voltage values ​​of the verification level and the read level with higher accuracy.

[0258] In the memory device as the semiconductor device of this embodiment, the DA conversion circuit 163 is used to control the magnitude of the voltage Vout output by the drive circuit 162 .

[0259] In the DA conversion circuit 163, the DA converter DAC includes a resistor string RS and a plurality of switches SW. The resistor string RS includes a plurality of resistors 55 connected in series. Each of the plurality of switches SW is connected to one end of a corresponding resistor 55. The resistor string RS is electrically connected to the current source circuit 59 via the plurality of switches SW.

[0260] When the voltage Vout is output from each driver DRV in the driving circuit 162, one of the multiple switches SW of each DA converter DAC is set to the on state based on the digital value of the code CD. As a result, the number of resistors 55 in the resistor string RS through which the current from the driver DRV flows is controlled, and the magnitude of the current flowing in the resistor string RS is determined.

[0261] As a result, in the memory device 1 as the semiconductor device of the present embodiment, the monotonicity of DA conversion by the DA converter DAC is ensured.

[0262] For example, when a DA converter of a semiconductor device has a circuit configuration that uses a resistor string to divide the output voltage of a voltage source, the output impedance at the output node of the resistor string changes according to the digital code. As a result, in a circuit that combines a DA converter that uses a resistor to divide the voltage and an inverting amplifier circuit, INL (Integral nonlinearity) deteriorates.

[0263] When the DA converter DAC has a circuit configuration utilizing current branching of the output of the current source circuit 59 by the resistor string as in the semiconductor device of this embodiment, changes in output impedance at the output node of the resistor string RS can be substantially eliminated.

[0264] As a result, the circuit combining the DA converter DAC and the inverting amplifier circuit (driver) DRV in the present embodiment does not cause deterioration in INL.

[0265] Even if the resistance values ​​R2 of the plurality of resistors 55 in the DA converter 205 vary (are uneven) during the manufacturing process, the current Iin and the output voltage Vout are hardly affected. Therefore, in the semiconductor device 1 of the present embodiment, even if the resolution of the DA converter DAC is high, such as 8 bits or more, it is easy to maintain high precision of the DNL (differential non-linearity) of the resistor string RS and the DA conversion circuit 163.

[0266] In addition, since the output voltage Vout of the driver DRV increases according to the value of the code, the resistance value R2 of the resistor 55 can be any value. Therefore, if the resistor 55 has a resistance value that is easy to manufacture according to the manufacturing method, etc., it does not matter even if the resistance value R2 of the resistor 55 is small. Therefore, in the semiconductor device 1 of this embodiment, it is possible to realize the resistor string RS and the DA conversion circuit 163 with a small area.

[0267] As shown in the above-mentioned equations 1 and 2, the current Iin and the output voltage Vout do not depend on the resistance value R2 of the resistor 55 in the resistor string RS.

[0268] Therefore, the resistance value R2 of the resistor 55 can be set independently of the resistance value R1 of the resistor 51 used for the driver (inverting amplifier circuit) DRV. As a result, the semiconductor device 1 of this embodiment can improve the degree of freedom in designing the resistor string RS and the DA conversion circuit 163.

[0269] In the semiconductor device 1 of the present embodiment, the operational amplifier 50 of the driver DRV outputs the output voltage Vout by an inverting amplification operation. Therefore, a wide range of input voltages need not be supplied to the operational amplifier 50. As a result, in the semiconductor device 1 of the present embodiment, the driver DRV is suitable for operation based on a low power supply voltage.

[0270] As described above, the semiconductor device of this embodiment can improve the characteristics of the device.

[0271] (2) Second Embodiment

[0272] Reference Fig.12 , a semiconductor device according to a second embodiment is described.

[0273] Fig.12 1 is a diagram showing a configuration example of a DA converter DAC in a semiconductor device (eg, a storage device) 1 according to the present embodiment.

[0274] like Fig.12 As shown, in this embodiment, the non-inverting input terminal IT2 of the operational amplifier 50 is separated from the resistor string RS.

[0275] The non-inverting input terminal IT2 of the operational amplifier 50 is connected to the voltage node NZ1 . The voltage generating circuit 160 applies the voltage Vc1 to the voltage node NZ1 . Thus, the voltage Vc1 is supplied to the non-inverting input terminal IT2 of the operational amplifier 50 .

[0276] The node NDb of the resistor string RS is connected to the voltage node NZ2. The voltage generating circuit 160 applies a voltage Vc2 to the voltage node NZ2.

[0277] Thus, the voltage Vc2 is supplied to the node NDb of the resistor string RS.

[0278] Each of the voltage Vc1 and the voltage Vc2 is a fixed voltage having a certain voltage value.

[0279] By controlling the magnitude relationship between the voltages Vc1 and Vc2 , the magnitude of the output voltage Vout of the driver DRV can be changed.

[0280] For example, when the voltage value of the voltage Vc2 is lower than the voltage value of the voltage Vc1 , the voltage value of the output voltage Vout increases.

[0281] On the other hand, when the voltage value of the voltage Vc2 is larger than the voltage value of the voltage Vc1 , the voltage value of the output voltage Vout decreases.

[0282] In this embodiment, the current Iin is expressed by the following equation 3.

[0283] Iin=(N / M)×Ir+(Vc1-Vc2) / (M×R2)…(Formula 3)

[0284] Here, "Vc1" indicates the voltage value of the voltage Vc1 supplied to the non-inverting input terminal IT2 of the operational amplifier 50. "Vc2" indicates the voltage value of the voltage Vc2 supplied to the other end of the resistor string RS.

[0285] The output voltage Vout of the driver DRV is expressed by the following equation 4.

[0286] Vout=Vc1+R1×(N / M)×Ir+(R1 / R2)×(Vc1-Vc2) / M…(Formula 4)

[0287] In this way, the magnitude of the output voltage Vout changes according to the voltages Vc1 and Vc2 in addition to the values ​​of “N” and “M” determined by the DA converter DAC.

[0288] With the above configuration, in the present embodiment, the monotonicity of DA conversion in the DA converter DAC is ensured.

[0289] In this embodiment, the rise and fall of the output voltage Vout of the driver DRV can be controlled.

[0290] As described above, the semiconductor device of the present embodiment can improve the characteristics of the semiconductor device, similarly to the first embodiment.

[0291] (3) Third Embodiment

[0292] Reference Fig.13, a semiconductor device according to a third embodiment is described.

[0293] Fig.13 1 is a diagram showing a configuration example of a DA converter DAC of a DA conversion circuit in a semiconductor device (eg, a memory device) 1 according to the present embodiment.

[0294] like Fig.13 As shown, the resistor 56 is connected to a node NDx provided between the driver DRV and the DA converter DAC.

[0295] The node NDx is connected to the inverting input terminal IT1 of the operational amplifier 50 , a node NDa at one end of the resistor string RS, and one end of the resistor body 51 .

[0296] One end of the resistor 56 is connected to the node NDx. ​​The other end of the resistor 56 is connected to the voltage node NZ3. The node NDx is provided between the node ND1 and the node NDa.

[0297] The voltage generating circuit 160 applies the voltage Vr5 to the voltage node NZ3 , thereby supplying the voltage Vr5 to the resistor 56 .

[0298] The resistor 56 has a resistance value R3.

[0299] The magnitude of the output voltage Vout of the driver DRV can be adjusted according to the resistance value R3 of the resistor 56 and the magnitude of the voltage Vr5.

[0300] When the adjustment amount of the output voltage Vout increases, the resistance value R3 decreases. On the other hand, when the adjustment amount of the output voltage Vout decreases, the resistance value R3 increases. For example, when the adjustment amount of the output voltage Vout is small, the resistor 56 having a large resistance value R3 is used. In this case, for example, the resistance value R3 of the resistor 56 is greater than the resistance value R2 of the resistor 51.

[0301] For example, when the adjustment amount of the output voltage Vout is large, the resistance value R3 of the resistor 56 is smaller than the resistance value R2 of the resistor 51 .

[0302] In this embodiment, the current Iin is expressed by the following equation 5.

[0303] Iin=(N / M)×Ir+(Vcenter-Vr5) / R3…(Formula 5)

[0304] In Formula 5, “Vr5” represents the voltage value of voltage Vr5 , and “R3” represents the resistance value R3 of resistor 56 .

[0305] The output voltage Vout of the driver DRV is expressed by the following equation 6.

[0306] Vout=Vcenter+R1×(N / M)×Ir+(R1 / R3)×(Vcenter-Vr5)…(Formula 6)

[0307] according to Fig.13 In the present embodiment, the monotonicity of DA conversion by the DA converter DAC in the DA conversion circuit 163 is ensured.

[0308] In the present embodiment, it is possible to control the rise and fall of the output voltage Vout of the driver DRV in the drive circuit 162 .

[0309] As described above, the semiconductor device of the present embodiment can improve the characteristics of the semiconductor device, similarly to the first embodiment.

[0310] (4) Fourth Embodiment

[0311] Reference Fig.14 as well as Fig.15 , a semiconductor device according to a fourth embodiment is described.

[0312] Fig.14 1 is a diagram showing a configuration example of a DA conversion circuit in a semiconductor device (eg, a storage device) 1 according to the present embodiment.

[0313] like Fig.14 As shown, the resistor string RS may also include a variable resistor (variable resistor element) 57 (57a, 57b).

[0314] The variable resistor 57a is provided at one end of the resistor string RS. For example, the variable resistor 57a is provided at the initial stage of the resistor string RS. One end of the variable resistor 57a is connected to the node NDa (and the node ND1). The other end of the variable resistor 57a is connected to one end of the resistor 55 via the node NDc.

[0315] The variable resistor 57a has a resistance value that is a multiple of 1-α with respect to the resistance value R2 of the resistor 55. The variable resistor 57a has a resistance value of (1-α)R2.

[0316] The variable resistor 57b is provided at the other end side of the resistor string RS. For example, the variable resistor 57b is provided at the final stage of the resistor string RS. One end of the variable resistor 57b is connected to the other end of the resistor 55 via the node NDc. The other end of the variable resistor 57b is connected to the node NDb (and the node ND2).

[0317] The variable resistor 57b has a multiplication factor of α with respect to the resistance value R2 of the resistor 55. The variable resistor 57b has a resistance value of αR2.

[0318] The digital control circuit 191 of the sequencer 190 supplies a control signal (digital signal) Dg to the variable resistors 57a and 57b. The magnitude of the multiplication factor α of the variable resistors 57a and 57b is controlled by the control signal Dg.

[0319] For example, α can take a value in the range from 0 to 0.75. For example, the value of α is represented by a 2-bit digital signal. In this case, the value of α can be set to any one of 0, 0.25, 0.5, and 0.75 according to the value of the digital signal.

[0320] Fig.15 : is an equivalent circuit diagram showing an example of the variable resistor 57 .

[0321] like Fig.15 As shown, the variable resistor 57 includes a plurality of resistors 571 , 572 , 573 , and a plurality of switches SX1 , SX2 , SX3 .

[0322] The plurality of resistors 571, 572, and 573 are connected in series. The number of resistors 571, 572, and 573 is determined by the value of α. Fig.15 In the example of , there are three. One end of the resistor 571 is connected to the node NY1. The other end of the resistor 571 is connected to the node NY2. One end of the resistor 572 is connected to the other end of the resistor 571 via the node NY2. The other end of the resistor 572 is connected to the node NY3. One end of the resistor 573 is connected to the other end of the resistor 572 via the node NY3. The other end of the resistor 573 is connected to the node NY4.

[0323] A plurality of switches SX1, SX2, and SX3 are connected to the resistors 571, 572, and 573. The number of switches SX1, SX2, and SX3 is determined by the value of α. Fig.15 In the example of , there are 3. One end of the switch SX1 is connected to the node NY1. The other end of the switch SX1 is connected to the node NY4. One end of the switch SX2 is connected to the node NY2. The other end of the switch SX2 is connected to the node NY4. One end of the switch SX3 is connected to the node NY3. The other end of the switch SX3 is connected to the node NY4.

[0324] exist Fig.15 The variable resistor 57 is Fig.14 In the case of the variable resistor 57a, the node NY1 is connected to the node NDa, and the node NY4 is connected to the resistor 55 via the node NDc. Fig.15 The variable resistor 57 is Fig.14 In the case of the variable resistor 57b, the node NY1 is connected to the resistor 55 via the node NDc, and the node NY4 is connected to the node NDb via the node NDc.

[0325] The resistors 571, 572, and 573 each have a resistance value R9. For example, the resistance value R9 is equal to one-fourth of the resistance value R2 (R2 / 4). In the variable resistor 57, based on the digital signal Dg, one of the switches SX1, SX2, and SX3 is turned on. As a result, in the variable resistor 57, current is shunted at the position of the switch SX in the turned-on state.

[0326] like Fig.15 In this way, the two variable resistors 57a and 57b including the three resistors 571, 572, and 573 respectively can correspond to the 2-bit digital value included in the code CD.

[0327] In the present embodiment, the monotonicity of DA conversion by the DA converter DAC in the DA conversion circuit 163 is ensured.

[0328] In this embodiment, when the variable resistor 57 is applied to the resistor string RS of the DA converter DAC, the number of resistors 55 in the resistor string RS can be reduced. Therefore, in the semiconductor device 1 of this embodiment, the DA converter DAC can be miniaturized.

[0329] As a result, the semiconductor device 1 of the present embodiment can reduce the area of ​​the circuit including the plurality of DA converters DAC, and accordingly, the semiconductor device 1 of the present embodiment can reduce the manufacturing cost (chip cost) of the semiconductor device.

[0330] (5) Fifth Embodiment

[0331] Reference Fig.16 , a semiconductor device according to a fifth embodiment is described.

[0332] The semiconductor device of the embodiment may be a device other than a storage device. For example, the semiconductor device of the embodiment is a wireless communication device.

[0333] Fig.16 It is a block diagram showing a configuration example of a wireless communication device 1A according to the present embodiment.

[0334] The wireless communication device 1A of this embodiment includes an antenna 700 , a filter 701 , a power amplifier 702 , a multi-band transceiver 703 , and a processor 704 .

[0335] In addition, the wireless communication device 1A of this embodiment includes a storage module 705, an additional wireless communication circuit 706A, an antenna 706B, a camera 707, an input interface 708, a display 709, an audio device 710, a lighting control circuit 711, a light-emitting device (LED) control circuit 712, an audio control circuit 713, etc.

[0336] The antenna 700 receives a radio frequency signal (radio wave) from outside the wireless communication device 1A. The antenna 700 transmits a radio frequency signal generated in the wireless communication device 1A to the outside of the wireless communication device 1A.

[0337] The filter 701 performs various filtering processes on the radio frequency signal supplied from the antenna 700 or the power amplifier 702. For example, the filter 701 can switch (switching) the transmission path and the reception path of the radio frequency signal.

[0338] The power amplifier 702 amplifies the signal transmitted to the outside of the wireless communication device 1A. The power amplifier 702 amplifies the power of the signal from the multi-band transceiver 703. For example, the power amplifier 702 includes the driving circuit 162 and the DA conversion circuit 163 of the above-mentioned embodiment. For example, in the DA conversion circuit 163 used in the power amplifier 702, the current source circuit 59 has Figure 8 , Fig. 9 or Fig.10 Any one of the circuits in .

[0339] The multi-band transceiver 703 performs modulation and demodulation processing on the radio frequency signal. The multi-band transceiver 703 performs demodulation processing on the signal received through the antenna 700. Thus, a baseband signal is extracted from the received signal. The multi-band transceiver 703 performs modulation processing on the baseband signal generated in the wireless communication device 1A. Thus, the modulated signal is transmitted from the antenna 700 to the outside of the wireless communication device 1A via the power amplifier 702 and the filter 701.

[0340] The multi-band transceiver 703 is configured to perform signal processing simultaneously using multiple carrier frequencies through carrier aggregation. For example, the multi-band transceiver performs various signal processing based on various standards of the third-generation mobile communication system such as the WCDMA (registered trademark) (wideband code division multiple access) standard, various standards of the fourth-generation mobile communication system such as the LTE (registered trademark) (long term evolution)-Advanced standard, standards of the fifth-generation mobile communication system, and the sixth-generation mobile communication system.

[0341] The processor 704 performs various calculation processes and control processes in the wireless communication device 1A. The processor 704 includes, for example, a CPU (central processing unit) 719A, a baseband processor 719B, and an application processor 719C.

[0342] The CPU 719A performs control processing related to the entire wireless communication device 1A and various processing related to data.

[0343] The baseband processor 719B performs various controls related to wireless communication, such as signal generation, signal demodulation and modulation control, signal encoding, and frequency shift.

[0344] The application processor 719C manages the software (programs) within the wireless communication device 1A.

[0345] The storage module 705 stores various data for the wireless communication device 1A. The storage module 705 includes a volatile semiconductor memory such as SRAM or DRAM and / or a nonvolatile semiconductor memory such as a flash memory.

[0346] The additional wireless communication circuit 706A performs a wireless communication function used in the wireless communication device 1A as an auxiliary, such as GPS (global positioning system), WLAN (wireless local area network), Bluetooth (registered trademark), etc. The additional wireless communication circuit 706A communicates with a device external to the wireless communication device 1A via the antenna 706B.

[0347] The camera 707 can capture still images and dynamic images (videos). The camera 707 can read one-dimensional codes and two-dimensional codes. For example, the camera 707 includes an image sensor.

[0348] The input interface 708 functions as an input interface for the wireless communication device 1A by the user. For example, the input interface 708 is a touch panel or a keypad. The input interface may also be a keyboard or a mouse.

[0349] The display 709 displays information received by the wireless communication device 1A and information generated by the wireless communication device 1A to the user. The display 709 is, for example, a liquid crystal display such as a touch panel or an organic EL (Electro Luminescence) display.

[0350] The sound device 710 provides the user with sound information received by the wireless communication device 1A and sound information generated by the wireless communication device 1A. The sound device 710 includes a microphone and a speaker.

[0351] The lighting control circuit 711 controls the illumination of the display 709. For example, the lighting control circuit 711 includes the driving circuit 162 and the DA conversion circuit 163 of the above-mentioned embodiment. When the DA conversion circuit 163 is used in the lighting control circuit 711, the current source circuit 59 of the DA converter DAC is used. Figure 8 Circuit 59A or Fig. 9 Circuit 59B.

[0352] The light emitting device (e.g., LED) control circuit 712 controls the light intensity of a light emitting device (e.g., light emitting diode) such as a lamp (not shown) of the wireless communication device 1A. For example, the light emitting device control circuit 712 includes the drive circuit 162 and the DA conversion circuit 163 of the above-mentioned embodiment. When the DA conversion circuit 163 is used in the light emitting device control circuit 712, the current source circuit 59 of the DA converter DAC is used. Figure 8 Circuit 59A or Fig. 9 Circuit 59B.

[0353] The sound control circuit 713 controls the sound signal of the sound device 710. For example, the sound control circuit 713 includes the driving circuit 162 and the DA conversion circuit 163 of the above-mentioned embodiment. When the DA conversion circuit 163 is used in the sound control circuit 713, the current source circuit 59 of the DA converter DAC is preferably used. Fig.10 The circuit 59C enables control of the sound signal by current of positive polarity and current of negative polarity.

[0354] For example, the SIM card 715 is inserted into the slot 714 of the wireless communication device 1A. The SIM card 715 provides the wireless communication device 1A with identification information of a user who uses the wireless communication device 1A.

[0355] The wireless communication device 1A is, for example, a smartphone, a portable information terminal (eg, a tablet device), a notebook PC, or an unmanned aerial vehicle.

[0356] As described above, the DA converter DAC of the DA conversion circuit 163 and the driver DRV of the drive circuit 162 of the above-described embodiment are applied to the wireless communication device 1A as the semiconductor device of the present embodiment.

[0357] The semiconductor device of this embodiment can obtain the same effects as those of the above-mentioned embodiments.

[0358] (6) Sixth Embodiment

[0359] Reference Fig.17 , a semiconductor device according to a sixth embodiment is described.

[0360] The semiconductor device of the embodiment may be an input / output interface circuit. The input / output interface circuit may be a circuit that supports wired communication such as optical or Ethernet (registered trademark), or a circuit that supports wireless communication such as RF.

[0361] Fig.17 1 is a block diagram showing a configuration example of an input / output interface circuit 1B according to the present embodiment.

[0362] exist Fig.17 In the embodiment, the input / output interface circuit (transceiver) 1B is a differential transmission type input / output interface circuit. The input / output interface circuit 1B includes a pair of differential input / output terminals 739A and 739B. The input / output interface circuit 1B receives differential signals IO+ and IO- and transmits differential signals IO+ and IO- via the differential input / output terminals 739A and 739B. The two differential signals IO+ and IO- have a mutually complementary relationship.

[0363] In this embodiment, the two input / output terminals 739A and 739B that form a pair for differential transmission are referred to as a differential input / output terminal pair. A pair of signal lines used for differential transmission in the input / output interface circuit 1B is referred to as a differential transmission path.

[0364] The input-output interface circuit 1B includes an analog-to-digital conversion circuit (AD conversion circuit) 720, a resistor-capacitor circuit 722A, 722B, a capacitor circuit 723A, 723B, a digital-to-analog conversion circuit (DA conversion circuit) 724, a current sink circuit 725, a clock phase adjustment circuit 726, a control clock generation circuit 727, an input monitor 728, an input-output monitor 729, a PVT monitor 730, a global bias generation circuit 731, bias generation circuits 732, 733, and an input-output control circuit 734, etc.

[0365] The AD conversion circuit 720 receives the differential signals IO+ and IO- input to the input-output interface circuit 1B via the resistor-capacitor circuits (RC circuits) 722A and 722B. The AD conversion circuit 720 receives the reference signals IOMVR+ and IOMVR- from the bias generation circuit 732. The AD conversion circuit 720 converts the signals IO+ and IO- from analog signals to digital signals using the reference signals IOMVR+ and IOMVR-.

[0366] For example, the AD conversion circuit 720 includes the driving circuit 162 and the DA conversion circuit 163 of the above-mentioned embodiment. For example, when the AD conversion circuit 720 has a circuit configuration of a successive approximation type, the AD conversion circuit 720 includes a DA conversion circuit, a comparison circuit, and a control circuit. The DA conversion circuit 163 of the embodiment is used for the DA conversion circuit of the AD conversion circuit 720 of the successive approximation type.

[0367] RC circuits (hereinafter, also referred to as RC networks) 722A and 722B are provided to correspond to input / output terminals 739A and 739B, respectively. RC circuit 722A is connected to the signal path of input / output terminal 739A. RC circuit 722B is connected to the signal path of input / output terminal 739B. RC circuits 722A and 722B control the time constant associated with the supplied signal. RC circuits 722A and 722B are circuits composed of resistors and capacitors and can be designed (programmed) after installation.

[0368] Capacitor circuits 723A and 723B are provided between RC circuits 722A and 722B and DA conversion circuit 724. Capacitor circuit 723A is connected to RC circuit 722A. Capacitor circuit 723B is connected to RC circuit 722B. Capacitor circuits 723A and 723B include a plurality of capacitors. Capacitor circuits 723A and 723A smooth signals.

[0369] The DA conversion circuit 724 receives the digital signal and receives the reference signals IOMVR+ and IOMVR− from the offset generation circuit 732 .

[0370] The DA conversion circuit 724 generates an analog signal IODACOUT+ and an analog signal IODACOUT- based on the received digital signal and the reference signals IOMVR+ and IOMVR-. The two analog signals IODACOUT+ and IODACOUT- are signals that complement each other.

[0371] The DA conversion circuit 724 transmits the generated analog signals IODACOUT+ and IODACOUT− to the input / output terminals 739A and 739B via the capacitor circuit 723 and the RC circuit 722 . The DA conversion circuit 724 transmits the analog signals IODACOUT+ and IODACOUT− to the current sink circuit 725 .

[0372] The signals IODACOUT+ and IODACOUT− are output to the outside of the input / output interface circuit 1B as differential signals IO+ and IO−.

[0373] The DA converter circuit 724 includes the drive circuit 162 and the DA converter circuit 163 of the above embodiment. The DA converter circuit 724 generates analog signals IODACOUT+ and IODACOUT− from the digital signal and the reference signals IOMVR+ and IOMVR− using the drive circuit 162 and the DA converter circuit 163 of the above embodiment.

[0374] For example, the DA conversion circuit 724 generates the analog signal IODACOUT+ and the analog signal IODACOUT- using two DA conversion circuits 163. Alternatively, the DA conversion circuit 724 generates a pair of analog signals IODACOUT- by inverting and amplifying the analog signal IODACOUT+ generated by one DA conversion circuit 163 using an operational amplifier.

[0375] The current sink circuit 725 controls the magnitude of the current flowing through the input / output terminal 739 and the signal line within an allowable range based on the specification of the input / output interface circuit 1B. For example, the current sink circuit 725 includes the drive circuit 162 and the DA conversion circuit 163 of the above-described embodiment.

[0376] The clock phase adjustment circuit 726 adjusts the phase of the reference clock signal to generate various clock signals for the input / output interface circuit 1B.

[0377] The control clock generation circuit 727 generates a control clock for the AD conversion circuit 720 and the input / output monitor 729 .

[0378] The input monitor 728 monitors the signals IO+ and IO− at the input / output terminals 739A and 739B.

[0379] The input / output monitor 729 monitors a plurality of clock signals from the control clock generation circuit 727 .

[0380] The PVT monitor 730 monitors various bandgap voltages and bias voltages in the input / output interface circuit 1B. The bandgap voltage is a voltage (reference voltage) that serves as a reference for the voltage amplitude of a signal. The bias voltage is a voltage used for the operation of each circuit block in the input / output interface circuit 1B.

[0381] The global bias generation circuit 731 generates a main bias voltage for each circuit block in the input / output interface circuit 1B.

[0382] The bias generation circuit 732 generates a voltage that serves as a reference for the bias voltage (bias signal) of the AD conversion circuit 720 and the DA conversion circuit 724. The bias generation circuit 732 includes, for example, the drive circuit 162 and the DA conversion circuit 163 of the above-mentioned embodiment. The bias generation circuit 732 generates a voltage that serves as a reference for the bias voltage (bias signal) based on a control signal received from the input / output control circuit 734 using the drive circuit 162 and the DA conversion circuit 163 of the above-mentioned embodiment.

[0383] The bias generation circuit 733 generates a bias voltage for the AD conversion circuit 720 and the input / output control circuit 734 .

[0384] The input / output control circuit 734 generates a control signal for each circuit block in the input / output interface circuit 1B. The input / output control circuit 734 supplies the generated control signal to each circuit block.

[0385] As described above, the DA converter DAC of the DA conversion circuit 163 and the driver DRV of the drive circuit 162 of the above-described embodiment are applied to the input / output interface circuit 1B as the semiconductor device of the present embodiment.

[0386] Therefore, the semiconductor device of this embodiment can obtain the same effects as those of the above-mentioned embodiments.

[0387] (7) Seventh Implementation Method

[0388] Reference Fig.18 , a semiconductor device according to a seventh embodiment is described.

[0389] The semiconductor device according to the embodiment may be a microcontroller.

[0390] Fig.18 It is a block diagram showing a configuration example of a microcontroller 1C according to the present embodiment.

[0391] The microcontroller 1C of this embodiment includes a system on chip (SoC), a system in package (SIP), and a system on package (SoP). The microcontroller 1C is used in an embedded system. For example, the microcontroller 1C of this embodiment is a vehicle-mounted device. However, the microcontroller 1C can also be used in home appliances, computers, industrial machinery, railway vehicles, aircraft, and ships.

[0392] Microcontrollers 1C are classified based on bus width, memory structure, command set, etc. Bus width indicates the size of a data bus. For example, microcontrollers 1C are classified as 8-bit microcontrollers, 16-bit microcontrollers, or 32-bit microcontrollers based on bus width. Microcontrollers 1C can achieve better performance through a high bus width.

[0393] like Fig.18 As shown, the microcontroller 1C includes a processor 750, a bus 751, a bus control circuit 752, storage devices 753, 754, a DA conversion circuit 755, an AD conversion circuit 756, a timer 757, an input / output (I / O) port 758, an oscillator 759, and an interrupt controller 760, etc.

[0394] The processor 750 executes various processes in the microcontroller 1C. The processor 750 performs various processes on supplied data. The processor 750 is, for example, a CPU.

[0395] The bus 751 is connected to the processor 750, the bus control circuit 752, the storage devices 753 and 754, the DA conversion circuit 755, the AD conversion circuit 756, the timer 757, and the input / output port 758. The bus 751 is a transmission path for signals and data in the microcontroller 1C.

[0396] The bus control circuit 752 controls the bus 751. The bus control circuit 752 may also be disposed in the processor 750.

[0397] The storage device 753 stores data in a nonvolatile manner. The storage device 753 is, for example, a NOR flash memory. For example, the NOR flash memory as the storage device 753 includes the drive circuit 162 and the DA conversion circuit 163 of the above-mentioned embodiment. In addition, the storage device 753 may also be the above-mentioned NAND flash memory.

[0398] The storage device 754 temporarily stores data. The storage device 753 is a random access memory such as SRAM or DRAM. For example, the random access memory as the storage device 753 includes the drive circuit 162 and the DA conversion circuit 163 of the above-mentioned embodiment.

[0399] The DA conversion circuit 755 converts a digital signal (digital value) into an analog signal (analog value). For example, the DA conversion circuit 755 includes the drive circuit 162 and the DA conversion circuit 163 of the above-described embodiment.

[0400] The AD conversion circuit 756 converts the analog signal into a digital signal. For example, the AD conversion circuit 756 includes the drive circuit 162 and the DA conversion circuit 163 of the above-mentioned embodiment.

[0401] The timer 757 manages the time (operation timing) within the microcontroller 1C.

[0402] The input / output port 758 functions as a data interface circuit in the microcontroller 1C. The input / output port 758 includes, for example, four ports P1, P2, P3, and P4. The number of ports of the input / output port 758 may be 3 or less, or 5 or more.

[0403] The input / output port 758 receives data, addresses, and signals from outside the microcontroller 1C via the ports P1, P2, P3, and P4, and transmits data and signals to outside the microcontroller 1C via the ports P1, P2, P3, and P4.

[0404] For example, the input / output port 758 includes an interface based on the GPIO (General purpose input / output) standard, the USART (Universal synchronous / asynchronous receiver transmitter) standard, or the I2C (Inter-integrated circuit) standard.

[0405] For example, the input / output port 758 includes the driving circuit 162 and the DA conversion circuit 163 of the above-described embodiment.

[0406] The oscillator 759 outputs a clock signal as a synchronization signal to the processor 750. The clock signal has a certain period (number of clocks). Thus, the processor 750 performs various processes at a timing synchronized with the clock signal. The period of the clock signal is, for example, 4 MHz, 8 MHz, 12 MHz, or 24 MHz.

[0407] The interrupt controller 760 receives an external interrupt command. For example, the interrupt controller 760 has a register for managing the state of the interrupt request.

[0408] The interrupt controller 760 sends various interrupt requests to the processor 750 based on the received external interrupt command. The processor 750 temporarily interrupts the processing in progress according to the interrupt request and performs the processing of the interrupt request. After the processing of the interrupt request is completed, the processor 750 restarts the processing in the interrupt.

[0409] As described above, the DA converter DAC of the DA conversion circuit 163 and the driver DRV of the drive circuit 162 of the above-described embodiment are applied to the microcontroller 1C as the semiconductor device of the present embodiment.

[0410] Therefore, the semiconductor device of this embodiment can obtain the same effects as those of the above-mentioned embodiments.

[0411] (8) Others

[0412] The semiconductor device 1 of the embodiment is not limited to the various devices described above. For example, the semiconductor device 1 of the embodiment may also be a random access memory, a read-only memory, an image sensor, an ASIC (application specific integrated circuit), a processor, or the like.

[0413] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: An operational amplifier having a first input terminal, a second input terminal, and an output terminal, and outputting a first voltage from the output terminal; a first resistor having one end connected to the first input terminal and the other end connected to the output terminal; a plurality of second resistors having one end connected to the first input terminal and connected in series; a plurality of switches, each having one end connected to the first node between two adjacent resistors of the plurality of second resistors and the other end connected to the second node, and receiving a digital code; as well as A current source circuit is connected between the second node and the third node. One of the plurality of switches is turned on based on the digital code, The current source circuit allows the first current to flow from a part or all of the plurality of second resistors to the third node via the one switch in an on state.

2. The semiconductor device according to claim 1, The second input terminal is connected to the other ends of the plurality of second resistors.

3. The semiconductor device according to claim 1, The first voltage is determined based on N and M. The M is the number of the plurality of second resistors.

4. The semiconductor device according to claim 3, The N represents a value of the digital code assigned to a switch set to an on state among the plurality of switches.

5. The semiconductor device according to claim 3, The N represents the number of resistors among the plurality of second resistors that are not present between the one end of the plurality of second resistors and the switch in the on state.

6. The semiconductor device according to claim 3, The N represents the number of resistors existing between the other ends of the plurality of second resistors and the switches in the on state.

7. The semiconductor device according to claim 3, The plurality of second resistors include a plurality of connection nodes, The N is a value indicating a position of a connection node connected to the current source circuit via an on-state switch among the plurality of connection nodes.

8. The semiconductor device according to claim 2, The first voltage is represented by the following formula A: Vout=Vcenter+R1×(N / M)×Ir…(Formula A) Here, M represents the number of the plurality of second resistors, N represents the number of the second resistors among the plurality of second resistors that are not between the one end of the plurality of second resistors and the switch in the on state, Vcenter represents the voltage supplied to the second input terminal, R1 represents the resistance value of the first resistor, and Ir represents the first current.

9. The semiconductor device according to claim 1, The second input terminal is connected to a first voltage node to which a second voltage is supplied. The other ends of the plurality of second resistors are electrically separated from the first voltage node and connected to a second voltage node to which a third voltage is supplied.

10. The semiconductor device according to claim 9, The first voltage is expressed by the following formula B: Vout=Vc1+R1×(N / M)×Ir+(R1 / R2)×(Vc1-Vc2) / M…(Formula B) Here, M represents the number of the plurality of second resistors, N represents the number of second resistors among the plurality of second resistors that are not between the one end of the plurality of second resistors and the switch in the on state, Vc1 represents the voltage value of the second voltage, Vc2 represents the voltage value of the third voltage, R1 represents the resistance value of the first resistor, R2 represents the resistance value of one resistor among the plurality of second resistors, and Ir represents the first current.

11. The semiconductor device according to claim 1, The semiconductor device further comprises: A third voltage node is supplied with a fourth voltage; and The third resistor is connected between the first input terminal and the third voltage node.

12. The semiconductor device according to claim 11, The first voltage is represented by the following formula C: Vout=Vcenter+R1×(N / M)×Ir+(R1 / R3)×(Vcenter-Vr5)…(Formula C) Here, M represents the number of the plurality of second resistors, N represents the number of the second resistors among the plurality of second resistors that are not between the one end of the plurality of second resistors and the switch in the on state, Vcenter represents the voltage supplied to the second input terminal, R1 represents the resistance value of the first resistor, R3 represents the resistance value of the third resistor, Vr5 represents the fourth voltage, and Ir represents the first current.

13. The semiconductor device according to claim 1, The resistor at one end of the plurality of second resistors is a first variable resistor, The resistor at the other end of the plurality of second resistors is a second variable resistor. The first variable resistor has a variable rate of 1-α with respect to the resistance value of one of the plurality of second resistors. The second variable resistor has a variable rate of α with respect to the resistance value of one of the second resistors.

14. The semiconductor device according to claim 1, The current source circuit causes a current having a unidirectional polarity to flow.

15. The semiconductor device according to claim 1, The current source circuit causes a current having bipolarity to flow.

16. The semiconductor device according to claim 1, The semiconductor device further includes a communication circuit for transmitting and receiving wireless signals.

17. The semiconductor device according to claim 1, The semiconductor device further includes an input and output terminal pair for differential transmission.

18. The semiconductor device according to claim 1, The semiconductor device further includes a processor that processes data supplied via the port and performs interrupt processing supplied from the outside.

19. A storage device comprising: A storage unit for storing data; and a voltage generating circuit for generating a voltage for operating the memory cell; The voltage generating circuit comprises: An operational amplifier having a first input terminal, a second input terminal, and an output terminal, and outputting a first voltage from the output terminal; a first resistor having one end connected to the first input terminal and the other end connected to the output terminal; a plurality of second resistors having one end connected to the first input terminal and connected in series; a plurality of switches, each having one end connected to the first node between two adjacent resistors of the plurality of second resistors and the other end connected to the second node, and receiving a digital code; and A current source circuit is connected between the second node and the third node. One of the plurality of switches is turned on based on the digital code, The current source circuit allows the first current to flow from a part or all of the plurality of second resistors to the third node via the one switch in an on state.

20. The storage device according to claim 19, The storage device further includes a temperature sensor for measuring the temperature of the storage device. The digital code is a value corresponding to a measurement result of the temperature measured by the temperature sensor.

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