Method and device for monitoring abnormal cutting depth of LED chip and medium
By conducting electrical testing on the wafer of Mini LED chip, we can determine whether the reverse leakage current data is abnormal, and the problem of insufficient cutting depth in the semi-cutting process is solved, and product yield and production efficiency are improved.
Patent Information
- Application Number
- CN202411937536.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-04-11
AI Technical Summary
During the Mini LED chip manufacturing process, the semi-cutting process is affected by equipment deviation and wafer thickness uniformity, resulting in insufficient cutting depth, which affects the authenticity of electrical test data and product yield.
By conducting electrical performance tests on the wafer, the reverse leakage current data is obtained, and it is determined whether the reverse leakage current data of N adjacent grains are all greater than the preset threshold. If so, it is determined that there is an abnormal cutting depth.
Effectively filter out data abnormal slice sources to prevent them from entering subsequent production, improve product yield and quality, avoid resource waste, and improve production efficiency.
Smart Images
Figure CN119795398A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of LED chips, and in particular to a method and device for monitoring abnormal cutting depth of LED chips, and a medium. Background Art
[0002] In the field of red light vertical structure Mini LED chip manufacturing, as the product yield continues to improve, red light LED Mini products are gradually mass-produced. In the manufacturing process of vertical structure Mini LED chips, after the wafer is produced and before it is completely cut into grains, it is necessary to go through an electrical test process (WAT) to monitor whether the wafer manufacturing process is abnormal and whether the product meets the electrical specification requirements. Specifically, before the test, it is necessary to form a cutting groove on the wafer through a one-and-a-half-cutting process (also called a "half-cutting process"), and cut the epitaxial surface to test the product electrical characteristics data, but it cannot be cut through, otherwise it cannot be tested. After the test is completed, the products with qualified test data yield will continue normally to the next process, and the two-knife full-cutting process will be carried out to completely cut the wafer into single grains along the cutting groove.
[0003] However, in actual production, the one-and-a-half-cutting process is affected by factors such as the operating deviation of the cutting equipment and the thickness uniformity of the wafer source itself, which leads to the problem of insufficient half-cut depth in some areas or large areas of the wafer after half-cutting. This directly affects the authenticity of the point measurement data and causes abnormal yield of the point measurement data. In addition, since the yield deviation of the point measurement data varies in size, it is difficult to effectively control it by directly setting the data yield threshold, which makes it easy for abnormal data sources to flow out. When the threshold is set too high, it seriously affects production efficiency. Summary of the invention
[0004] The purpose of the present invention is to provide a method, device and medium for monitoring abnormal cutting depth of LED chips in view of the existing technical status.
[0005] The present invention can effectively determine whether the wafer has abnormal cutting depth, and timely screen out data abnormal sources, so as to timely process the data abnormal sources, effectively control the outflow of data abnormal sources, improve the yield and quality of subsequent products, and avoid the waste of resources caused by the data abnormal sources entering the subsequent production. At the same time, it can avoid the problem of excessively high thresholds affecting production efficiency in the prior art, ensure that normal sources can carry out the subsequent production process in an orderly and normal manner, and the monitoring of abnormal cutting depth can be better integrated into the original production process of the wafer, thereby improving the overall production efficiency of the product.
[0006] In order to achieve the above object, the present invention adopts the following technical scheme:
[0007] In one aspect, the present invention provides a method for monitoring abnormal cutting depth of an LED chip, comprising:
[0008] Providing a wafer, the wafer comprising a substrate and an epitaxial layer disposed on the substrate;
[0009] A first cutting is performed by using a half-cut process to form a plurality of crystal grains and cutting grooves, wherein the crystal grains are arranged in an array and the cutting grooves are arranged between adjacent crystal grains;
[0010] Performing electrical testing on each of the crystal grains to obtain test data, wherein the test data at least includes reverse leakage current data;
[0011] Determine whether the cutting depth of the wafer is abnormal. If the reverse leakage current data corresponding to N adjacent grains are all greater than the preset reverse leakage current threshold, it is determined that the cutting depth of the wafer is abnormal. Otherwise, it is determined that the cutting depth of the wafer is normal, N≥3.
[0012] In some embodiments, the preset reverse leakage current threshold is 1 μA.
[0013] In some embodiments, among the N adjacent grains, at least two of the grains are disposed adjacent to each other in a transverse direction, and at least two of the grains are disposed adjacent to each other in a longitudinal direction.
[0014] In some embodiments, N is 9, and 9 adjacent grains are arranged in a nine-square grid.
[0015] In some embodiments, including:
[0016] After determining that the wafer has an abnormal cutting depth, a second cutting is performed using a half-cut process;
[0017] After determining that the wafer cutting depth is normal, the wafer is cut into a plurality of independent crystal grains along the cutting grooves.
[0018] In some embodiments, the step of determining whether the wafer has an abnormal cutting depth comprises:
[0019] A reverse leakage current MAP diagram is constructed based on the reverse leakage current data and coordinate position information obtained from each of the grains.
[0020] In another aspect, the present invention provides a device for monitoring abnormal cutting depth of an LED chip, comprising:
[0021] A cutting mechanism, used for cutting a wafer, wherein the wafer comprises a substrate and an epitaxial layer disposed on the substrate;
[0022] An initial processing module, used for driving the cutting mechanism to perform a first cutting using a half-cutting process to form a plurality of crystal grains and cutting grooves, wherein the crystal grains are arranged in an array, and the cutting grooves are arranged between adjacent crystal grains;
[0023] A detection module, used to perform electrical testing on each of the die to obtain test data, wherein the test data at least includes reverse leakage current data;
[0024] The judgment module is used to judge whether the cutting depth of the wafer is abnormal. If the reverse leakage current data corresponding to N adjacent grains are all greater than the preset reverse leakage current threshold, it is judged that the cutting depth of the wafer is abnormal. Otherwise, it is judged that the cutting depth of the wafer is normal, N≥3.
[0025] In some embodiments, the preset reverse leakage current threshold is 1 μA;
[0026] The N is 9, and the 9 adjacent crystal grains are arranged in a nine-square grid.
[0027] In some embodiments, including:
[0028] An abnormality processing module, used for driving the cutting mechanism to perform a second cutting using a half-cutting process when the judgment module determines that the cutting depth of the wafer is abnormal;
[0029] The reference processing module is used to drive the cutting mechanism to cut the wafer into a plurality of independent crystal grains along the cutting groove when the judgment module determines that the wafer does not have abnormal cutting depth.
[0030] Furthermore, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.
[0031] The beneficial effects of the present invention are:
[0032] The test found that when the half-cut process is used for the first cutting, if the wafer has a problem of insufficient half-cut depth, the cutting depth abnormality is regional and clustered, that is, the cutting depth abnormality affects at least a part of the continuous area of the grains, rather than just a single, discrete grain. At the same time, the cutting depth abnormality directly affects the reverse leakage current data of the electrical test. When the cutting depth is normal, the reverse leakage current data is usually kept at 0μA~0.1μA range, and when the cutting depth is abnormal, the measured reverse leakage current data increases significantly, and is different from the reverse leakage current data abnormalities caused by other reasons. The reverse leakage current data abnormalities caused by the cutting depth abnormalities also show continuity and aggregation.
[0033] Based on this, in the present invention, after the electrical test, by monitoring whether the reverse leakage current data corresponding to N adjacent grains are all greater than the preset reverse leakage current threshold, it is possible to effectively determine whether the wafer has abnormal cutting depth, and timely screen out the data abnormal chip source, so as to timely process the data abnormal chip source, effectively control the outflow of the data abnormal chip source, improve the yield and quality of the subsequent products, and avoid the waste of resources caused by the data abnormal chip source entering the subsequent production. At the same time, it can avoid the problem of excessively high threshold setting affecting production efficiency in the prior art, ensure that normal chip sources can carry out the subsequent production process in an orderly and normal manner, and the monitoring of abnormal cutting depth can be better integrated into the original production process of the wafer, thereby improving the overall production efficiency of the product. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 The present invention is a flowchart of a method for monitoring abnormal cutting depth of an LED chip according to an embodiment of the present invention.
[0035] Figure 2 The figure is a schematic diagram of the principle of a method for monitoring abnormal cutting depth of an LED chip according to an embodiment of the present invention.
[0036] Figure 3 This is a reverse leakage current MAP diagram of one of the data abnormality chip sources according to an embodiment of the present invention.
[0037] Figure 4 This is a reverse leakage current MAP diagram of another data abnormal chip source according to an embodiment of the present invention.
[0038] Figure 5 This is a reverse leakage current MAP diagram of one of the chip sources with normal data according to an embodiment of the present invention.
[0039] Figure 6 FIG. 4 is a reverse leakage current MAP diagram of another chip source with normal data according to an embodiment of the present invention. DETAILED DESCRIPTION
[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0041] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.
[0042] It should be noted that in this specification, the term "comprising" includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprising..." do not exclude the existence of other identical elements in the process, method, article or device that includes the elements.
[0043] On the one hand, see Figure 1 to Figure 2 As shown, the present invention provides a method for monitoring abnormal cutting depth of LED chips, which can be used for vertical structure chips, comprising:
[0044] S100. Providing a wafer, wherein the wafer includes a substrate and an epitaxial layer disposed on the substrate;
[0045] S200. Performing a first cutting process using a half-cut process to form a plurality of crystal grains and cutting grooves, wherein the crystal grains are arranged in an array, and the cutting grooves are provided between adjacent crystal grains;
[0046] S300. Perform electrical testing on each of the grains to obtain test data, wherein the test data at least includes reverse leakage current data;
[0047] S400. Determine whether the cutting depth of the wafer is abnormal. If the reverse leakage current data corresponding to N adjacent grains are all greater than the preset reverse leakage current threshold, it is determined that the cutting depth of the wafer is abnormal. Otherwise, it is determined that the cutting depth of the wafer is normal, N≥3.
[0048] Exemplarily, N is 3, 4, 5, 6, 7, 8 or 9, but is not limited thereto. The setting of the N value should not be too low, otherwise it is easy to increase the probability of misjudgment, that is, the reverse leakage current data anomaly caused by other reasons is misjudged as being caused by cutting depth anomaly, which is easy to reduce the accuracy of the judgment and affect the subsequent correct processing of the film source.
[0049] The experiment found that when the half-cut process is used for the first cutting, if the wafer has a problem of insufficient half-cut depth, the cutting depth abnormality is regional and clustered, that is, the cutting depth abnormality affects at least a part of the continuous area of the grains, rather than just a single, discrete grain. At the same time, the cutting depth abnormality directly affects the reverse leakage current data (IR) of the electrical test. When the cutting depth is normal, the reverse leakage current data usually remains at 0μA~0.1μA When the cutting depth is abnormal, the measured reverse leakage current data increases significantly. Different from the reverse leakage current data abnormality caused by other reasons, the reverse leakage current data abnormality caused by the cutting depth abnormality also presents continuity and aggregation. Specifically, Figure 5 to Figure 6As shown in the reverse leakage current MAP of the data source, the grains with abnormal reverse leakage current are distributed in a point-like and discrete manner, while Figure 3 to Figure 4 As shown, in the reverse leakage current MAP diagram of the data abnormal chip source caused by the abnormal cutting depth, the grains with abnormal reverse leakage current are distributed in a clustered, regional, and continuous manner. Based on this, in the present invention, after the electrical test, by monitoring whether the reverse leakage current data corresponding to N adjacent grains are all greater than the preset reverse leakage current threshold, it is possible to effectively determine whether the wafer has an abnormal cutting depth, and timely screen out the data abnormal chip source, so as to timely process the data abnormal chip source, effectively control the outflow of the data abnormal chip source, improve the yield and quality of the subsequent products, and avoid the waste of resources caused by the data abnormal chip source entering the subsequent production. At the same time, it can avoid the problem of excessively high threshold setting affecting production efficiency in the prior art, ensure that normal chip sources can carry out the subsequent production process in an orderly and normal manner, and the monitoring of the abnormal cutting depth can be better integrated into the original production process of the wafer, thereby improving the overall production efficiency of the product.
[0050] It can be understood that the N adjacent grains here can be N grains that are adjacent and continuously arranged in the longitudinal direction, or N grains that are adjacent and continuously arranged in the transverse direction, or include N grains that are adjacent and continuously arranged in the longitudinal direction and the transverse direction.
[0051] In some embodiments, the preset reverse leakage current threshold is 1 μA.
[0052] Exemplarily, the preset reverse leakage current threshold is 1 μA, 1.1 μA, 1.15 μA or 1.2 μA, but is not limited thereto.
[0053] If the preset reverse leakage current threshold is too large or too small, the accuracy of determining whether the wafer has abnormal cutting depth will be reduced.
[0054] After testing, when the preset reverse leakage current threshold is set to 1μA, combined with the situation that the reverse leakage current data corresponding to N adjacent grains are all greater than the preset reverse leakage current threshold, the accuracy of determining whether there is an abnormal cutting depth of the wafer can be improved.
[0055] Preferably, the preset reverse leakage current threshold is 1 μA, which can improve the accuracy of determining whether there is an abnormal cutting depth of the wafer.
[0056] In some embodiments, among the N adjacent grains, at least two of the grains are disposed adjacent to each other in a transverse direction, and at least two of the grains are disposed adjacent to each other in a longitudinal direction.
[0057] When there is an abnormality in the wafer cutting depth, taking the insufficient cutting depth of the i-th longitudinal cutting groove as an example, at this time, the two columns of grains on both sides of the cutting groove are affected. Therefore, the judgment condition is set to: among the N adjacent grains, at least two of the grains are arranged adjacent to each other in the horizontal direction, at least two of the grains are arranged adjacent to each other in the longitudinal direction, and the N adjacent grains are all greater than the preset reverse leakage current threshold. This can more accurately and quickly determine whether the wafer has an abnormal cutting depth.
[0058] In some embodiments, see Figure 2 As shown, N is 9, and the 9 adjacent grains are arranged in a nine-square grid.
[0059] After testing, it was found that when the wafer has an abnormal cutting depth, the area of abnormal reverse leakage current is usually larger than the grain array arranged in a nine-square grid. Therefore, the judgment condition is set to: N is 9, and the 9 adjacent grains are arranged in a nine-square grid, and the N adjacent grains are all greater than the preset reverse leakage current threshold. The accuracy and efficiency of determining whether the wafer has an abnormal cutting depth are higher.
[0060] In some embodiments, including:
[0061] S500. After determining that the wafer has an abnormal cutting depth, a second cutting is performed using a half-cut process;
[0062] S600. After determining that the wafer cutting depth is normal, the wafer is cut into a plurality of independent crystal grains along the cutting grooves, that is, the cutting grooves are cut along the cutting grooves until the bottom of the grooves is completely disconnected, and all the crystal grains cut from the entire wafer are cut.
[0063] When it is determined that the wafer has an abnormal cutting depth, the wafer (data abnormality wafer source) is reprocessed and half-cut again to correct the abnormal cutting depth.
[0064] In some embodiments, the equipment-set cutting depth for the second cut (second half cut) is equal to or greater than the equipment-set cutting depth for the first cut (first half cut). For example, the equipment-set cutting depth for the second cut can be set to 1.01 times, 1.05 times, etc., of the equipment-set cutting depth for the first cut, but is not limited to this.
[0065] In some embodiments, after step S500, the following steps are included:
[0066] Conduct electrical testing on the wafers that have been cut for the second time.
[0067] In some embodiments, in step S400, the step of determining whether the wafer has an abnormal cutting depth includes:
[0068] A reverse leakage current MAP diagram is constructed based on the reverse leakage current data and coordinate position information obtained from each of the grains.
[0069] Through the reverse leakage current MAP diagram, it is possible to intuitively determine whether there is an abnormal cutting depth on the wafer, or use the reverse leakage current MAP diagram to identify whether there is an abnormal cutting depth.
[0070] Exemplarily, in one embodiment, the reverse leakage current MAP image is preprocessed, the image corresponding to the reverse leakage current abnormal area is extracted, and the grain array pattern arranged in a nine-square grid is used as a characteristic pattern for identification to determine whether there is a characteristic pattern in the reverse leakage current abnormal area.
[0071] In some embodiments, the test data further includes any one or more of forward voltage, reverse voltage, brightness, peak wavelength, center wavelength and main wavelength.
[0072] In the present invention, the monitoring of the abnormal cutting depth can be well integrated into the original production process of the wafer. Specifically, when determining whether the wafer has an abnormal cutting depth in step S400, it is possible to synchronously detect whether the wafer meets the electrical specifications based on the remaining test data. The steps are as follows:
[0073] S701. Test data is uploaded to the system;
[0074] S702. The system counts the mean and yield of various test data of the wafer;
[0075] S703. Set a data filtering threshold, and determine whether each test data is qualified based on the data filtering threshold.
[0076] Exemplarily, the following are the threshold settings for each test data:
[0077]
[0078] In another aspect, the present invention provides a device for monitoring abnormal cutting depth of an LED chip, comprising:
[0079] A cutting mechanism, used for cutting a wafer, wherein the wafer comprises a substrate and an epitaxial layer disposed on the substrate;
[0080] An initial processing module, used for driving the cutting mechanism to perform a first cutting using a half-cutting process to form a plurality of crystal grains and cutting grooves, wherein the crystal grains are arranged in an array, and the cutting grooves are arranged between adjacent crystal grains;
[0081] A detection module, used to perform electrical testing on each of the die to obtain test data, wherein the test data at least includes reverse leakage current data;
[0082] The judgment module is used to judge whether the cutting depth of the wafer is abnormal. If the reverse leakage current data corresponding to N adjacent grains are all greater than the preset reverse leakage current threshold, it is judged that the cutting depth of the wafer is abnormal. Otherwise, it is judged that the cutting depth of the wafer is normal, N≥3.
[0083] In some embodiments, the preset reverse leakage current threshold is 1 μA;
[0084] The N is 9, and the 9 adjacent crystal grains are arranged in a nine-square grid.
[0085] In some embodiments, including:
[0086] An abnormality processing module, used for driving the cutting mechanism to perform a second cutting using a half-cutting process when the judgment module determines that the cutting depth of the wafer is abnormal;
[0087] The reference processing module is used to drive the cutting mechanism to cut the wafer into a plurality of independent crystal grains along the cutting groove when the judgment module determines that the wafer does not have abnormal cutting depth.
[0088] Furthermore, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.
[0089] In the description of this specification, the description with reference to the terms "some embodiments", "exemplary", "example", or "for example" means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0090] The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with the field can make some changes or modify the technical contents suggested above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the solution of the present invention.
Claims
1. A method for monitoring abnormal cutting depth of LED chips, characterized in that: include: Providing a wafer, the wafer comprising a substrate and an epitaxial layer disposed on the substrate; A first cutting is performed by using a half-cut process to form a plurality of crystal grains and cutting grooves, wherein the crystal grains are arranged in an array and the cutting grooves are arranged between adjacent crystal grains; Performing electrical testing on each of the crystal grains to obtain test data, wherein the test data at least includes reverse leakage current data; Determine whether the cutting depth of the wafer is abnormal. If the reverse leakage current data corresponding to N adjacent grains are all greater than the preset reverse leakage current threshold, it is determined that the cutting depth of the wafer is abnormal. Otherwise, it is determined that the cutting depth of the wafer is normal, N≥3.
2. The LED chip cutting depth abnormality monitoring method according to claim 1, characterized in that: The preset reverse leakage current threshold is 1 μA.
3. The LED chip cutting depth abnormality monitoring method according to claim 1, characterized in that: Among the N adjacent crystal grains, at least two of the crystal grains are arranged adjacent to each other in a transverse direction, and at least two of the crystal grains are arranged adjacent to each other in a longitudinal direction.
4. The LED chip cutting depth abnormality monitoring method according to claim 1, characterized in that: The N is 9, and the 9 adjacent crystal grains are arranged in a nine-square grid.
5. The LED chip cutting depth abnormality monitoring method according to claim 1, characterized in that: include: After determining that the wafer has an abnormal cutting depth, a second cutting is performed using a half-cut process; After determining that the wafer cutting depth is normal, the wafer is cut into a plurality of independent crystal grains along the cutting grooves.
6. The LED chip cutting depth abnormality monitoring method according to claim 1, characterized in that: The step of determining whether the wafer has an abnormal cutting depth comprises: A reverse leakage current MAP diagram is constructed based on the reverse leakage current data and coordinate position information obtained from each of the grains.
7. A device for monitoring abnormal cutting depth of LED chips, characterized in that: include: A cutting mechanism, used for cutting a wafer, wherein the wafer comprises a substrate and an epitaxial layer disposed on the substrate; An initial processing module, used for driving the cutting mechanism to perform a first cutting using a half-cutting process to form a plurality of crystal grains and cutting grooves, wherein the crystal grains are arranged in an array, and the cutting grooves are arranged between adjacent crystal grains; A detection module, used to perform electrical testing on each of the die to obtain test data, wherein the test data at least includes reverse leakage current data; The judgment module is used to judge whether the cutting depth of the wafer is abnormal. If the reverse leakage current data corresponding to N adjacent grains are all greater than the preset reverse leakage current threshold, it is judged that the cutting depth of the wafer is abnormal. Otherwise, it is judged that the cutting depth of the wafer is normal, N≥3.
8. The LED chip cutting depth abnormality monitoring device according to claim 7, characterized in that: The preset reverse leakage current threshold is 1 μA; The N is 9, and the 9 adjacent crystal grains are arranged in a nine-square grid.
9. The LED chip cutting depth abnormality monitoring device according to claim 7, characterized in that: include: An abnormality processing module, used for driving the cutting mechanism to perform a second cutting using a half-cutting process when the judgment module determines that the cutting depth of the wafer is abnormal; The reference processing module is used to drive the cutting mechanism to cut the wafer into a plurality of independent crystal grains along the cutting groove when the judgment module determines that the wafer does not have abnormal cutting depth.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.