Flow-adaptive power system fault recording data acquisition method

Abstract

The invention relates to the technical field of electric power automation, and discloses a flow-adaptive electric power system fault recording data acquisition method. Each channel port of the FPGA receives the message, analyzes and processes the message, adds an FPGA Header, and stores the message in each port receiving buffer area; an FPGA data receiving engine reads messages frame by frame and writes the messages into a DDR3 circular buffer area according to the time sequence of message receiving completion of each channel port in a speed and bit width multiplying polling mode, and a data block which does not exceed 8000 bytes is formed; and an FPGA data sending engine adopts a flow self-adaptive mechanism, reads data blocks from the DDR3 memory, and sends the data blocks to an upper computer in a gigabit network huge frame DMA (Direct Memory Access), so that efficient transmission between the FPGA and the upper computer is realized.

Description

Technical Field

[0001] The invention relates to the technical field of electric power automation, and in particular to a flow-adaptive electric power system fault recording data acquisition method. Background Art

[0002] In the power system, fault recording data is mainly used to record the operating data of the power system, especially the data under fault or abnormal conditions. It transmits the data of changes in various electrical quantities before and after the fault in real time and efficiently, which is important for analyzing and handling accidents, judging whether the protection is operating correctly, and improving the safe operation level of the power system.

[0003] However, the amount of fault recording data in the power system is large, and the types of data collected are various, including analog quantity, switch quantity, process layer and station control layer data, especially when using digital analog signals, such as the IEC 61850-9-2 standard defines sampled value (SV) and generic object oriented substation event (GOOSE). The fault recorder needs to process this data in real time and efficiently so that timely measures can be taken.

[0004] At the same time, the fault recording data of the power system has a great burstiness, and the data volume is small most of the time. Only when a fault occurs will there be a large amount of data. If the sampled data is simply sent directly without making a balanced distinction, the transmission bandwidth utilization rate is not high, the data throughput is limited, and it will cause the host computer CPU occupancy rate to be high and the efficiency of receiving data to be low. Therefore, there is an urgent need for a real-time and flow-adaptive recording data acquisition method. Summary of the invention

[0005] In view of the above problems existing in the prior art, the present invention is proposed.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions: a flow-adaptive power system fault recording data acquisition method, comprising: after each Ethernet port of FPGA receives the Ethernet message and parses it, the FPGAHeader is added and then stored in the receiving buffer of each port; the FPGA data receiving engine adopts a double frequency and double bit width polling method to effectively improve the bandwidth and real-time performance of data receiving and sending, and realizes reading the message frame by frame and writing it into the DDR3 circular buffer according to the time sequence of the completion of message reception of each Ethernet port, and forming a data block; the FPGA data sending engine adopts a flow-adaptive mechanism to read the data block from the DDR3 memory, and send it to the host computer through the gigabit network port in jumbo frame DMA;

[0007] As a preferred solution of the flow-adaptive power system fault recording data acquisition method described in the present invention, wherein: the Ethernet message received by each Ethernet port of the FPGA includes the total frame length, message length, CRC, large and small packet flags, seconds, nanoseconds and tick counts;

[0008] The clock contained in the FPGAHeader is a clock that has been synchronized with the GPSB code. The FPGAHeader and message data of each port message are stored separately in two FIFO buffers.

[0009] As a preferred solution of the flow-adaptive power system fault recording data acquisition method described in the present invention, wherein: the FPGA data receiving engine adopts a high-speed and high-bit-width polling method, polls according to each Ethernet port ID, and reads a frame of messages each time according to the message receiving time sequence, and writes them frame by frame into the DDR3 memory, and the DDR3 memory is equally divided into N ring-shaped 8000-byte storage blocks, which are written cyclically;

[0010] The data receiving engine receives the messages from each Ethernet port by polling, including the following steps:

[0011] Initialize variables, including the number of FPGA receiving data channels; the current channel ID number, which is initially 0; reset the Data FIFO and Header FIFO of the receiving buffer of each channel port to 0, and the Data FIFO and Header FIFO empty flags to 1;

[0012] Each channel port of FPGA receives the message and writes it into the buffer. FPGA parses and extracts the complete message data and writes it into DataFIFO (message data buffer). After receiving a single frame message, the FPGA Header information of the current frame message is written into Header FIFO (message data information buffer). The empty flags of Data FIFO and Header FIFO are automatically set to non-zero.

[0013] The FPGA data receiving engine detects the status of each channel buffer in real time. If the Header FIFO of a channel is not empty, it polls to read the data of each channel. If all the Header FIFOs of the channels are empty, it waits.

[0014] The polling and reading of data from each channel includes: firstly, detecting and judging whether the Header FIFO of the current CHAN_ID channel is not empty, and if it is not empty, reading a piece of FPGA Header information from the Header FIFO, and reading the corresponding message data from the DATA FIFO according to the information and writing it into the DDR circular buffer, and at the same time, switching CHAN_ID+1 to the next channel; if the Header FIFO of the previous CHAN_ID channel is empty, switching CHAN_ID+1 to the next channel; if (CHAN_ID+1)≥N (N is the number of data channels), all channels are polled once, switching to the channel CHAN_ID=0, and repeating the polling process to realize real-time polling reception of data;

[0015] The frequency doubling and bit width doubling include: the sending engine logic uses X times the data channel frequency clock X*f clk The data buffer of each data channel uses Y times the data channel width Y*B. width , then the sending engine read bandwidth is expressed as:

[0016] Bandwith=X*f clk *Y*B width

[0017] The overall bandwidth is X*Y times that of a single data channel, thus achieving high-throughput polling reading, improving the real-time performance of data reception, and ensuring reading in the order in which messages are received.

[0018] The data channel includes an external receiving network port channel and an internal direct acquisition channel;

[0019] In the receiving mode, each channel port of FPGA adopts FIFO buffer for receiving. Its first-in-first-out characteristic ensures that the data receiving engine reads the message data of the same channel port in the order of message reception completion. At the same time, it adopts high-throughput polling and only reads one frame of message in each polling. This ensures that the FPGA data receiving engine reads the message data of different channel ports basically in the order of the time when each port completes receiving the message, thus ensuring the real-time nature of the data.

[0020] As a preferred solution of the flow-adaptive power system fault recording data acquisition method described in the present invention, wherein: the flow-adaptive mechanism includes: when the flow is high, the 8000-byte data block is sent to the host computer in real time through the gigabit network port in Ethernet jumbo frames; when the flow is low, the actual data length is delayed and sent to the host computer through the gigabit network; when the flow is low, the maximum framing time is configured through the CPU interface, which ensures real-time performance while effectively improving the data receiving efficiency of the host computer;

[0021] The sending engine adopts the traffic adaptive sending mechanism mainly by limiting the framing waiting time of the DDR3 buffer data block, including the following steps:

[0022] DDR3 is divided into A ring buffer data block ID numbers, the initial value is 0, and the value range is [0, A-1];

[0023] The maximum framing time of the 8000-byte ring buffer is initially 50ms. The user can configure and adjust it in real time through the register interface provided by the FPGA to the CPU.

[0024] The total number of bytes written into the current buffer block is initially 0. At the same time, the TX_ENG Header FIFO buffer storing the information of each data block to be sent is reset to 0, and the empty flag is 1. The FPGA data receiving engine uses polling to read the data of each channel, one frame at a time. Read the FPGA Header of the current frame message of the current channel and extract the message length information pkt_length.

[0025] When the FPGA data receiving engine starts writing the first frame of message data in the current DDR3 cyclic data block, it starts a timer wait_time_cnt. When the timer value exceeds the maximum allowed value of framing waiting, that is, wait_time_cnt>max_wait_time, the current traffic volume is low traffic, and the 8000-byte framing times out. When the buffer write is idle, the data receiving engine ends the framing of the current buffer data block and switches to the next cyclic data block ddr_blk_id+1; and writes the current buffer data block ID and the total length of the data into the sending engine TX_ENG Header FIFO buffer;

[0026] If pkt_length (the current length of the message to be written) + total_byte_num (the length of the message written into the buffer) < 8000, the current buffer block has sufficient remaining space, write the frame message into the current circular buffer, and update the total number of bytes written into the current buffer, total_byte_num, to pkt_length + total_byte_num;

[0027] If pkt_length+total_byte_num≥8000, the remaining space of the current buffer block is insufficient, the current buffer data block framing ends, and switches to the next cyclic data block ddr_blk_id+1; and the current buffer data block ID and total data length are written into the sending engine to send the data block Header information TX_ENG Header FIFO buffer;

[0028] The FPGA data transmission engine detects the empty flag status of the TX_ENG Header FIFO buffer of the data block information to be sent by the transmission engine in real time. If it is not empty, it immediately reads a piece of data information from the TX_ENG Header FIFO buffer of the data block information to be sent, and reads data from the corresponding DDR3 circular buffer according to the circular buffer block ID and data length provided by the data information, and transmits it to the host computer through the gigabit network jumbo frame;

[0029] This sending method realizes traffic adaptive sending by limiting the framing time of DDR3 cyclic data blocks. When the data flow is high, the FPGA data receiving engine quickly completes the framing of the 8000-byte data block and hands it over to the FPGA data sending engine for real-time uploading via the gigabit network jumbo frame. When the data flow is low, the FPGA data receiving engine needs to wait to complete the framing of the 8000-byte data block. If the maximum allowed framing time is exceeded, the framing is stopped and the data block is directly handed over to the FPGA data sending engine for uploading via the gigabit network. This uploading method improves the utilization rate of the gigabit network bandwidth and avoids frequent response processing of the host computer, thereby realizing adaptive sending processing of different data flows and effectively improving data transmission performance.

[0030] The beneficial effects of the present invention are as follows: the present invention is based on a configurable data flow adaptive DMA sending mechanism, which effectively avoids frequent response processing of the host computer and improves the CPU performance of the host computer; based on a double-frequency and double-bit-width data polling receiving method, high-throughput polling reading is achieved, the real-time performance of data reception is improved, and reading is ensured in the order of message reception; this method effectively improves the fault recording data transmission efficiency and improves the performance of the fault recorder. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0032] Figure 1 A schematic diagram of the overall architecture of a flow-adaptive power system fault recording data collection method provided by an embodiment of the present invention.

[0033] Figure 2 A data transmission control flow chart of a flow-adaptive power system fault recording data acquisition method provided by an embodiment of the present invention.

[0034] Figure 3 A schematic diagram of an FPGA network port receiving buffer of a flow-adaptive power system fault recording data acquisition method provided by an embodiment of the present invention.

[0035] Figure 4 A schematic diagram of FPGA sending engine polling reception of a flow-adaptive power system fault recording data acquisition method provided by an embodiment of the present invention.

[0036] Figure 5 A schematic diagram of DDR3 circular buffer reading and writing of a flow-adaptive power system fault recording data acquisition method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0038] Example 1

[0039] Reference Figure 1-Figure 5 , which is the first embodiment of the present invention, and provides a flow-adaptive power system fault recording data acquisition method, comprising:

[0040] The fault recording data of the power system has a great burstiness, and the data volume is small most of the time. Only when a fault occurs will there be a large amount of data. If the sampled data is simply sent directly without making a balanced distinction, the transmission bandwidth utilization rate is not high, the data throughput is limited, and it will cause the host computer CPU occupancy rate to be high and the efficiency of receiving data to be low. The present invention adopts a configurable data flow adaptive DMA sending mechanism, which effectively avoids the frequent response processing of the host computer and improves the CPU performance of the host computer; based on the double-frequency double-bit width data polling reception method, high-throughput polling reading is achieved, the real-time performance of data reception is improved, and the reading is guaranteed in the order of message reception; this method effectively improves the fault recording data transmission efficiency, throughput and real-time performance, and improves the performance of the fault recorder.

[0041] Specifically include:

[0042] After receiving the Ethernet message at each channel port of FPGA, it parses it, adds the FPGA Header and stores it in the receiving buffer of each port;

[0043] The FPGA data receiving engine adopts a high-speed and high-bit-width polling method. It reads the messages frame by frame and writes them into the DDR3 memory according to the time sequence of the message reception completion of each channel port, and forms a data block of no more than 8000 bytes;

[0044] The FPGA data transmission engine adopts a traffic adaptive mechanism to read data blocks from the DDR3 memory and send them to the host computer in jumbo frames through the Gigabit network port.

[0045] Figure 1 This is a schematic diagram of the overall system architecture, which mainly includes 14 100M Ethernet ports, 2 Gigabit Ethernet ports and 1 internal direct acquisition directly controlled by FPGA. The storage uses external DDR3 memory, provides CPU interaction interface, uses GPS B code for time calibration, and uses Gigabit network jumbo frames to upload data. The internal direct acquisition uses 4000 points per second with equal interval sampling.

[0046] Figure 2 The data transmission control flow chart of the system includes 4 processing steps. The FPGA side mainly includes FPGA parsing, receiving and processing the data of each port, the data receiving engine high-throughput polling receiving and storing data, and the data sending engine traffic adaptive DMA sending data; the host computer Linux side is responsible for data reception based on the Linux PACKET_MMAP receiving mechanism.

[0047] S1, FPGA analyzes, receives and processes the data from each port:

[0048] like Figure 1 As shown in the figure, in this case, the FPGA needs to receive and process 17 channels of data, of which the internal direct sampling adopts 4000 points per second with equal interval sampling. After each port of the FPGA receives the message, the FPGA uses parallel capabilities to pre-process the message and analyze whether the message has CRC errors, small frames, long frames, and message length. Figure 3 As shown, the FPGA Header of the message is written into the Header FIFO buffer, and the original message is written into the Data FIFO buffer. The FPGA Header format is defined as shown in Table 1, where the receiving time stamp is the time after the GPS B code calibration, and the self-timekeeping technology is used to achieve accurate timekeeping after B code decoding and GPS loss inside the FPGA.

[0049] Table 1. FPGA Header format definition

[0050]

[0051]

[0052] S2, FPGA data receiving engine high throughput polling receiving storage data:

[0053] The FPGA data receiving engine polls the status of the 17-port Header FIFO in real time. If it is empty, it switches to the next port. If it is not empty, there is an Ethernet message on the port. The data receiving engine reads a piece of Header information of the port and stores it in the data receiving engine RX_ENG Header FIFO. Since FIFO is first-in-first-out, the Header FIFO information of all ports is transferred from the Header FIFO of each port to the RX_ENG Header FIFO of the data receiving engine in this cycle according to the order of reception time. The process is as follows: Figure 4 shown.

[0054] At the same time, taking the 100M data channel as an example, f clk 25M, data bit width B width 4; FPGA data polling reads in a frequency-multiplied bit-width manner, select X=8, Y=64, then the data polling bandwidth is:

[0055] Bandwith=X*f clk *Y*B width =51.2Gb / s

[0056] That is, the logic master clock adopts a 200M=8*25M high-frequency clock, and the data storage buffer read port width of each of the 17 data channels adopts a high bit width of 256bit=64*4bit. The reading bandwidth of the data receiving engine can reach 51.2Gb / s, which is much larger than the 100Mb / s and 1000Mb / s bandwidths of the data channel. This enables reading data in the order in which the message data is received, thus ensuring the real-time nature of the data.

[0057] At the same time, the FPGA data receiving engine queries the status of the RX_ENG Header FIFO in real time. If it is empty, it waits. If it is not empty, it reads a piece of RX_ENG Header FIFO data and writes the information into the DDR3 ring storage area. It also extracts information such as the port and message length based on the data content, reads the data from the Data FIFO buffer of the corresponding port, and writes it into the DDR3 ring buffer. Figure 5 As shown, in this way, the read pointer of the circular buffer always lags behind the write pointer to prevent read-write conflicts and ensure data reliability.

[0058] Specifically, the ring buffer is divided equally according to the gigabit network jumbo frame length according to actual needs. Considering compatibility and data processing efficiency, this case selects a buffer storage block size of 8000 bytes, and takes 1Gbit DDR3 as an example to divide the space into 16384 ring data blocks. The FPGA data receiving engine reads data from the Data FIFO of each port and writes 8000-byte data blocks. Before writing, it determines the remaining space of the data block. If it is greater than the message data length, it switches to the next buffer and writes the current buffer data block ID and total data length to the sending engine TX_ENG Header FIFO buffer.

[0059] Specifically, the FPGA data receiving engine polling and reading data includes the following steps:

[0060] 1) Variable initialization, the initialization data includes:

[0061] N: the number of FPGA receiving data channels (including external receiving network port channels and internal direct acquisition channels). In this case, N = 17;

[0062] CHAN_ID: Current channel ID, initially 0, value range [0,16];

[0063] At the same time, the data FIFO and message information Header FIFO of the receiving buffer of each channel port are reset to 0, and the empty flags of Data FIFO and Header FIFO are 1;

[0064] 2) Each channel port of FPGA receives the message and writes it into the buffer: FPGA parses and extracts the complete message data and writes it into DataFIFO. After receiving a single frame of message, the FPGA Header information of the frame message is written into Header FIFO, and the Data FIFO and Header FIFO empty flags are automatically set to non-0;

[0065] 3) The FPGA data receiving engine detects the status of each channel buffer in real time: if the Header FIFO of a channel is not empty, it starts a polling, otherwise it waits;

[0066] 4) Polling to read data from each channel: First, check whether the Header FIFO of the current CHAN_ID channel is not empty. If it is not empty, read a piece of FPGA Header information from the Header FIFO, and read the corresponding message data from the DATA FIFO and write it into the DDR3 circular buffer according to the information. At the same time, CHAN_ID+1 switches to the next channel; if the Header FIFO of the previous CHAN_ID channel is empty, CHAN_ID+1 switches to the next channel; in particular, if (CHAN_ID+1)≥17, it means that all channels are polled once, switch to channel CHAN_ID=0, and repeat steps 2, 3 and 4 to realize data polling reception;

[0067] S3, FPGA data transmission engine traffic adaptive DMA transmission data:

[0068] The power system fault recording data is non-uniform data. When the flow is low, the total flow of all port data may be only a few megabytes. When a fault occurs, a large amount of recording data may generate a flow of thousands of megabytes. If it is simply sent directly, only one frame of data is transmitted each time, which requires frequent response processing by the host computer, and the efficiency is low.

[0069] To solve this problem, the present invention proposes to adopt a DMA transmission method based on Ethernet jumbo frames. First, the equally divided DDR3 circular buffer is written when the data is received, that is, the data to be sent is packaged into a data block of no more than 8000 bytes, and then the data block is sent in the Ethernet jumbo frame mode, which greatly improves the utilization rate of the gigabit network bandwidth and also avoids the frequent response processing of the host computer. When the data flow is high, the receiving data engine writes the current buffer data block ID and the total data length into the sending engine TX_ENG Header FIFO buffer every time a DDR3 circular data block is filled. When the data flow is low, in order to avoid excessive delay in sending the message, a timed sending mechanism is adopted, that is, FPGA provides a configurable register interface, and the CPU can set the maximum time max_wait_time allowed for a single circular buffer group frame. When the FPGA data receiving engine completes switching to a new DDR3 buffer data block, a timer is started. When the timer value is greater than max_wait_time, regardless of whether the current data block has been written, the data block is considered to be written, and the current buffer data block ID and the total data length are written into the sending engine TX_ENG Header FIFO buffer. The FPGA data transmission engine detects the status of the transmission engine TX_ENG Header FIFO buffer in real time. If it is not empty, it immediately reads a piece of data information from the TX_ENG Header FIFO buffer, and reads the book from the corresponding DDR3 buffer according to the buffer ID and data length provided by the data information, and transmits it to the host computer through the gigabit network jumbo frame. This case realizes adaptive transmission processing of different data flows by controlling the maximum write duration of a single circular buffer block, effectively improving data transmission performance.

[0070] Specifically, the traffic adaptive sending mechanism comprises the following steps:

[0071] 1) Variable initialization, the initialization data includes:

[0072] ddr_blk_id: DDR3 is divided into 16384 ring buffer data block IDs, the initial value is 0, and the value range is [0, 16383];

[0073] max_wait_time: The maximum time for framing in the 8000-byte ring buffer. The initial value is 50ms. Users can configure and adjust it in real time through the register interface provided by FPGA to the CPU.

[0074] total_byte_num: the total number of bytes written to the current buffer block, the initial value is 0;

[0075] At the same time, the transmit engine TX_ENG Header FIFO buffer is reset to 0 and the empty flag is 1;

[0076] 2) FPGA data receiving engine polls and reads data from each channel:

[0077] The FPGA data receiving engine uses polling to read the data of each channel, one frame at a time; reads the FPGA Header of the frame message of the current channel, and extracts the message length information pkt_length;

[0078] 3) Determine whether the current buffer write framing has timed out:

[0079] When the FPGA data receiving engine starts writing the first frame of message data in the current DDR3 cyclic data block, it starts a timer wait_time_cnt. When the timer value exceeds the maximum allowed value of framing waiting, that is, wait_time_cnt>max_wait_time, it means that the current data flow is low and the 8000-byte framing times out. To prevent excessive data transmission delay, the data receiving engine will end the framing of the current buffer data block when the buffer write is idle, and switch to the next cyclic data block ddr_blk_id+1; and write the current buffer data block ID and total data length into the sending engine TX_ENG Header FIFO buffer;

[0080] 4) Determine whether there is enough remaining space in the current buffer:

[0081] If pkt_length+total_byte_num<8000, it indicates that there is sufficient remaining space in the current buffer block, and the frame message is written into the current circular buffer for framing, and the total number of bytes written in the current buffer, total_byte_num, is updated to pkt_length+total_byte_num;

[0082] If pkt_length+total_byte_num is 8000, it indicates that the remaining space of the current buffer block is insufficient, the current buffer data block framing ends, and switches to the next cyclic data block ddr_blk_id+1; and the current buffer data block ID and total data length are written to the sending engine TX_ENG Header FIFO buffer;

[0083] 5) FPGA data transmission engine sends data:

[0084] The FPGA data transmission engine detects the empty flag status of the transmission engine TX_ENG Header FIFO buffer in real time. If it is not empty, it immediately reads a data message from the TX_ENG Header FIFO buffer, and reads the book from the corresponding DDR3 circular buffer according to the circular buffer block ID and data length provided by the data message, and transmits it to the host computer through the Gigabit Network jumbo frame.

[0085] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A flow-adaptive power system fault recording data acquisition method, characterized in that: include, After receiving the Ethernet message, each Ethernet port of FPGA parses it, adds FPGAHeader and stores it in the receiving buffer of each port; The FPGA data receiving engine adopts a double frequency and double bit width polling method. According to the time sequence of the completion of message reception on each Ethernet port, it reads the message frame by frame and writes it into the DDR3 circular buffer to form a data block. The FPGA data transmission engine adopts a traffic adaptive mechanism to read data blocks from the DDR3 memory and send them to the host computer through the Gigabit network port in jumbo frame DMA.

2. A flow-adaptive power system fault recording data acquisition method according to claim 1, characterized in that: The FPGAHeader includes the total frame length, message length, CRC, large and small packet flags, seconds, nanoseconds and tick counts; The FPGA Header and message data of each port message are stored separately in two FIFO buffers.

3. A flow-adaptive power system fault recording data acquisition method according to claim 1, characterized in that: The FPGA data receiving engine adopts a double-speed double-bit-width polling method including: the number of FPGA receiving data channels; the current channel ID number, which is initially 0; the message data buffer Data FIFO and the message information buffer Header FIFO are reset to 0, and the DataFIFO and Header FIFO empty flags are 1; FPGA parses and extracts complete message data and writes it into Data FIFO. After receiving a single frame message, the FPGA Header information of the current frame message is written into Header FIFO. The empty flags of the message data buffer Data FIFO and the message information buffer HeaderFIFO are automatically set to non-zero. If the Header FIFO of any channel is not empty, polling is performed to read the data of each channel. If the Header FIFO of all channels is empty, waiting is performed.

4. A flow-adaptive power system fault recording data acquisition method according to claim 1, characterized in that: The polling and reading of the data of each channel includes, firstly, detecting and judging whether the Header FIFO of the current channel ID number is not empty, and if not empty, reading a piece of FPGA Header information from the Header FIFO, and reading the corresponding message data from the Data FIFO according to the information and writing it into the DDR3 circular buffer, and at the same time, CHAN_ID+1 switches to the next channel; if the Header FIFO of the previous CHAN_ID channel is empty, CHAN_ID+1 switches to the next channel; if CHAN_ID+1≥N, all channels are polled once, switched to the channel CHAN_ID=0, and the polling process is repeated, and real-time data is polled and received; wherein, CHAN_ID represents the channel ID number, and N represents the number of data channels.

5. A flow-adaptive power system fault recording data acquisition method according to claim 1, characterized in that: The frequency doubling and bit width doubling include: the sending engine logic uses X times the data channel frequency clock X*f clk The data buffer of each data channel uses Y times the data channel width Y*B. width , then the sending engine read bandwidth is expressed as: Bandwith=X*f clk *Y*B width The data channel includes an external receiving network port channel and an internal direct acquisition channel.

6. A flow-adaptive power system fault recording data acquisition method according to claim 1, characterized in that: The traffic adaptive mechanism includes sending 8000-byte data blocks to the host computer in real time through the Gigabit network port in Ethernet jumbo frames when the traffic is high, sending the actual data length to the host computer through the Gigabit network at regular intervals when the traffic is low, and the maximum framing time during low traffic is configured through the CPU interface; DDR3 is divided into A ring buffer data block ID numbers, with an initial value of 0 and a value range of [0, A-1], where A represents the number of ring buffer blocks; the maximum framing time of the 8000-byte ring buffer, with an initial value of 50ms; the user can adjust the configuration in real time through the register interface provided by the FPGA to the CPU; The total number of bytes written into the current buffer block is initially 0. At the same time, the TX_ENG Header FIFO buffer storing the information of each data block to be sent is reset to 0, and the empty flag is 1. The FPGA data receiving engine uses polling to read the data of each channel, one frame at a time. Read the FPGA Header of the current frame message of the current channel and extract the message length information pkt_length. The FPGA data receiving engine starts a timer when the first frame of message data is written into the current DDR3 cyclic data block. When the timer value exceeds the maximum allowable value of framing waiting, wait_time_cnt>max_wait_time, the current traffic volume is low traffic, and the 8000-byte framing times out. The data receiving engine will end the framing of the current buffer data block when the buffer write is idle, and switch to the next cyclic data block ddr_blk_id+1; and write the current buffer data block ID and total data length into the TX_ENG Header FIFO, where wait_time_cnt represents the timer and max_wait_time represents the maximum allowable value of framing waiting. If pkt_length+total_byte_num<8000, the current buffer block has sufficient remaining space, write the current frame message into the current circular buffer frame, and update the total number of bytes written in the current buffer, total_byte_num, to pkt_length+total_byte_num, where pkt_length represents the length of the current message to be written, and total_byte_num represents the length of the message written in the buffer; If pkt_length+total_byte_num≥8000, the remaining space of the current buffer block is insufficient, the current buffer data block framing ends, and switches to the next cyclic data block ddr_blk_id+1; and the current buffer data block ID and total data length are written to the TX_ENG Header FIFO; The FPGA data transmission engine detects the empty flag status of the TX_ENG Header FIFO in real time. If it is not empty, it immediately reads a piece of data information from the TX_ENG Header FIFO, and reads data from the corresponding DDR3 circular buffer according to the circular buffer block ID and data length provided by the data information, and transmits it to the host computer through the Gigabit Network jumbo frame.

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